LXR linux/drivers/gpu/drm/amd/amdkfd/kfd_pm4

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef KFD_PM4_HEADERS_H_
  25#define KFD_PM4_HEADERS_H_
  26
  27#ifndef PM4_MES_HEADER_DEFINED
  28#define PM4_MES_HEADER_DEFINED
  29union PM4_MES_TYPE_3_HEADER {
  30        struct {
  31                uint32_t reserved1:8;   /* < reserved */
  32                uint32_t opcode:8;      /* < IT opcode */
  33                uint32_t count:14;      /* < number of DWORDs - 1
  34                                         * in the information body.
  35                                         */
  36                uint32_t type:2;        /* < packet identifier.
  37                                         * It should be 3 for type 3 packets
  38                                         */
  39        };
  40        uint32_t u32all;
  41};
  42#endif /* PM4_MES_HEADER_DEFINED */
  43
  44/* --------------------MES_SET_RESOURCES-------------------- */
  45
  46#ifndef PM4_MES_SET_RESOURCES_DEFINED
  47#define PM4_MES_SET_RESOURCES_DEFINED
  48enum set_resources_queue_type_enum {
  49        queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
  50        queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
  51        queue_type__mes_set_resources__hsa_debug_interface_queue = 4
  52};
  53
  54struct pm4_set_resources {
  55        union {
  56                union PM4_MES_TYPE_3_HEADER header;     /* header */
  57                uint32_t ordinal1;
  58        };
  59
  60        union {
  61                struct {
  62                        uint32_t vmid_mask:16;
  63                        uint32_t unmap_latency:8;
  64                        uint32_t reserved1:5;
  65                        enum set_resources_queue_type_enum queue_type:3;
  66                } bitfields2;
  67                uint32_t ordinal2;
  68        };
  69
  70        uint32_t queue_mask_lo;
  71        uint32_t queue_mask_hi;
  72        uint32_t gws_mask_lo;
  73        uint32_t gws_mask_hi;
  74
  75        union {
  76                struct {
  77                        uint32_t oac_mask:16;
  78                        uint32_t reserved2:16;
  79                } bitfields7;
  80                uint32_t ordinal7;
  81        };
  82
  83        union {
  84                struct {
  85                        uint32_t gds_heap_base:6;
  86                        uint32_t reserved3:5;
  87                        uint32_t gds_heap_size:6;
  88                        uint32_t reserved4:15;
  89                } bitfields8;
  90                uint32_t ordinal8;
  91        };
  92
  93};
  94#endif
  95
  96/*--------------------MES_RUN_LIST-------------------- */
  97
  98#ifndef PM4_MES_RUN_LIST_DEFINED
  99#define PM4_MES_RUN_LIST_DEFINED
 100
 101struct pm4_runlist {
 102        union {
 103                union PM4_MES_TYPE_3_HEADER header;     /* header */
 104                uint32_t ordinal1;
 105        };
 106
 107        union {
 108                struct {
 109                        uint32_t reserved1:2;
 110                        uint32_t ib_base_lo:30;
 111                } bitfields2;
 112                uint32_t ordinal2;
 113        };
 114
 115        union {
 116                struct {
 117                        uint32_t ib_base_hi:16;
 118                        uint32_t reserved2:16;
 119                } bitfields3;
 120                uint32_t ordinal3;
 121        };
 122
 123        union {
 124                struct {
 125                        uint32_t ib_size:20;
 126                        uint32_t chain:1;
 127                        uint32_t offload_polling:1;
 128                        uint32_t reserved3:1;
 129                        uint32_t valid:1;
 130                        uint32_t reserved4:8;
 131                } bitfields4;
 132                uint32_t ordinal4;
 133        };
 134
 135};
 136#endif
 137
 138/*--------------------MES_MAP_PROCESS-------------------- */
 139
 140#ifndef PM4_MES_MAP_PROCESS_DEFINED
 141#define PM4_MES_MAP_PROCESS_DEFINED
 142
 143struct pm4_map_process {
 144        union {
 145                union PM4_MES_TYPE_3_HEADER header;     /* header */
 146                uint32_t ordinal1;
 147        };
 148
 149        union {
 150                struct {
 151                        uint32_t pasid:16;
 152                        uint32_t reserved1:8;
 153                        uint32_t diq_enable:1;
 154                        uint32_t process_quantum:7;
 155                } bitfields2;
 156                uint32_t ordinal2;
 157        };
 158
 159        union {
 160                struct {
 161                        uint32_t page_table_base:28;
 162                        uint32_t reserved3:4;
 163                } bitfields3;
 164                uint32_t ordinal3;
 165        };
 166
 167        uint32_t sh_mem_bases;
 168        uint32_t sh_mem_ape1_base;
 169        uint32_t sh_mem_ape1_limit;
 170        uint32_t sh_mem_config;
 171        uint32_t gds_addr_lo;
 172        uint32_t gds_addr_hi;
 173
 174        union {
 175                struct {
 176                        uint32_t num_gws:6;
 177                        uint32_t reserved4:2;
 178                        uint32_t num_oac:4;
 179                        uint32_t reserved5:4;
 180                        uint32_t gds_size:6;
 181                        uint32_t num_queues:10;
 182                } bitfields10;
 183                uint32_t ordinal10;
 184        };
 185
 186};
 187#endif
 188
 189/*--------------------MES_MAP_QUEUES--------------------*/
 190
 191#ifndef PM4_MES_MAP_QUEUES_DEFINED
 192#define PM4_MES_MAP_QUEUES_DEFINED
 193enum map_queues_queue_sel_enum {
 194        queue_sel__mes_map_queues__map_to_specified_queue_slots = 0,
 195        queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1,
 196        queue_sel__mes_map_queues__enable_process_queues = 2
 197};
 198
 199enum map_queues_vidmem_enum {
 200        vidmem__mes_map_queues__uses_no_video_memory = 0,
 201        vidmem__mes_map_queues__uses_video_memory = 1
 202};
 203
 204enum map_queues_alloc_format_enum {
 205        alloc_format__mes_map_queues__one_per_pipe = 0,
 206        alloc_format__mes_map_queues__all_on_one_pipe = 1
 207};
 208
 209enum map_queues_engine_sel_enum {
 210        engine_sel__mes_map_queues__compute = 0,
 211        engine_sel__mes_map_queues__sdma0 = 2,
 212        engine_sel__mes_map_queues__sdma1 = 3
 213};
 214
 215struct pm4_map_queues {
 216        union {
 217                union PM4_MES_TYPE_3_HEADER header;     /* header */
 218                uint32_t ordinal1;
 219        };
 220
 221        union {
 222                struct {
 223                        uint32_t reserved1:4;
 224                        enum map_queues_queue_sel_enum queue_sel:2;
 225                        uint32_t reserved2:2;
 226                        uint32_t vmid:4;
 227                        uint32_t reserved3:4;
 228                        enum map_queues_vidmem_enum vidmem:2;
 229                        uint32_t reserved4:6;
 230                        enum map_queues_alloc_format_enum alloc_format:2;
 231                        enum map_queues_engine_sel_enum engine_sel:3;
 232                        uint32_t num_queues:3;
 233                } bitfields2;
 234                uint32_t ordinal2;
 235        };
 236
 237        struct {
 238                union {
 239                        struct {
 240                                uint32_t is_static:1;
 241                                uint32_t reserved5:1;
 242                                uint32_t doorbell_offset:21;
 243                                uint32_t reserved6:3;
 244                                uint32_t queue:6;
 245                        } bitfields3;
 246                        uint32_t ordinal3;
 247                };
 248
 249                uint32_t mqd_addr_lo;
 250                uint32_t mqd_addr_hi;
 251                uint32_t wptr_addr_lo;
 252                uint32_t wptr_addr_hi;
 253
 254        } mes_map_queues_ordinals[1];   /* 1..N of these ordinal groups */
 255
 256};
 257#endif
 258
 259/*--------------------MES_QUERY_STATUS--------------------*/
 260
 261#ifndef PM4_MES_QUERY_STATUS_DEFINED
 262#define PM4_MES_QUERY_STATUS_DEFINED
 263enum query_status_interrupt_sel_enum {
 264        interrupt_sel__mes_query_status__completion_status = 0,
 265        interrupt_sel__mes_query_status__process_status = 1,
 266        interrupt_sel__mes_query_status__queue_status = 2
 267};
 268
 269enum query_status_command_enum {
 270        command__mes_query_status__interrupt_only = 0,
 271        command__mes_query_status__fence_only_immediate = 1,
 272        command__mes_query_status__fence_only_after_write_ack = 2,
 273        command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
 274};
 275
 276enum query_status_engine_sel_enum {
 277        engine_sel__mes_query_status__compute = 0,
 278        engine_sel__mes_query_status__sdma0_queue = 2,
 279        engine_sel__mes_query_status__sdma1_queue = 3
 280};
 281
 282struct pm4_query_status {
 283        union {
 284                union PM4_MES_TYPE_3_HEADER header;     /* header */
 285                uint32_t ordinal1;
 286        };
 287
 288        union {
 289                struct {
 290                        uint32_t context_id:28;
 291                        enum query_status_interrupt_sel_enum interrupt_sel:2;
 292                        enum query_status_command_enum command:2;
 293                } bitfields2;
 294                uint32_t ordinal2;
 295        };
 296
 297        union {
 298                struct {
 299                        uint32_t pasid:16;
 300                        uint32_t reserved1:16;
 301                } bitfields3a;
 302                struct {
 303                        uint32_t reserved2:2;
 304                        uint32_t doorbell_offset:21;
 305                        uint32_t reserved3:3;
 306                        enum query_status_engine_sel_enum engine_sel:3;
 307                        uint32_t reserved4:3;
 308                } bitfields3b;
 309                uint32_t ordinal3;
 310        };
 311
 312        uint32_t addr_lo;
 313        uint32_t addr_hi;
 314        uint32_t data_lo;
 315        uint32_t data_hi;
 316};
 317#endif
 318
 319/*--------------------MES_UNMAP_QUEUES--------------------*/
 320
 321#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
 322#define PM4_MES_UNMAP_QUEUES_DEFINED
 323enum unmap_queues_action_enum {
 324        action__mes_unmap_queues__preempt_queues = 0,
 325        action__mes_unmap_queues__reset_queues = 1,
 326        action__mes_unmap_queues__disable_process_queues = 2
 327};
 328
 329enum unmap_queues_queue_sel_enum {
 330        queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
 331        queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
 332        queue_sel__mes_unmap_queues__perform_request_on_all_active_queues = 2,
 333        queue_sel__mes_unmap_queues__perform_request_on_dynamic_queues_only = 3
 334};
 335
 336enum unmap_queues_engine_sel_enum {
 337        engine_sel__mes_unmap_queues__compute = 0,
 338        engine_sel__mes_unmap_queues__sdma0 = 2,
 339        engine_sel__mes_unmap_queues__sdma1 = 3
 340};
 341
 342struct pm4_unmap_queues {
 343        union {
 344                union PM4_MES_TYPE_3_HEADER header;     /* header */
 345                uint32_t ordinal1;
 346        };
 347
 348        union {
 349                struct {
 350                        enum unmap_queues_action_enum action:2;
 351                        uint32_t reserved1:2;
 352                        enum unmap_queues_queue_sel_enum queue_sel:2;
 353                        uint32_t reserved2:20;
 354                        enum unmap_queues_engine_sel_enum engine_sel:3;
 355                        uint32_t num_queues:3;
 356                } bitfields2;
 357                uint32_t ordinal2;
 358        };
 359
 360        union {
 361                struct {
 362                        uint32_t pasid:16;
 363                        uint32_t reserved3:16;
 364                } bitfields3a;
 365                struct {
 366                        uint32_t reserved4:2;
 367                        uint32_t doorbell_offset0:21;
 368                        uint32_t reserved5:9;
 369                } bitfields3b;
 370                uint32_t ordinal3;
 371        };
 372
 373        union {
 374                struct {
 375                        uint32_t reserved6:2;
 376                        uint32_t doorbell_offset1:21;
 377                        uint32_t reserved7:9;
 378                } bitfields4;
 379                uint32_t ordinal4;
 380        };
 381
 382        union {
 383                struct {
 384                        uint32_t reserved8:2;
 385                        uint32_t doorbell_offset2:21;
 386                        uint32_t reserved9:9;
 387                } bitfields5;
 388                uint32_t ordinal5;
 389        };
 390
 391        union {
 392                struct {
 393                        uint32_t reserved10:2;
 394                        uint32_t doorbell_offset3:21;
 395                        uint32_t reserved11:9;
 396                } bitfields6;
 397                uint32_t ordinal6;
 398        };
 399
 400};
 401#endif
 402
 403enum {
 404        CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014
 405};
 406
 407#endif /* KFD_PM4_HEADERS_H_ */
 408