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8
9#include <linux/errno.h>
10#include <linux/fs.h>
11#include <linux/major.h>
12#include <asm/io.h>
13#include <linux/delay.h>
14#include <linux/kernel.h>
15#include <linux/signal.h>
16#include <linux/slab.h>
17#include <linux/mm.h>
18#include <linux/mman.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timer.h>
22#include <linux/wait.h>
23#include <linux/isdnif.h>
24#include <linux/tty.h>
25#include <linux/serial_reg.h>
26#include <linux/netdevice.h>
27
28#define ERROR_STATISTIC
29
30#define REQUEST 0
31#define CONFIRM 1
32#define INDICATION 2
33#define RESPONSE 3
34
35#define HW_ENABLE 0x0000
36#define HW_RESET 0x0004
37#define HW_POWERUP 0x0008
38#define HW_ACTIVATE 0x0010
39#define HW_DEACTIVATE 0x0018
40
41#define HW_INFO1 0x0010
42#define HW_INFO2 0x0020
43#define HW_INFO3 0x0030
44#define HW_INFO4 0x0040
45#define HW_INFO4_P8 0x0040
46#define HW_INFO4_P10 0x0048
47#define HW_RSYNC 0x0060
48#define HW_TESTLOOP 0x0070
49#define CARD_RESET 0x00F0
50#define CARD_INIT 0x00F2
51#define CARD_RELEASE 0x00F3
52#define CARD_TEST 0x00F4
53#define CARD_AUX_IND 0x00F5
54
55#define PH_ACTIVATE 0x0100
56#define PH_DEACTIVATE 0x0110
57#define PH_DATA 0x0120
58#define PH_PULL 0x0130
59#define PH_TESTLOOP 0x0140
60#define PH_PAUSE 0x0150
61#define MPH_ACTIVATE 0x0180
62#define MPH_DEACTIVATE 0x0190
63#define MPH_INFORMATION 0x01A0
64
65#define DL_ESTABLISH 0x0200
66#define DL_RELEASE 0x0210
67#define DL_DATA 0x0220
68#define DL_FLUSH 0x0224
69#define DL_UNIT_DATA 0x0230
70
71#define MDL_BC_RELEASE 0x0278
72#define MDL_BC_ASSIGN 0x027C
73#define MDL_ASSIGN 0x0280
74#define MDL_REMOVE 0x0284
75#define MDL_ERROR 0x0288
76#define MDL_INFO_SETUP 0x02E0
77#define MDL_INFO_CONN 0x02E4
78#define MDL_INFO_REL 0x02E8
79
80#define CC_SETUP 0x0300
81#define CC_RESUME 0x0304
82#define CC_MORE_INFO 0x0310
83#define CC_IGNORE 0x0320
84#define CC_REJECT 0x0324
85#define CC_SETUP_COMPL 0x0330
86#define CC_PROCEEDING 0x0340
87#define CC_ALERTING 0x0344
88#define CC_PROGRESS 0x0348
89#define CC_CONNECT 0x0350
90#define CC_CHARGE 0x0354
91#define CC_NOTIFY 0x0358
92#define CC_DISCONNECT 0x0360
93#define CC_RELEASE 0x0368
94#define CC_SUSPEND 0x0370
95#define CC_PROCEED_SEND 0x0374
96#define CC_REDIR 0x0378
97#define CC_T302 0x0382
98#define CC_T303 0x0383
99#define CC_T304 0x0384
100#define CC_T305 0x0385
101#define CC_T308_1 0x0388
102#define CC_T308_2 0x038A
103#define CC_T309 0x0309
104#define CC_T310 0x0390
105#define CC_T313 0x0393
106#define CC_T318 0x0398
107#define CC_T319 0x0399
108#define CC_TSPID 0x03A0
109#define CC_NOSETUP_RSP 0x03E0
110#define CC_SETUP_ERR 0x03E1
111#define CC_SUSPEND_ERR 0x03E2
112#define CC_RESUME_ERR 0x03E3
113#define CC_CONNECT_ERR 0x03E4
114#define CC_RELEASE_ERR 0x03E5
115#define CC_RESTART 0x03F4
116#define CC_TDSS1_IO 0x13F4
117#define CC_TNI1_IO 0x13F5
118
119
120#define MAX_WAITING_CALLS 2
121
122
123#ifdef __KERNEL__
124
125extern const char *CardType[];
126extern int nrcards;
127
128extern const char *l1_revision;
129extern const char *l2_revision;
130extern const char *l3_revision;
131extern const char *lli_revision;
132extern const char *tei_revision;
133
134
135#ifdef CONFIG_HISAX_EURO
136#define l3dss1_process
137#include "l3dss1.h"
138#undef l3dss1_process
139#endif
140
141#ifdef CONFIG_HISAX_NI1
142#define l3ni1_process
143#include "l3ni1.h"
144#undef l3ni1_process
145#endif
146
147#define MAX_DFRAME_LEN 260
148#define MAX_DFRAME_LEN_L1 300
149#define HSCX_BUFMAX 4096
150#define MAX_DATA_SIZE (HSCX_BUFMAX - 4)
151#define MAX_DATA_MEM (HSCX_BUFMAX + 64)
152#define RAW_BUFMAX (((HSCX_BUFMAX * 6) / 5) + 5)
153#define MAX_HEADER_LEN 4
154#define MAX_WINDOW 8
155#define MAX_MON_FRAME 32
156#define MAX_DLOG_SPACE 2048
157#define MAX_BLOG_SPACE 256
158
159
160#define I4L_IRQ_FLAG 0
161
162
163
164
165
166struct FsmInst;
167
168typedef void (*FSMFNPTR)(struct FsmInst *, int, void *);
169
170struct Fsm {
171 FSMFNPTR *jumpmatrix;
172 int state_count, event_count;
173 char **strEvent, **strState;
174};
175
176struct FsmInst {
177 struct Fsm *fsm;
178 int state;
179 int debug;
180 void *userdata;
181 int userint;
182 void (*printdebug) (struct FsmInst *, char *, ...);
183};
184
185struct FsmNode {
186 int state, event;
187 void (*routine) (struct FsmInst *, int, void *);
188};
189
190struct FsmTimer {
191 struct FsmInst *fi;
192 struct timer_list tl;
193 int event;
194 void *arg;
195};
196
197struct L3Timer {
198 struct l3_process *pc;
199 struct timer_list tl;
200 int event;
201};
202
203#define FLG_L1_ACTIVATING 1
204#define FLG_L1_ACTIVATED 2
205#define FLG_L1_DEACTTIMER 3
206#define FLG_L1_ACTTIMER 4
207#define FLG_L1_T3RUN 5
208#define FLG_L1_PULL_REQ 6
209#define FLG_L1_UINT 7
210
211struct Layer1 {
212 void *hardware;
213 struct BCState *bcs;
214 struct PStack **stlistp;
215 unsigned long Flags;
216 struct FsmInst l1m;
217 struct FsmTimer timer;
218 void (*l1l2) (struct PStack *, int, void *);
219 void (*l1hw) (struct PStack *, int, void *);
220 void (*l1tei) (struct PStack *, int, void *);
221 int mode, bc;
222 int delay;
223};
224
225#define GROUP_TEI 127
226#define TEI_SAPI 63
227#define CTRL_SAPI 0
228#define PACKET_NOACK 7
229
230
231
232#define FLG_LAPB 0
233#define FLG_LAPD 1
234#define FLG_ORIG 2
235#define FLG_MOD128 3
236#define FLG_PEND_REL 4
237#define FLG_L3_INIT 5
238#define FLG_T200_RUN 6
239#define FLG_ACK_PEND 7
240#define FLG_REJEXC 8
241#define FLG_OWN_BUSY 9
242#define FLG_PEER_BUSY 10
243#define FLG_DCHAN_BUSY 11
244#define FLG_L1_ACTIV 12
245#define FLG_ESTAB_PEND 13
246#define FLG_PTP 14
247#define FLG_FIXED_TEI 15
248#define FLG_L2BLOCK 16
249
250struct Layer2 {
251 int tei;
252 int sap;
253 int maxlen;
254 u_long flag;
255 spinlock_t lock;
256 u_int vs, va, vr;
257 int rc;
258 unsigned int window;
259 unsigned int sow;
260 struct sk_buff *windowar[MAX_WINDOW];
261 struct sk_buff_head i_queue;
262 struct sk_buff_head ui_queue;
263 void (*l2l1) (struct PStack *, int, void *);
264 void (*l2l3) (struct PStack *, int, void *);
265 void (*l2tei) (struct PStack *, int, void *);
266 struct FsmInst l2m;
267 struct FsmTimer t200, t203;
268 int T200, N200, T203;
269 int debug;
270 char debug_id[16];
271};
272
273struct Layer3 {
274 void (*l3l4) (struct PStack *, int, void *);
275 void (*l3ml3) (struct PStack *, int, void *);
276 void (*l3l2) (struct PStack *, int, void *);
277 struct FsmInst l3m;
278 struct FsmTimer l3m_timer;
279 struct sk_buff_head squeue;
280 struct l3_process *proc;
281 struct l3_process *global;
282 int N303;
283 int debug;
284 char debug_id[8];
285};
286
287struct LLInterface {
288 void (*l4l3) (struct PStack *, int, void *);
289 int (*l4l3_proto) (struct PStack *, isdn_ctrl *);
290 void *userdata;
291 u_long flag;
292};
293
294#define FLG_LLI_L1WAKEUP 1
295#define FLG_LLI_L2WAKEUP 2
296
297struct Management {
298 int ri;
299 struct FsmInst tei_m;
300 struct FsmTimer t202;
301 int T202, N202, debug;
302 void (*layer) (struct PStack *, int, void *);
303};
304
305#define NO_CAUSE 254
306
307struct Param {
308 u_char cause;
309 u_char loc;
310 u_char diag[6];
311 int bchannel;
312 int chargeinfo;
313 int spv;
314 setup_parm setup;
315 u_char moderate;
316};
317
318
319struct PStack {
320 struct PStack *next;
321 struct Layer1 l1;
322 struct Layer2 l2;
323 struct Layer3 l3;
324 struct LLInterface lli;
325 struct Management ma;
326 int protocol;
327
328
329 union
330 { u_char uuuu;
331#ifdef CONFIG_HISAX_EURO
332 dss1_stk_priv dss1;
333#endif
334#ifdef CONFIG_HISAX_NI1
335 ni1_stk_priv ni1;
336#endif
337 } prot;
338};
339
340struct l3_process {
341 int callref;
342 int state;
343 struct L3Timer timer;
344 int N303;
345 int debug;
346 struct Param para;
347 struct Channel *chan;
348 struct PStack *st;
349 struct l3_process *next;
350 ulong redir_result;
351
352
353 union
354 { u_char uuuu;
355#ifdef CONFIG_HISAX_EURO
356 dss1_proc_priv dss1;
357#endif
358#ifdef CONFIG_HISAX_NI1
359 ni1_proc_priv ni1;
360#endif
361 } prot;
362};
363
364struct hscx_hw {
365 int hscx;
366 int rcvidx;
367 int count;
368 u_char *rcvbuf;
369 u_char tsaxr0;
370 u_char tsaxr1;
371};
372
373struct w6692B_hw {
374 int bchan;
375 int rcvidx;
376 int count;
377 u_char *rcvbuf;
378};
379
380struct isar_reg {
381 unsigned long Flags;
382 volatile u_char bstat;
383 volatile u_char iis;
384 volatile u_char cmsb;
385 volatile u_char clsb;
386 volatile u_char par[8];
387};
388
389struct isar_hw {
390 int dpath;
391 int rcvidx;
392 int txcnt;
393 int mml;
394 u_char state;
395 u_char cmd;
396 u_char mod;
397 u_char newcmd;
398 u_char newmod;
399 char try_mod;
400 struct timer_list ftimer;
401 u_char *rcvbuf;
402 u_char conmsg[16];
403 struct isar_reg *reg;
404};
405
406struct hdlc_stat_reg {
407#ifdef __BIG_ENDIAN
408 u_char fill;
409 u_char mode;
410 u_char xml;
411 u_char cmd;
412#else
413 u_char cmd;
414 u_char xml;
415 u_char mode;
416 u_char fill;
417#endif
418} __attribute__((packed));
419
420struct hdlc_hw {
421 union {
422 u_int ctrl;
423 struct hdlc_stat_reg sr;
424 } ctrl;
425 u_int stat;
426 int rcvidx;
427 int count;
428 u_char *rcvbuf;
429};
430
431struct hfcB_hw {
432 unsigned int *send;
433 int f1;
434 int f2;
435};
436
437struct tiger_hw {
438 u_int *send;
439 u_int *s_irq;
440 u_int *s_end;
441 u_int *sendp;
442 u_int *rec;
443 int free;
444 u_char *rcvbuf;
445 u_char *sendbuf;
446 u_char *sp;
447 int sendcnt;
448 u_int s_tot;
449 u_int r_bitcnt;
450 u_int r_tot;
451 u_int r_err;
452 u_int r_fcs;
453 u_char r_state;
454 u_char r_one;
455 u_char r_val;
456 u_char s_state;
457};
458
459struct amd7930_hw {
460 u_char *tx_buff;
461 u_char *rv_buff;
462 int rv_buff_in;
463 int rv_buff_out;
464 struct sk_buff *rv_skb;
465 struct hdlc_state *hdlc_state;
466 struct work_struct tq_rcv;
467 struct work_struct tq_xmt;
468};
469
470#define BC_FLG_INIT 1
471#define BC_FLG_ACTIV 2
472#define BC_FLG_BUSY 3
473#define BC_FLG_NOFRAME 4
474#define BC_FLG_HALF 5
475#define BC_FLG_EMPTY 6
476#define BC_FLG_ORIG 7
477#define BC_FLG_DLEETX 8
478#define BC_FLG_LASTDLE 9
479#define BC_FLG_FIRST 10
480#define BC_FLG_LASTDATA 11
481#define BC_FLG_NMD_DATA 12
482#define BC_FLG_FTI_RUN 13
483#define BC_FLG_LL_OK 14
484#define BC_FLG_LL_CONN 15
485#define BC_FLG_FTI_FTS 16
486#define BC_FLG_FRH_WAIT 17
487
488#define L1_MODE_NULL 0
489#define L1_MODE_TRANS 1
490#define L1_MODE_HDLC 2
491#define L1_MODE_EXTRN 3
492#define L1_MODE_HDLC_56K 4
493#define L1_MODE_MODEM 7
494#define L1_MODE_V32 8
495#define L1_MODE_FAX 9
496
497struct BCState {
498 int channel;
499 int mode;
500 u_long Flag;
501 struct IsdnCardState *cs;
502 int tx_cnt;
503 struct sk_buff *tx_skb;
504 struct sk_buff_head rqueue;
505 struct sk_buff_head squeue;
506 int ackcnt;
507 spinlock_t aclock;
508 struct PStack *st;
509 u_char *blog;
510 u_char *conmsg;
511 struct timer_list transbusy;
512 struct work_struct tqueue;
513 u_long event;
514 int (*BC_SetStack) (struct PStack *, struct BCState *);
515 void (*BC_Close) (struct BCState *);
516#ifdef ERROR_STATISTIC
517 int err_crc;
518 int err_tx;
519 int err_rdo;
520 int err_inv;
521#endif
522 union {
523 struct hscx_hw hscx;
524 struct hdlc_hw hdlc;
525 struct isar_hw isar;
526 struct hfcB_hw hfc;
527 struct tiger_hw tiger;
528 struct amd7930_hw amd7930;
529 struct w6692B_hw w6692;
530 struct hisax_b_if *b_if;
531 } hw;
532};
533
534struct Channel {
535 struct PStack *b_st, *d_st;
536 struct IsdnCardState *cs;
537 struct BCState *bcs;
538 int chan;
539 int incoming;
540 struct FsmInst fi;
541 struct FsmTimer drel_timer, dial_timer;
542 int debug;
543 int l2_protocol, l2_active_protocol;
544 int l3_protocol;
545 int data_open;
546 struct l3_process *proc;
547 setup_parm setup;
548 u_long Flags;
549 int leased;
550};
551
552struct elsa_hw {
553 struct pci_dev *dev;
554 unsigned long base;
555 unsigned int cfg;
556 unsigned int ctrl;
557 unsigned int ale;
558 unsigned int isac;
559 unsigned int itac;
560 unsigned int hscx;
561 unsigned int trig;
562 unsigned int timer;
563 unsigned int counter;
564 unsigned int status;
565 struct timer_list tl;
566 unsigned int MFlag;
567 struct BCState *bcs;
568 u_char *transbuf;
569 u_char *rcvbuf;
570 unsigned int transp;
571 unsigned int rcvp;
572 unsigned int transcnt;
573 unsigned int rcvcnt;
574 u_char IER;
575 u_char FCR;
576 u_char LCR;
577 u_char MCR;
578 u_char ctrl_reg;
579};
580
581struct teles3_hw {
582 unsigned int cfg_reg;
583 signed int isac;
584 signed int hscx[2];
585 signed int isacfifo;
586 signed int hscxfifo[2];
587};
588
589struct teles0_hw {
590 unsigned int cfg_reg;
591 void __iomem *membase;
592 unsigned long phymem;
593};
594
595struct avm_hw {
596 unsigned int cfg_reg;
597 unsigned int isac;
598 unsigned int hscx[2];
599 unsigned int isacfifo;
600 unsigned int hscxfifo[2];
601 unsigned int counter;
602 struct pci_dev *dev;
603};
604
605struct ix1_hw {
606 unsigned int cfg_reg;
607 unsigned int isac_ale;
608 unsigned int isac;
609 unsigned int hscx_ale;
610 unsigned int hscx;
611};
612
613struct diva_hw {
614 unsigned long cfg_reg;
615 unsigned long pci_cfg;
616 unsigned int ctrl;
617 unsigned long isac_adr;
618 unsigned int isac;
619 unsigned long hscx_adr;
620 unsigned int hscx;
621 unsigned int status;
622 struct timer_list tl;
623 u_char ctrl_reg;
624 struct pci_dev *dev;
625};
626
627struct asus_hw {
628 unsigned int cfg_reg;
629 unsigned int adr;
630 unsigned int isac;
631 unsigned int hscx;
632 unsigned int u7;
633 unsigned int pots;
634};
635
636
637struct hfc_hw {
638 unsigned int addr;
639 unsigned int fifosize;
640 unsigned char cirm;
641 unsigned char ctmt;
642 unsigned char cip;
643 u_char isac_spcr;
644 struct timer_list timer;
645};
646
647struct sedl_hw {
648 unsigned int cfg_reg;
649 unsigned int adr;
650 unsigned int isac;
651 unsigned int hscx;
652 unsigned int reset_on;
653 unsigned int reset_off;
654 struct isar_reg isar;
655 unsigned int chip;
656 unsigned int bus;
657 struct pci_dev *dev;
658};
659
660struct spt_hw {
661 unsigned int cfg_reg;
662 unsigned int isac;
663 unsigned int hscx[2];
664 unsigned char res_irq;
665};
666
667struct mic_hw {
668 unsigned int cfg_reg;
669 unsigned int adr;
670 unsigned int isac;
671 unsigned int hscx;
672};
673
674struct njet_hw {
675 unsigned long base;
676 unsigned int isac;
677 unsigned int auxa;
678 unsigned char auxd;
679 unsigned char dmactrl;
680 unsigned char ctrl_reg;
681 unsigned char irqmask0;
682 unsigned char irqstat0;
683 unsigned char last_is0;
684 struct pci_dev *dev;
685};
686
687struct hfcPCI_hw {
688 unsigned char cirm;
689 unsigned char ctmt;
690 unsigned char conn;
691 unsigned char mst_m;
692 unsigned char int_m1;
693 unsigned char int_m2;
694 unsigned char int_s1;
695 unsigned char sctrl;
696 unsigned char sctrl_r;
697 unsigned char sctrl_e;
698 unsigned char trm;
699 unsigned char stat;
700 unsigned char fifo;
701 unsigned char fifo_en;
702 unsigned char bswapped;
703 unsigned char nt_mode;
704 int nt_timer;
705 struct pci_dev *dev;
706 unsigned char *pci_io;
707 dma_addr_t dma;
708 void *fifos;
709 int last_bfifo_cnt[2];
710 struct timer_list timer;
711};
712
713struct hfcSX_hw {
714 unsigned long base;
715 unsigned char cirm;
716 unsigned char ctmt;
717 unsigned char conn;
718 unsigned char mst_m;
719 unsigned char int_m1;
720 unsigned char int_m2;
721 unsigned char int_s1;
722 unsigned char sctrl;
723 unsigned char sctrl_r;
724 unsigned char sctrl_e;
725 unsigned char trm;
726 unsigned char stat;
727 unsigned char fifo;
728 unsigned char bswapped;
729 unsigned char nt_mode;
730 unsigned char chip;
731 int b_fifo_size;
732 unsigned char last_fifo;
733 void *extra;
734 int nt_timer;
735 struct timer_list timer;
736};
737
738struct hfcD_hw {
739 unsigned int addr;
740 unsigned int bfifosize;
741 unsigned int dfifosize;
742 unsigned char cirm;
743 unsigned char ctmt;
744 unsigned char cip;
745 unsigned char conn;
746 unsigned char mst_m;
747 unsigned char int_m1;
748 unsigned char int_m2;
749 unsigned char int_s1;
750 unsigned char sctrl;
751 unsigned char stat;
752 unsigned char fifo;
753 unsigned char f1;
754 unsigned char f2;
755 unsigned int *send;
756 struct timer_list timer;
757};
758
759struct isurf_hw {
760 unsigned int reset;
761 unsigned long phymem;
762 void __iomem *isac;
763 void __iomem *isar;
764 struct isar_reg isar_r;
765};
766
767struct saphir_hw {
768 struct pci_dev *dev;
769 unsigned int cfg_reg;
770 unsigned int ale;
771 unsigned int isac;
772 unsigned int hscx;
773 struct timer_list timer;
774};
775
776struct bkm_hw {
777 struct pci_dev *dev;
778 unsigned long base;
779
780 unsigned long isac_adr;
781 unsigned int isac_ale;
782 unsigned long jade_adr;
783 unsigned int jade_ale;
784
785 unsigned long plx_adr;
786 unsigned long data_adr;
787};
788
789struct gazel_hw {
790 struct pci_dev *dev;
791 unsigned int cfg_reg;
792 unsigned int pciaddr[2];
793 signed int ipac;
794 signed int isac;
795 signed int hscx[2];
796 signed int isacfifo;
797 signed int hscxfifo[2];
798 unsigned char timeslot;
799 unsigned char iom2;
800};
801
802struct w6692_hw {
803 struct pci_dev *dev;
804 unsigned int iobase;
805 struct timer_list timer;
806};
807
808struct arcofi_msg {
809 struct arcofi_msg *next;
810 u_char receive;
811 u_char len;
812 u_char msg[10];
813};
814
815struct isac_chip {
816 int ph_state;
817 u_char *mon_tx;
818 u_char *mon_rx;
819 int mon_txp;
820 int mon_txc;
821 int mon_rxp;
822 struct arcofi_msg *arcofi_list;
823 struct timer_list arcofitimer;
824 wait_queue_head_t arcofi_wait;
825 u_char arcofi_bc;
826 u_char arcofi_state;
827 u_char mocr;
828 u_char adf2;
829};
830
831struct hfcd_chip {
832 int ph_state;
833};
834
835struct hfcpci_chip {
836 int ph_state;
837};
838
839struct hfcsx_chip {
840 int ph_state;
841};
842
843struct w6692_chip {
844 int ph_state;
845};
846
847struct amd7930_chip {
848 u_char lmr1;
849 u_char ph_state;
850 u_char old_state;
851 u_char flg_t3;
852 unsigned int tx_xmtlen;
853 struct timer_list timer3;
854 void (*ph_command) (struct IsdnCardState *, u_char, char *);
855 void (*setIrqMask) (struct IsdnCardState *, u_char);
856};
857
858struct icc_chip {
859 int ph_state;
860 u_char *mon_tx;
861 u_char *mon_rx;
862 int mon_txp;
863 int mon_txc;
864 int mon_rxp;
865 struct arcofi_msg *arcofi_list;
866 struct timer_list arcofitimer;
867 wait_queue_head_t arcofi_wait;
868 u_char arcofi_bc;
869 u_char arcofi_state;
870 u_char mocr;
871 u_char adf2;
872};
873
874#define HW_IOM1 0
875#define HW_IPAC 1
876#define HW_ISAR 2
877#define HW_ARCOFI 3
878#define FLG_TWO_DCHAN 4
879#define FLG_L1_DBUSY 5
880#define FLG_DBUSY_TIMER 6
881#define FLG_LOCK_ATOMIC 7
882#define FLG_ARCOFI_TIMER 8
883#define FLG_ARCOFI_ERROR 9
884#define FLG_HW_L1_UINT 10
885
886struct IsdnCardState {
887 spinlock_t lock;
888 u_char typ;
889 u_char subtyp;
890 int protocol;
891 u_int irq;
892 u_long irq_flags;
893 u_long HW_Flags;
894 int *busy_flag;
895 int chanlimit;
896 int logecho;
897 union {
898 struct elsa_hw elsa;
899 struct teles0_hw teles0;
900 struct teles3_hw teles3;
901 struct avm_hw avm;
902 struct ix1_hw ix1;
903 struct diva_hw diva;
904 struct asus_hw asus;
905 struct hfc_hw hfc;
906 struct sedl_hw sedl;
907 struct spt_hw spt;
908 struct mic_hw mic;
909 struct njet_hw njet;
910 struct hfcD_hw hfcD;
911 struct hfcPCI_hw hfcpci;
912 struct hfcSX_hw hfcsx;
913 struct ix1_hw niccy;
914 struct isurf_hw isurf;
915 struct saphir_hw saphir;
916 struct bkm_hw ax;
917 struct gazel_hw gazel;
918 struct w6692_hw w6692;
919 struct hisax_d_if *hisax_d_if;
920 } hw;
921 int myid;
922 isdn_if iif;
923 spinlock_t statlock;
924 u_char *status_buf;
925 u_char *status_read;
926 u_char *status_write;
927 u_char *status_end;
928 u_char (*readisac) (struct IsdnCardState *, u_char);
929 void (*writeisac) (struct IsdnCardState *, u_char, u_char);
930 void (*readisacfifo) (struct IsdnCardState *, u_char *, int);
931 void (*writeisacfifo) (struct IsdnCardState *, u_char *, int);
932 u_char (*BC_Read_Reg) (struct IsdnCardState *, int, u_char);
933 void (*BC_Write_Reg) (struct IsdnCardState *, int, u_char, u_char);
934 void (*BC_Send_Data) (struct BCState *);
935 int (*cardmsg) (struct IsdnCardState *, int, void *);
936 void (*setstack_d) (struct PStack *, struct IsdnCardState *);
937 void (*DC_Close) (struct IsdnCardState *);
938 irq_handler_t irq_func;
939 int (*auxcmd) (struct IsdnCardState *, isdn_ctrl *);
940 struct Channel channel[2 + MAX_WAITING_CALLS];
941 struct BCState bcs[2 + MAX_WAITING_CALLS];
942 struct PStack *stlist;
943 struct sk_buff_head rq, sq;
944 int cardnr;
945 char *dlog;
946 int debug;
947 union {
948 struct isac_chip isac;
949 struct hfcd_chip hfcd;
950 struct hfcpci_chip hfcpci;
951 struct hfcsx_chip hfcsx;
952 struct w6692_chip w6692;
953 struct amd7930_chip amd7930;
954 struct icc_chip icc;
955 } dc;
956 u_char *rcvbuf;
957 int rcvidx;
958 struct sk_buff *tx_skb;
959 int tx_cnt;
960 u_long event;
961 struct work_struct tqueue;
962 struct timer_list dbusytimer;
963 unsigned int irq_cnt;
964#ifdef ERROR_STATISTIC
965 int err_crc;
966 int err_tx;
967 int err_rx;
968#endif
969};
970
971
972#define schedule_event(s, ev) do { test_and_set_bit(ev, &s->event); schedule_work(&s->tqueue); } while (0)
973
974#define MON0_RX 1
975#define MON1_RX 2
976#define MON0_TX 4
977#define MON1_TX 8
978
979
980#ifdef ISDN_CHIP_ISAC
981#undef ISDN_CHIP_ISAC
982#endif
983
984#ifdef CONFIG_HISAX_16_0
985#define CARD_TELES0 1
986#ifndef ISDN_CHIP_ISAC
987#define ISDN_CHIP_ISAC 1
988#endif
989#else
990#define CARD_TELES0 0
991#endif
992
993#ifdef CONFIG_HISAX_16_3
994#define CARD_TELES3 1
995#ifndef ISDN_CHIP_ISAC
996#define ISDN_CHIP_ISAC 1
997#endif
998#else
999#define CARD_TELES3 0
1000#endif
1001
1002#ifdef CONFIG_HISAX_TELESPCI
1003#define CARD_TELESPCI 1
1004#ifndef ISDN_CHIP_ISAC
1005#define ISDN_CHIP_ISAC 1
1006#endif
1007#else
1008#define CARD_TELESPCI 0
1009#endif
1010
1011#ifdef CONFIG_HISAX_AVM_A1
1012#define CARD_AVM_A1 1
1013#ifndef ISDN_CHIP_ISAC
1014#define ISDN_CHIP_ISAC 1
1015#endif
1016#else
1017#define CARD_AVM_A1 0
1018#endif
1019
1020#ifdef CONFIG_HISAX_AVM_A1_PCMCIA
1021#define CARD_AVM_A1_PCMCIA 1
1022#ifndef ISDN_CHIP_ISAC
1023#define ISDN_CHIP_ISAC 1
1024#endif
1025#else
1026#define CARD_AVM_A1_PCMCIA 0
1027#endif
1028
1029#ifdef CONFIG_HISAX_FRITZPCI
1030#define CARD_FRITZPCI 1
1031#ifndef ISDN_CHIP_ISAC
1032#define ISDN_CHIP_ISAC 1
1033#endif
1034#else
1035#define CARD_FRITZPCI 0
1036#endif
1037
1038#ifdef CONFIG_HISAX_ELSA
1039#define CARD_ELSA 1
1040#ifndef ISDN_CHIP_ISAC
1041#define ISDN_CHIP_ISAC 1
1042#endif
1043#else
1044#define CARD_ELSA 0
1045#endif
1046
1047#ifdef CONFIG_HISAX_IX1MICROR2
1048#define CARD_IX1MICROR2 1
1049#ifndef ISDN_CHIP_ISAC
1050#define ISDN_CHIP_ISAC 1
1051#endif
1052#else
1053#define CARD_IX1MICROR2 0
1054#endif
1055
1056#ifdef CONFIG_HISAX_DIEHLDIVA
1057#define CARD_DIEHLDIVA 1
1058#ifndef ISDN_CHIP_ISAC
1059#define ISDN_CHIP_ISAC 1
1060#endif
1061#else
1062#define CARD_DIEHLDIVA 0
1063#endif
1064
1065#ifdef CONFIG_HISAX_ASUSCOM
1066#define CARD_ASUSCOM 1
1067#ifndef ISDN_CHIP_ISAC
1068#define ISDN_CHIP_ISAC 1
1069#endif
1070#else
1071#define CARD_ASUSCOM 0
1072#endif
1073
1074#ifdef CONFIG_HISAX_TELEINT
1075#define CARD_TELEINT 1
1076#ifndef ISDN_CHIP_ISAC
1077#define ISDN_CHIP_ISAC 1
1078#endif
1079#else
1080#define CARD_TELEINT 0
1081#endif
1082
1083#ifdef CONFIG_HISAX_SEDLBAUER
1084#define CARD_SEDLBAUER 1
1085#ifndef ISDN_CHIP_ISAC
1086#define ISDN_CHIP_ISAC 1
1087#endif
1088#else
1089#define CARD_SEDLBAUER 0
1090#endif
1091
1092#ifdef CONFIG_HISAX_SPORTSTER
1093#define CARD_SPORTSTER 1
1094#ifndef ISDN_CHIP_ISAC
1095#define ISDN_CHIP_ISAC 1
1096#endif
1097#else
1098#define CARD_SPORTSTER 0
1099#endif
1100
1101#ifdef CONFIG_HISAX_MIC
1102#define CARD_MIC 1
1103#ifndef ISDN_CHIP_ISAC
1104#define ISDN_CHIP_ISAC 1
1105#endif
1106#else
1107#define CARD_MIC 0
1108#endif
1109
1110#ifdef CONFIG_HISAX_NETJET
1111#define CARD_NETJET_S 1
1112#ifndef ISDN_CHIP_ISAC
1113#define ISDN_CHIP_ISAC 1
1114#endif
1115#else
1116#define CARD_NETJET_S 0
1117#endif
1118
1119#ifdef CONFIG_HISAX_HFCS
1120#define CARD_HFCS 1
1121#else
1122#define CARD_HFCS 0
1123#endif
1124
1125#ifdef CONFIG_HISAX_HFC_PCI
1126#define CARD_HFC_PCI 1
1127#else
1128#define CARD_HFC_PCI 0
1129#endif
1130
1131#ifdef CONFIG_HISAX_HFC_SX
1132#define CARD_HFC_SX 1
1133#else
1134#define CARD_HFC_SX 0
1135#endif
1136
1137#ifdef CONFIG_HISAX_NICCY
1138#define CARD_NICCY 1
1139#ifndef ISDN_CHIP_ISAC
1140#define ISDN_CHIP_ISAC 1
1141#endif
1142#else
1143#define CARD_NICCY 0
1144#endif
1145
1146#ifdef CONFIG_HISAX_ISURF
1147#define CARD_ISURF 1
1148#ifndef ISDN_CHIP_ISAC
1149#define ISDN_CHIP_ISAC 1
1150#endif
1151#else
1152#define CARD_ISURF 0
1153#endif
1154
1155#ifdef CONFIG_HISAX_S0BOX
1156#define CARD_S0BOX 1
1157#ifndef ISDN_CHIP_ISAC
1158#define ISDN_CHIP_ISAC 1
1159#endif
1160#else
1161#define CARD_S0BOX 0
1162#endif
1163
1164#ifdef CONFIG_HISAX_HSTSAPHIR
1165#define CARD_HSTSAPHIR 1
1166#ifndef ISDN_CHIP_ISAC
1167#define ISDN_CHIP_ISAC 1
1168#endif
1169#else
1170#define CARD_HSTSAPHIR 0
1171#endif
1172
1173#ifdef CONFIG_HISAX_BKM_A4T
1174#define CARD_BKM_A4T 1
1175#ifndef ISDN_CHIP_ISAC
1176#define ISDN_CHIP_ISAC 1
1177#endif
1178#else
1179#define CARD_BKM_A4T 0
1180#endif
1181
1182#ifdef CONFIG_HISAX_SCT_QUADRO
1183#define CARD_SCT_QUADRO 1
1184#ifndef ISDN_CHIP_ISAC
1185#define ISDN_CHIP_ISAC 1
1186#endif
1187#else
1188#define CARD_SCT_QUADRO 0
1189#endif
1190
1191#ifdef CONFIG_HISAX_GAZEL
1192#define CARD_GAZEL 1
1193#ifndef ISDN_CHIP_ISAC
1194#define ISDN_CHIP_ISAC 1
1195#endif
1196#else
1197#define CARD_GAZEL 0
1198#endif
1199
1200#ifdef CONFIG_HISAX_W6692
1201#define CARD_W6692 1
1202#ifndef ISDN_CHIP_W6692
1203#define ISDN_CHIP_W6692 1
1204#endif
1205#else
1206#define CARD_W6692 0
1207#endif
1208
1209#ifdef CONFIG_HISAX_NETJET_U
1210#define CARD_NETJET_U 1
1211#ifndef ISDN_CHIP_ICC
1212#define ISDN_CHIP_ICC 1
1213#endif
1214#ifndef HISAX_UINTERFACE
1215#define HISAX_UINTERFACE 1
1216#endif
1217#else
1218#define CARD_NETJET_U 0
1219#endif
1220
1221#ifdef CONFIG_HISAX_ENTERNOW_PCI
1222#define CARD_FN_ENTERNOW_PCI 1
1223#else
1224#define CARD_FN_ENTERNOW_PCI 0
1225#endif
1226
1227#define TEI_PER_CARD 1
1228
1229
1230#define L1_DEB_WARN 0x01
1231#define L1_DEB_INTSTAT 0x02
1232#define L1_DEB_ISAC 0x04
1233#define L1_DEB_ISAC_FIFO 0x08
1234#define L1_DEB_HSCX 0x10
1235#define L1_DEB_HSCX_FIFO 0x20
1236#define L1_DEB_LAPD 0x40
1237#define L1_DEB_IPAC 0x80
1238#define L1_DEB_RECEIVE_FRAME 0x100
1239#define L1_DEB_MONITOR 0x200
1240#define DEB_DLOG_HEX 0x400
1241#define DEB_DLOG_VERBOSE 0x800
1242
1243#define L2FRAME_DEBUG
1244
1245#ifdef L2FRAME_DEBUG
1246extern void Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf, int dir);
1247#endif
1248
1249#include "hisax_cfg.h"
1250
1251void init_bcstate(struct IsdnCardState *cs, int bc);
1252
1253void setstack_HiSax(struct PStack *st, struct IsdnCardState *cs);
1254void HiSax_addlist(struct IsdnCardState *sp, struct PStack *st);
1255void HiSax_rmlist(struct IsdnCardState *sp, struct PStack *st);
1256
1257void setstack_l1_B(struct PStack *st);
1258
1259void setstack_tei(struct PStack *st);
1260void setstack_manager(struct PStack *st);
1261
1262void setstack_isdnl2(struct PStack *st, char *debug_id);
1263void releasestack_isdnl2(struct PStack *st);
1264void setstack_transl2(struct PStack *st);
1265void releasestack_transl2(struct PStack *st);
1266void lli_writewakeup(struct PStack *st, int len);
1267
1268void setstack_l3dc(struct PStack *st, struct Channel *chanp);
1269void setstack_l3bc(struct PStack *st, struct Channel *chanp);
1270void releasestack_isdnl3(struct PStack *st);
1271
1272u_char *findie(u_char *p, int size, u_char ie, int wanted_set);
1273int getcallref(u_char *p);
1274int newcallref(void);
1275
1276int FsmNew(struct Fsm *fsm, struct FsmNode *fnlist, int fncount);
1277void FsmFree(struct Fsm *fsm);
1278int FsmEvent(struct FsmInst *fi, int event, void *arg);
1279void FsmChangeState(struct FsmInst *fi, int newstate);
1280void FsmInitTimer(struct FsmInst *fi, struct FsmTimer *ft);
1281int FsmAddTimer(struct FsmTimer *ft, int millisec, int event,
1282 void *arg, int where);
1283void FsmRestartTimer(struct FsmTimer *ft, int millisec, int event,
1284 void *arg, int where);
1285void FsmDelTimer(struct FsmTimer *ft, int where);
1286int jiftime(char *s, long mark);
1287
1288int HiSax_command(isdn_ctrl *ic);
1289int HiSax_writebuf_skb(int id, int chan, int ack, struct sk_buff *skb);
1290__printf(3, 4)
1291void HiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, ...);
1292__printf(3, 0)
1293void VHiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, va_list args);
1294void HiSax_reportcard(int cardnr, int sel);
1295int QuickHex(char *txt, u_char *p, int cnt);
1296void LogFrame(struct IsdnCardState *cs, u_char *p, int size);
1297void dlogframe(struct IsdnCardState *cs, struct sk_buff *skb, int dir);
1298void iecpy(u_char *dest, u_char *iestart, int ieoffset);
1299#endif
1300
1301
1302
1303
1304#define HZDELAY(jiffs) do { \
1305 int tout = jiffs; \
1306 \
1307 while (tout--) { \
1308 int loops = USEC_PER_SEC / HZ; \
1309 while (loops--) \
1310 udelay(1); \
1311 } \
1312 } while (0)
1313
1314int ll_run(struct IsdnCardState *cs, int addfeatures);
1315int CallcNew(void);
1316void CallcFree(void);
1317int CallcNewChan(struct IsdnCardState *cs);
1318void CallcFreeChan(struct IsdnCardState *cs);
1319int Isdnl1New(void);
1320void Isdnl1Free(void);
1321int Isdnl2New(void);
1322void Isdnl2Free(void);
1323int Isdnl3New(void);
1324void Isdnl3Free(void);
1325void init_tei(struct IsdnCardState *cs, int protocol);
1326void release_tei(struct IsdnCardState *cs);
1327char *HiSax_getrev(const char *revision);
1328int TeiNew(void);
1329void TeiFree(void);
1330
1331#ifdef CONFIG_PCI
1332
1333#include <linux/pci.h>
1334
1335
1336
1337
1338
1339
1340static inline struct pci_dev *hisax_find_pci_device(unsigned int vendor,
1341 unsigned int device,
1342 struct pci_dev *from)
1343{
1344 struct pci_dev *pdev;
1345
1346 pci_dev_get(from);
1347 pdev = pci_get_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
1348 pci_dev_put(pdev);
1349 return pdev;
1350}
1351
1352#endif
1353
