1/* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10#ifndef BNXT_HSI_H 11#define BNXT_HSI_H 12 13/* per-context HW statistics -- chip view */ 14struct ctx_hw_stats { 15 __le64 rx_ucast_pkts; 16 __le64 rx_mcast_pkts; 17 __le64 rx_bcast_pkts; 18 __le64 rx_discard_pkts; 19 __le64 rx_drop_pkts; 20 __le64 rx_ucast_bytes; 21 __le64 rx_mcast_bytes; 22 __le64 rx_bcast_bytes; 23 __le64 tx_ucast_pkts; 24 __le64 tx_mcast_pkts; 25 __le64 tx_bcast_pkts; 26 __le64 tx_discard_pkts; 27 __le64 tx_drop_pkts; 28 __le64 tx_ucast_bytes; 29 __le64 tx_mcast_bytes; 30 __le64 tx_bcast_bytes; 31 __le64 tpa_pkts; 32 __le64 tpa_bytes; 33 __le64 tpa_events; 34 __le64 tpa_aborts; 35}; 36 37/* Statistics Ejection Buffer Completion Record (16 bytes) */ 38struct eject_cmpl { 39 __le16 type; 40 #define EJECT_CMPL_TYPE_MASK 0x3fUL 41 #define EJECT_CMPL_TYPE_SFT 0 42 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 43 __le16 len; 44 __le32 opaque; 45 __le32 v; 46 #define EJECT_CMPL_V 0x1UL 47 __le32 unused_2; 48}; 49 50/* HWRM Completion Record (16 bytes) */ 51struct hwrm_cmpl { 52 __le16 type; 53 #define HWRM_CMPL_TYPE_MASK 0x3fUL 54 #define HWRM_CMPL_TYPE_SFT 0 55 #define HWRM_CMPL_TYPE_HWRM_DONE 0x20UL 56 __le16 sequence_id; 57 __le32 unused_1; 58 __le32 v; 59 #define HWRM_CMPL_V 0x1UL 60 __le32 unused_3; 61}; 62 63/* HWRM Forwarded Request (16 bytes) */ 64struct hwrm_fwd_req_cmpl { 65 __le16 req_len_type; 66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL 67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 71 __le16 source_id; 72 __le32 unused_0; 73 __le32 req_buf_addr_v[2]; 74 #define HWRM_FWD_REQ_CMPL_V 0x1UL 75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 77}; 78 79/* HWRM Forwarded Response (16 bytes) */ 80struct hwrm_fwd_resp_cmpl { 81 __le16 type; 82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL 83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 85 __le16 source_id; 86 __le16 resp_len; 87 __le16 unused_1; 88 __le32 resp_buf_addr_v[2]; 89 #define HWRM_FWD_RESP_CMPL_V 0x1UL 90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 92}; 93 94/* HWRM Asynchronous Event Completion Record (16 bytes) */ 95struct hwrm_async_event_cmpl { 96 __le16 type; 97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 100 __le16 event_id; 101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 115 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 116 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 117 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 118 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 119 __le32 event_data2; 120 u8 opaque_v; 121 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL 122 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 123 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 124 u8 timestamp_lo; 125 __le16 timestamp_hi; 126 __le32 event_data1; 127}; 128 129/* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 130struct hwrm_async_event_cmpl_link_status_change { 131 __le16 type; 132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 133 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 135 __le16 event_id; 136 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 137 __le32 event_data2; 138 u8 opaque_v; 139 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 140 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 141 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 142 u8 timestamp_lo; 143 __le16 timestamp_hi; 144 __le32 event_data1; 145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 149 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 150 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 151 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 152 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 153}; 154 155/* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 156struct hwrm_async_event_cmpl_link_mtu_change { 157 __le16 type; 158 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 159 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 160 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 161 __le16 event_id; 162 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 163 __le32 event_data2; 164 u8 opaque_v; 165 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 166 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 167 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 168 u8 timestamp_lo; 169 __le16 timestamp_hi; 170 __le32 event_data1; 171 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 172 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 173}; 174 175/* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 176struct hwrm_async_event_cmpl_link_speed_change { 177 __le16 type; 178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 181 __le16 event_id; 182 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 183 __le32 event_data2; 184 u8 opaque_v; 185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 187 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 188 u8 timestamp_lo; 189 __le16 timestamp_hi; 190 __le32 event_data1; 191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 200 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 201 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 203 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 205 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 206 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 207}; 208 209/* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 210struct hwrm_async_event_cmpl_dcb_config_change { 211 __le16 type; 212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 214 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 215 __le16 event_id; 216 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 217 __le32 event_data2; 218 u8 opaque_v; 219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 220 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 221 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 222 u8 timestamp_lo; 223 __le16 timestamp_hi; 224 __le32 event_data1; 225 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 226 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 227}; 228 229/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 230struct hwrm_async_event_cmpl_port_conn_not_allowed { 231 __le16 type; 232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 233 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 234 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 235 __le16 event_id; 236 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 237 __le32 event_data2; 238 u8 opaque_v; 239 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 240 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 241 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 242 u8 timestamp_lo; 243 __le16 timestamp_hi; 244 __le32 event_data1; 245 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 246 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 247 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 248 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 249 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 250 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 251 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 253 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 254}; 255 256/* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 257struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 258 __le16 type; 259 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 260 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 261 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 262 __le16 event_id; 263 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 264 __le32 event_data2; 265 u8 opaque_v; 266 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 267 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 268 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 269 u8 timestamp_lo; 270 __le16 timestamp_hi; 271 __le32 event_data1; 272 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 274}; 275 276/* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 277struct hwrm_async_event_cmpl_link_speed_cfg_change { 278 __le16 type; 279 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 280 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 281 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 282 __le16 event_id; 283 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 284 __le32 event_data2; 285 u8 opaque_v; 286 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 287 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 288 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 289 u8 timestamp_lo; 290 __le16 timestamp_hi; 291 __le32 event_data1; 292 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 293 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 295 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 296}; 297 298/* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 299struct hwrm_async_event_cmpl_func_drvr_unload { 300 __le16 type; 301 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 302 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 303 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 304 __le16 event_id; 305 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 306 __le32 event_data2; 307 u8 opaque_v; 308 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 309 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 310 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 311 u8 timestamp_lo; 312 __le16 timestamp_hi; 313 __le32 event_data1; 314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 315 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 316}; 317 318/* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 319struct hwrm_async_event_cmpl_func_drvr_load { 320 __le16 type; 321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 322 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 323 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 324 __le16 event_id; 325 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 326 __le32 event_data2; 327 u8 opaque_v; 328 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 329 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 330 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 331 u8 timestamp_lo; 332 __le16 timestamp_hi; 333 __le32 event_data1; 334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 335 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 336}; 337 338/* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 339struct hwrm_async_event_cmpl_pf_drvr_unload { 340 __le16 type; 341 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 342 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 343 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 344 __le16 event_id; 345 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 346 __le32 event_data2; 347 u8 opaque_v; 348 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 349 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 350 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 351 u8 timestamp_lo; 352 __le16 timestamp_hi; 353 __le32 event_data1; 354 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 357 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 358}; 359 360/* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 361struct hwrm_async_event_cmpl_pf_drvr_load { 362 __le16 type; 363 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 365 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 366 __le16 event_id; 367 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 368 __le32 event_data2; 369 u8 opaque_v; 370 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 371 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 372 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 373 u8 timestamp_lo; 374 __le16 timestamp_hi; 375 __le32 event_data1; 376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 377 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 379 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 380}; 381 382/* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 383struct hwrm_async_event_cmpl_vf_flr { 384 __le16 type; 385 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 386 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 387 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 388 __le16 event_id; 389 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 390 __le32 event_data2; 391 u8 opaque_v; 392 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 393 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 394 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 395 u8 timestamp_lo; 396 __le16 timestamp_hi; 397 __le32 event_data1; 398 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 399 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 400}; 401 402/* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 403struct hwrm_async_event_cmpl_vf_mac_addr_change { 404 __le16 type; 405 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 406 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 407 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 408 __le16 event_id; 409 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 410 __le32 event_data2; 411 u8 opaque_v; 412 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 413 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 414 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 415 u8 timestamp_lo; 416 __le16 timestamp_hi; 417 __le32 event_data1; 418 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 419 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 420}; 421 422/* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 423struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 424 __le16 type; 425 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 426 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 427 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 428 __le16 event_id; 429 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 430 __le32 event_data2; 431 u8 opaque_v; 432 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 433 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 434 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 435 u8 timestamp_lo; 436 __le16 timestamp_hi; 437 __le32 event_data1; 438 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 439}; 440 441/* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 442struct hwrm_async_event_cmpl_vf_cfg_change { 443 __le16 type; 444 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 445 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 446 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 447 __le16 event_id; 448 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 449 __le32 event_data2; 450 u8 opaque_v; 451 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 452 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 453 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 454 u8 timestamp_lo; 455 __le16 timestamp_hi; 456 __le32 event_data1; 457 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 458 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 459 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 460 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 461}; 462 463/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 464struct hwrm_async_event_cmpl_hwrm_error { 465 __le16 type; 466 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 468 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 469 __le16 event_id; 470 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 471 __le32 event_data2; 472 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 473 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 474 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 475 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 476 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 478 u8 opaque_v; 479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 480 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 481 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 482 u8 timestamp_lo; 483 __le16 timestamp_hi; 484 __le32 event_data1; 485 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 486}; 487 488/* HW Resource Manager Specification 1.5.1 */ 489#define HWRM_VERSION_MAJOR 1 490#define HWRM_VERSION_MINOR 5 491#define HWRM_VERSION_UPDATE 1 492 493#define HWRM_VERSION_STR "1.5.1" 494/* 495 * Following is the signature for HWRM message field that indicates not 496 * applicable (All F's). Need to cast it the size of the field if needed. 497 */ 498#define HWRM_NA_SIGNATURE ((__le32)(-1)) 499#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 500#define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 501#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 502#define HW_HASH_KEY_SIZE 40 503#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 504/* Input (16 bytes) */ 505struct input { 506 __le16 req_type; 507 __le16 cmpl_ring; 508 __le16 seq_id; 509 __le16 target_id; 510 __le64 resp_addr; 511}; 512 513/* Output (8 bytes) */ 514struct output { 515 __le16 error_code; 516 __le16 req_type; 517 __le16 seq_id; 518 __le16 resp_len; 519}; 520 521/* Command numbering (8 bytes) */ 522struct cmd_nums { 523 __le16 req_type; 524 #define HWRM_VER_GET (0x0UL) 525 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 526 #define HWRM_FUNC_VF_CFG (0xfUL) 527 #define RESERVED1 (0x10UL) 528 #define HWRM_FUNC_RESET (0x11UL) 529 #define HWRM_FUNC_GETFID (0x12UL) 530 #define HWRM_FUNC_VF_ALLOC (0x13UL) 531 #define HWRM_FUNC_VF_FREE (0x14UL) 532 #define HWRM_FUNC_QCAPS (0x15UL) 533 #define HWRM_FUNC_QCFG (0x16UL) 534 #define HWRM_FUNC_CFG (0x17UL) 535 #define HWRM_FUNC_QSTATS (0x18UL) 536 #define HWRM_FUNC_CLR_STATS (0x19UL) 537 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 538 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 539 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 540 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 541 #define HWRM_FUNC_DRV_QVER (0x1eUL) 542 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 543 #define HWRM_PORT_PHY_CFG (0x20UL) 544 #define HWRM_PORT_MAC_CFG (0x21UL) 545 #define HWRM_PORT_TS_QUERY (0x22UL) 546 #define HWRM_PORT_QSTATS (0x23UL) 547 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 548 #define HWRM_PORT_CLR_STATS (0x25UL) 549 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 550 #define HWRM_PORT_PHY_QCFG (0x27UL) 551 #define HWRM_PORT_MAC_QCFG (0x28UL) 552 #define HWRM_PORT_BLINK_LED (0x29UL) 553 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 554 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 555 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 556 #define HWRM_QUEUE_QPORTCFG (0x30UL) 557 #define HWRM_QUEUE_QCFG (0x31UL) 558 #define HWRM_QUEUE_CFG (0x32UL) 559 #define RESERVED2 (0x33UL) 560 #define RESERVED3 (0x34UL) 561 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 562 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 563 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 564 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 565 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 566 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 567 #define HWRM_VNIC_ALLOC (0x40UL) 568 #define HWRM_VNIC_FREE (0x41UL) 569 #define HWRM_VNIC_CFG (0x42UL) 570 #define HWRM_VNIC_QCFG (0x43UL) 571 #define HWRM_VNIC_TPA_CFG (0x44UL) 572 #define HWRM_VNIC_TPA_QCFG (0x45UL) 573 #define HWRM_VNIC_RSS_CFG (0x46UL) 574 #define HWRM_VNIC_RSS_QCFG (0x47UL) 575 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 576 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 577 #define HWRM_VNIC_QCAPS (0x4aUL) 578 #define HWRM_RING_ALLOC (0x50UL) 579 #define HWRM_RING_FREE (0x51UL) 580 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 581 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 582 #define HWRM_RING_RESET (0x5eUL) 583 #define HWRM_RING_GRP_ALLOC (0x60UL) 584 #define HWRM_RING_GRP_FREE (0x61UL) 585 #define RESERVED5 (0x64UL) 586 #define RESERVED6 (0x65UL) 587 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 588 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 589 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 590 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 591 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 592 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 593 #define RESERVED4 (0x94UL) 594 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 595 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 596 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 597 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 598 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 599 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 600 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 601 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 602 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 603 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 604 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 605 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 606 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 607 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 608 #define HWRM_STAT_CTX_FREE (0xb1UL) 609 #define HWRM_STAT_CTX_QUERY (0xb2UL) 610 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 611 #define HWRM_FW_RESET (0xc0UL) 612 #define HWRM_FW_QSTATUS (0xc1UL) 613 #define HWRM_FW_SET_TIME (0xc8UL) 614 #define HWRM_FW_GET_TIME (0xc9UL) 615 #define HWRM_EXEC_FWD_RESP (0xd0UL) 616 #define HWRM_REJECT_FWD_RESP (0xd1UL) 617 #define HWRM_FWD_RESP (0xd2UL) 618 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 619 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 620 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 621 #define HWRM_WOL_FILTER_FREE (0xf1UL) 622 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 623 #define HWRM_WOL_REASON_QCFG (0xf3UL) 624 #define HWRM_DBG_READ_DIRECT (0xff10UL) 625 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 626 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 627 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 628 #define HWRM_DBG_DUMP (0xff14UL) 629 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 630 #define HWRM_NVM_MODIFY (0xfff4UL) 631 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 632 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 633 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 634 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 635 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 636 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 637 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 638 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 639 #define HWRM_NVM_READ (0xfffdUL) 640 #define HWRM_NVM_WRITE (0xfffeUL) 641 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 642 __le16 unused_0[3]; 643}; 644 645/* Return Codes (8 bytes) */ 646struct ret_codes { 647 __le16 error_code; 648 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 649 #define HWRM_ERR_CODE_FAIL (0x1UL) 650 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 651 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 652 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 653 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 654 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 655 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 656 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 657 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 658 __le16 unused_0[3]; 659}; 660 661/* Output (16 bytes) */ 662struct hwrm_err_output { 663 __le16 error_code; 664 __le16 req_type; 665 __le16 seq_id; 666 __le16 resp_len; 667 __le32 opaque_0; 668 __le16 opaque_1; 669 u8 cmd_err; 670 u8 valid; 671}; 672 673/* Port Tx Statistics Formats (408 bytes) */ 674struct tx_port_stats { 675 __le64 tx_64b_frames; 676 __le64 tx_65b_127b_frames; 677 __le64 tx_128b_255b_frames; 678 __le64 tx_256b_511b_frames; 679 __le64 tx_512b_1023b_frames; 680 __le64 tx_1024b_1518_frames; 681 __le64 tx_good_vlan_frames; 682 __le64 tx_1519b_2047_frames; 683 __le64 tx_2048b_4095b_frames; 684 __le64 tx_4096b_9216b_frames; 685 __le64 tx_9217b_16383b_frames; 686 __le64 tx_good_frames; 687 __le64 tx_total_frames; 688 __le64 tx_ucast_frames; 689 __le64 tx_mcast_frames; 690 __le64 tx_bcast_frames; 691 __le64 tx_pause_frames; 692 __le64 tx_pfc_frames; 693 __le64 tx_jabber_frames; 694 __le64 tx_fcs_err_frames; 695 __le64 tx_control_frames; 696 __le64 tx_oversz_frames; 697 __le64 tx_single_dfrl_frames; 698 __le64 tx_multi_dfrl_frames; 699 __le64 tx_single_coll_frames; 700 __le64 tx_multi_coll_frames; 701 __le64 tx_late_coll_frames; 702 __le64 tx_excessive_coll_frames; 703 __le64 tx_frag_frames; 704 __le64 tx_err; 705 __le64 tx_tagged_frames; 706 __le64 tx_dbl_tagged_frames; 707 __le64 tx_runt_frames; 708 __le64 tx_fifo_underruns; 709 __le64 tx_pfc_ena_frames_pri0; 710 __le64 tx_pfc_ena_frames_pri1; 711 __le64 tx_pfc_ena_frames_pri2; 712 __le64 tx_pfc_ena_frames_pri3; 713 __le64 tx_pfc_ena_frames_pri4; 714 __le64 tx_pfc_ena_frames_pri5; 715 __le64 tx_pfc_ena_frames_pri6; 716 __le64 tx_pfc_ena_frames_pri7; 717 __le64 tx_eee_lpi_events; 718 __le64 tx_eee_lpi_duration; 719 __le64 tx_llfc_logical_msgs; 720 __le64 tx_hcfc_msgs; 721 __le64 tx_total_collisions; 722 __le64 tx_bytes; 723 __le64 tx_xthol_frames; 724 __le64 tx_stat_discard; 725 __le64 tx_stat_error; 726}; 727 728/* Port Rx Statistics Formats (528 bytes) */ 729struct rx_port_stats { 730 __le64 rx_64b_frames; 731 __le64 rx_65b_127b_frames; 732 __le64 rx_128b_255b_frames; 733 __le64 rx_256b_511b_frames; 734 __le64 rx_512b_1023b_frames; 735 __le64 rx_1024b_1518_frames; 736 __le64 rx_good_vlan_frames; 737 __le64 rx_1519b_2047b_frames; 738 __le64 rx_2048b_4095b_frames; 739 __le64 rx_4096b_9216b_frames; 740 __le64 rx_9217b_16383b_frames; 741 __le64 rx_total_frames; 742 __le64 rx_ucast_frames; 743 __le64 rx_mcast_frames; 744 __le64 rx_bcast_frames; 745 __le64 rx_fcs_err_frames; 746 __le64 rx_ctrl_frames; 747 __le64 rx_pause_frames; 748 __le64 rx_pfc_frames; 749 __le64 rx_unsupported_opcode_frames; 750 __le64 rx_unsupported_da_pausepfc_frames; 751 __le64 rx_wrong_sa_frames; 752 __le64 rx_align_err_frames; 753 __le64 rx_oor_len_frames; 754 __le64 rx_code_err_frames; 755 __le64 rx_false_carrier_frames; 756 __le64 rx_ovrsz_frames; 757 __le64 rx_jbr_frames; 758 __le64 rx_mtu_err_frames; 759 __le64 rx_match_crc_frames; 760 __le64 rx_promiscuous_frames; 761 __le64 rx_tagged_frames; 762 __le64 rx_double_tagged_frames; 763 __le64 rx_trunc_frames; 764 __le64 rx_good_frames; 765 __le64 rx_pfc_xon2xoff_frames_pri0; 766 __le64 rx_pfc_xon2xoff_frames_pri1; 767 __le64 rx_pfc_xon2xoff_frames_pri2; 768 __le64 rx_pfc_xon2xoff_frames_pri3; 769 __le64 rx_pfc_xon2xoff_frames_pri4; 770 __le64 rx_pfc_xon2xoff_frames_pri5; 771 __le64 rx_pfc_xon2xoff_frames_pri6; 772 __le64 rx_pfc_xon2xoff_frames_pri7; 773 __le64 rx_pfc_ena_frames_pri0; 774 __le64 rx_pfc_ena_frames_pri1; 775 __le64 rx_pfc_ena_frames_pri2; 776 __le64 rx_pfc_ena_frames_pri3; 777 __le64 rx_pfc_ena_frames_pri4; 778 __le64 rx_pfc_ena_frames_pri5; 779 __le64 rx_pfc_ena_frames_pri6; 780 __le64 rx_pfc_ena_frames_pri7; 781 __le64 rx_sch_crc_err_frames; 782 __le64 rx_undrsz_frames; 783 __le64 rx_frag_frames; 784 __le64 rx_eee_lpi_events; 785 __le64 rx_eee_lpi_duration; 786 __le64 rx_llfc_physical_msgs; 787 __le64 rx_llfc_logical_msgs; 788 __le64 rx_llfc_msgs_with_crc_err; 789 __le64 rx_hcfc_msgs; 790 __le64 rx_hcfc_msgs_with_crc_err; 791 __le64 rx_bytes; 792 __le64 rx_runt_bytes; 793 __le64 rx_runt_frames; 794 __le64 rx_stat_discard; 795 __le64 rx_stat_err; 796}; 797 798/* hwrm_ver_get */ 799/* Input (24 bytes) */ 800struct hwrm_ver_get_input { 801 __le16 req_type; 802 __le16 cmpl_ring; 803 __le16 seq_id; 804 __le16 target_id; 805 __le64 resp_addr; 806 u8 hwrm_intf_maj; 807 u8 hwrm_intf_min; 808 u8 hwrm_intf_upd; 809 u8 unused_0[5]; 810}; 811 812/* Output (128 bytes) */ 813struct hwrm_ver_get_output { 814 __le16 error_code; 815 __le16 req_type; 816 __le16 seq_id; 817 __le16 resp_len; 818 u8 hwrm_intf_maj; 819 u8 hwrm_intf_min; 820 u8 hwrm_intf_upd; 821 u8 hwrm_intf_rsvd; 822 u8 hwrm_fw_maj; 823 u8 hwrm_fw_min; 824 u8 hwrm_fw_bld; 825 u8 hwrm_fw_rsvd; 826 u8 mgmt_fw_maj; 827 u8 mgmt_fw_min; 828 u8 mgmt_fw_bld; 829 u8 mgmt_fw_rsvd; 830 u8 netctrl_fw_maj; 831 u8 netctrl_fw_min; 832 u8 netctrl_fw_bld; 833 u8 netctrl_fw_rsvd; 834 __le32 dev_caps_cfg; 835 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 836 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 837 u8 roce_fw_maj; 838 u8 roce_fw_min; 839 u8 roce_fw_bld; 840 u8 roce_fw_rsvd; 841 char hwrm_fw_name[16]; 842 char mgmt_fw_name[16]; 843 char netctrl_fw_name[16]; 844 __le32 reserved2[4]; 845 char roce_fw_name[16]; 846 __le16 chip_num; 847 u8 chip_rev; 848 u8 chip_metal; 849 u8 chip_bond_id; 850 u8 chip_platform_type; 851 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 852 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 853 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 854 __le16 max_req_win_len; 855 __le16 max_resp_len; 856 __le16 def_req_timeout; 857 u8 unused_0; 858 u8 unused_1; 859 u8 unused_2; 860 u8 valid; 861}; 862 863/* hwrm_func_reset */ 864/* Input (24 bytes) */ 865struct hwrm_func_reset_input { 866 __le16 req_type; 867 __le16 cmpl_ring; 868 __le16 seq_id; 869 __le16 target_id; 870 __le64 resp_addr; 871 __le32 enables; 872 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 873 __le16 vf_id; 874 u8 func_reset_level; 875 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 876 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 877 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 878 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 879 u8 unused_0; 880}; 881 882/* Output (16 bytes) */ 883struct hwrm_func_reset_output { 884 __le16 error_code; 885 __le16 req_type; 886 __le16 seq_id; 887 __le16 resp_len; 888 __le32 unused_0; 889 u8 unused_1; 890 u8 unused_2; 891 u8 unused_3; 892 u8 valid; 893}; 894 895/* hwrm_func_getfid */ 896/* Input (24 bytes) */ 897struct hwrm_func_getfid_input { 898 __le16 req_type; 899 __le16 cmpl_ring; 900 __le16 seq_id; 901 __le16 target_id; 902 __le64 resp_addr; 903 __le32 enables; 904 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 905 __le16 pci_id; 906 __le16 unused_0; 907}; 908 909/* Output (16 bytes) */ 910struct hwrm_func_getfid_output { 911 __le16 error_code; 912 __le16 req_type; 913 __le16 seq_id; 914 __le16 resp_len; 915 __le16 fid; 916 u8 unused_0; 917 u8 unused_1; 918 u8 unused_2; 919 u8 unused_3; 920 u8 unused_4; 921 u8 valid; 922}; 923 924/* hwrm_func_vf_alloc */ 925/* Input (24 bytes) */ 926struct hwrm_func_vf_alloc_input { 927 __le16 req_type; 928 __le16 cmpl_ring; 929 __le16 seq_id; 930 __le16 target_id; 931 __le64 resp_addr; 932 __le32 enables; 933 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 934 __le16 first_vf_id; 935 __le16 num_vfs; 936}; 937 938/* Output (16 bytes) */ 939struct hwrm_func_vf_alloc_output { 940 __le16 error_code; 941 __le16 req_type; 942 __le16 seq_id; 943 __le16 resp_len; 944 __le16 first_vf_id; 945 u8 unused_0; 946 u8 unused_1; 947 u8 unused_2; 948 u8 unused_3; 949 u8 unused_4; 950 u8 valid; 951}; 952 953/* hwrm_func_vf_free */ 954/* Input (24 bytes) */ 955struct hwrm_func_vf_free_input { 956 __le16 req_type; 957 __le16 cmpl_ring; 958 __le16 seq_id; 959 __le16 target_id; 960 __le64 resp_addr; 961 __le32 enables; 962 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 963 __le16 first_vf_id; 964 __le16 num_vfs; 965}; 966 967/* Output (16 bytes) */ 968struct hwrm_func_vf_free_output { 969 __le16 error_code; 970 __le16 req_type; 971 __le16 seq_id; 972 __le16 resp_len; 973 __le32 unused_0; 974 u8 unused_1; 975 u8 unused_2; 976 u8 unused_3; 977 u8 valid; 978}; 979 980/* hwrm_func_vf_cfg */ 981/* Input (32 bytes) */ 982struct hwrm_func_vf_cfg_input { 983 __le16 req_type; 984 __le16 cmpl_ring; 985 __le16 seq_id; 986 __le16 target_id; 987 __le64 resp_addr; 988 __le32 enables; 989 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 990 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 991 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 992 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 993 __le16 mtu; 994 __le16 guest_vlan; 995 __le16 async_event_cr; 996 u8 dflt_mac_addr[6]; 997}; 998 999/* Output (16 bytes) */ 1000struct hwrm_func_vf_cfg_output {
1001 __le16 error_code; 1002 __le16 req_type; 1003 __le16 seq_id; 1004 __le16 resp_len; 1005 __le32 unused_0; 1006 u8 unused_1; 1007 u8 unused_2; 1008 u8 unused_3; 1009 u8 valid; 1010}; 1011 1012/* hwrm_func_qcaps */ 1013/* Input (24 bytes) */ 1014struct hwrm_func_qcaps_input { 1015 __le16 req_type; 1016 __le16 cmpl_ring; 1017 __le16 seq_id; 1018 __le16 target_id; 1019 __le64 resp_addr; 1020 __le16 fid; 1021 __le16 unused_0[3]; 1022}; 1023 1024/* Output (80 bytes) */ 1025struct hwrm_func_qcaps_output { 1026 __le16 error_code; 1027 __le16 req_type; 1028 __le16 seq_id; 1029 __le16 resp_len; 1030 __le16 fid; 1031 __le16 port_id; 1032 __le32 flags; 1033 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1034 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1035 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1036 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1037 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1038 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1039 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1040 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1041 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1042 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1043 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1044 u8 mac_address[6]; 1045 __le16 max_rsscos_ctx; 1046 __le16 max_cmpl_rings; 1047 __le16 max_tx_rings; 1048 __le16 max_rx_rings; 1049 __le16 max_l2_ctxs; 1050 __le16 max_vnics; 1051 __le16 first_vf_id; 1052 __le16 max_vfs; 1053 __le16 max_stat_ctx; 1054 __le32 max_encap_records; 1055 __le32 max_decap_records; 1056 __le32 max_tx_em_flows; 1057 __le32 max_tx_wm_flows; 1058 __le32 max_rx_em_flows; 1059 __le32 max_rx_wm_flows; 1060 __le32 max_mcast_filters; 1061 __le32 max_flow_id; 1062 __le32 max_hw_ring_grps; 1063 __le16 max_sp_tx_rings; 1064 u8 unused_0; 1065 u8 valid; 1066}; 1067 1068/* hwrm_func_qcfg */ 1069/* Input (24 bytes) */ 1070struct hwrm_func_qcfg_input { 1071 __le16 req_type; 1072 __le16 cmpl_ring; 1073 __le16 seq_id; 1074 __le16 target_id; 1075 __le64 resp_addr; 1076 __le16 fid; 1077 __le16 unused_0[3]; 1078}; 1079 1080/* Output (72 bytes) */ 1081struct hwrm_func_qcfg_output { 1082 __le16 error_code; 1083 __le16 req_type; 1084 __le16 seq_id; 1085 __le16 resp_len; 1086 __le16 fid; 1087 __le16 port_id; 1088 __le16 vlan; 1089 __le16 flags; 1090 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1091 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1092 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1093 u8 mac_address[6]; 1094 __le16 pci_id; 1095 __le16 alloc_rsscos_ctx; 1096 __le16 alloc_cmpl_rings; 1097 __le16 alloc_tx_rings; 1098 __le16 alloc_rx_rings; 1099 __le16 alloc_l2_ctx; 1100 __le16 alloc_vnics; 1101 __le16 mtu; 1102 __le16 mru; 1103 __le16 stat_ctx_id; 1104 u8 port_partition_type; 1105 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1106 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1107 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1108 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1109 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1110 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1111 u8 unused_0; 1112 __le16 dflt_vnic_id; 1113 u8 unused_1; 1114 u8 unused_2; 1115 __le32 min_bw; 1116 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1117 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1118 #define FUNC_QCFG_RESP_MIN_BW_RSVD 0x10000000UL 1119 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1120 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1121 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1122 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1123 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1124 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1125 __le32 max_bw; 1126 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1127 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1128 #define FUNC_QCFG_RESP_MAX_BW_RSVD 0x10000000UL 1129 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1130 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1131 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1132 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1133 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1134 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1135 u8 evb_mode; 1136 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1137 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1138 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1139 u8 unused_3; 1140 __le16 alloc_vfs; 1141 __le32 alloc_mcast_filters; 1142 __le32 alloc_hw_ring_grps; 1143 __le16 alloc_sp_tx_rings; 1144 u8 unused_4; 1145 u8 valid; 1146}; 1147 1148/* hwrm_func_cfg */ 1149/* Input (88 bytes) */ 1150struct hwrm_func_cfg_input { 1151 __le16 req_type; 1152 __le16 cmpl_ring; 1153 __le16 seq_id; 1154 __le16 target_id; 1155 __le64 resp_addr; 1156 __le16 fid; 1157 u8 unused_0; 1158 u8 unused_1; 1159 __le32 flags; 1160 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 1161 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 1162 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 1163 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 1164 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 1165 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 1166 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 1167 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 1168 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 1169 __le32 enables; 1170 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1171 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1172 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1173 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1174 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1175 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1176 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1177 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1178 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1179 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1180 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1181 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1182 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1183 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1184 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1185 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1186 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1187 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1188 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1189 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1190 __le16 mtu; 1191 __le16 mru; 1192 __le16 num_rsscos_ctxs; 1193 __le16 num_cmpl_rings; 1194 __le16 num_tx_rings; 1195 __le16 num_rx_rings; 1196 __le16 num_l2_ctxs; 1197 __le16 num_vnics; 1198 __le16 num_stat_ctxs; 1199 __le16 num_hw_ring_grps; 1200 u8 dflt_mac_addr[6]; 1201 __le16 dflt_vlan; 1202 __be32 dflt_ip_addr[4]; 1203 __le32 min_bw; 1204 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1205 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1206 #define FUNC_CFG_REQ_MIN_BW_RSVD 0x10000000UL 1207 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1208 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1209 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1210 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1211 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1212 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1213 __le32 max_bw; 1214 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1215 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1216 #define FUNC_CFG_REQ_MAX_BW_RSVD 0x10000000UL 1217 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1218 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1219 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1220 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1221 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1222 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1223 __le16 async_event_cr; 1224 u8 vlan_antispoof_mode; 1225 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1226 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1227 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1228 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1229 u8 allowed_vlan_pris; 1230 u8 evb_mode; 1231 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1232 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1233 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1234 u8 unused_2; 1235 __le16 num_mcast_filters; 1236}; 1237 1238/* Output (16 bytes) */ 1239struct hwrm_func_cfg_output { 1240 __le16 error_code; 1241 __le16 req_type; 1242 __le16 seq_id; 1243 __le16 resp_len; 1244 __le32 unused_0; 1245 u8 unused_1; 1246 u8 unused_2; 1247 u8 unused_3; 1248 u8 valid; 1249}; 1250 1251/* hwrm_func_qstats */ 1252/* Input (24 bytes) */ 1253struct hwrm_func_qstats_input { 1254 __le16 req_type; 1255 __le16 cmpl_ring; 1256 __le16 seq_id; 1257 __le16 target_id; 1258 __le64 resp_addr; 1259 __le16 fid; 1260 __le16 unused_0[3]; 1261}; 1262 1263/* Output (176 bytes) */ 1264struct hwrm_func_qstats_output { 1265 __le16 error_code; 1266 __le16 req_type; 1267 __le16 seq_id; 1268 __le16 resp_len; 1269 __le64 tx_ucast_pkts; 1270 __le64 tx_mcast_pkts; 1271 __le64 tx_bcast_pkts; 1272 __le64 tx_err_pkts; 1273 __le64 tx_drop_pkts; 1274 __le64 tx_ucast_bytes; 1275 __le64 tx_mcast_bytes; 1276 __le64 tx_bcast_bytes; 1277 __le64 rx_ucast_pkts; 1278 __le64 rx_mcast_pkts; 1279 __le64 rx_bcast_pkts; 1280 __le64 rx_err_pkts; 1281 __le64 rx_drop_pkts; 1282 __le64 rx_ucast_bytes; 1283 __le64 rx_mcast_bytes; 1284 __le64 rx_bcast_bytes; 1285 __le64 rx_agg_pkts; 1286 __le64 rx_agg_bytes; 1287 __le64 rx_agg_events; 1288 __le64 rx_agg_aborts; 1289 __le32 unused_0; 1290 u8 unused_1; 1291 u8 unused_2; 1292 u8 unused_3; 1293 u8 valid; 1294}; 1295 1296/* hwrm_func_clr_stats */ 1297/* Input (24 bytes) */ 1298struct hwrm_func_clr_stats_input { 1299 __le16 req_type; 1300 __le16 cmpl_ring; 1301 __le16 seq_id; 1302 __le16 target_id; 1303 __le64 resp_addr; 1304 __le16 fid; 1305 __le16 unused_0[3]; 1306}; 1307 1308/* Output (16 bytes) */ 1309struct hwrm_func_clr_stats_output { 1310 __le16 error_code; 1311 __le16 req_type; 1312 __le16 seq_id; 1313 __le16 resp_len; 1314 __le32 unused_0; 1315 u8 unused_1; 1316 u8 unused_2; 1317 u8 unused_3; 1318 u8 valid; 1319}; 1320 1321/* hwrm_func_vf_resc_free */ 1322/* Input (24 bytes) */ 1323struct hwrm_func_vf_resc_free_input { 1324 __le16 req_type; 1325 __le16 cmpl_ring; 1326 __le16 seq_id; 1327 __le16 target_id; 1328 __le64 resp_addr; 1329 __le16 vf_id; 1330 __le16 unused_0[3]; 1331}; 1332 1333/* Output (16 bytes) */ 1334struct hwrm_func_vf_resc_free_output { 1335 __le16 error_code; 1336 __le16 req_type; 1337 __le16 seq_id; 1338 __le16 resp_len; 1339 __le32 unused_0; 1340 u8 unused_1; 1341 u8 unused_2; 1342 u8 unused_3; 1343 u8 valid; 1344}; 1345 1346/* hwrm_func_vf_vnic_ids_query */ 1347/* Input (32 bytes) */ 1348struct hwrm_func_vf_vnic_ids_query_input { 1349 __le16 req_type; 1350 __le16 cmpl_ring; 1351 __le16 seq_id; 1352 __le16 target_id; 1353 __le64 resp_addr; 1354 __le16 vf_id; 1355 u8 unused_0; 1356 u8 unused_1; 1357 __le32 max_vnic_id_cnt; 1358 __le64 vnic_id_tbl_addr; 1359}; 1360 1361/* Output (16 bytes) */ 1362struct hwrm_func_vf_vnic_ids_query_output { 1363 __le16 error_code; 1364 __le16 req_type; 1365 __le16 seq_id; 1366 __le16 resp_len; 1367 __le32 vnic_id_cnt; 1368 u8 unused_0; 1369 u8 unused_1; 1370 u8 unused_2; 1371 u8 valid; 1372}; 1373 1374/* hwrm_func_drv_rgtr */ 1375/* Input (80 bytes) */ 1376struct hwrm_func_drv_rgtr_input { 1377 __le16 req_type; 1378 __le16 cmpl_ring; 1379 __le16 seq_id; 1380 __le16 target_id; 1381 __le64 resp_addr; 1382 __le32 flags; 1383 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1384 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1385 __le32 enables; 1386 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1387 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1388 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1389 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1390 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1391 __le16 os_type; 1392 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1393 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1394 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1395 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1396 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1397 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1398 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1399 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1400 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1401 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1402 u8 ver_maj; 1403 u8 ver_min; 1404 u8 ver_upd; 1405 u8 unused_0; 1406 __le16 unused_1; 1407 __le32 timestamp; 1408 __le32 unused_2; 1409 __le32 vf_req_fwd[8]; 1410 __le32 async_event_fwd[8]; 1411}; 1412 1413/* Output (16 bytes) */ 1414struct hwrm_func_drv_rgtr_output { 1415 __le16 error_code; 1416 __le16 req_type; 1417 __le16 seq_id; 1418 __le16 resp_len; 1419 __le32 unused_0; 1420 u8 unused_1; 1421 u8 unused_2; 1422 u8 unused_3; 1423 u8 valid; 1424}; 1425 1426/* hwrm_func_drv_unrgtr */ 1427/* Input (24 bytes) */ 1428struct hwrm_func_drv_unrgtr_input { 1429 __le16 req_type; 1430 __le16 cmpl_ring; 1431 __le16 seq_id; 1432 __le16 target_id; 1433 __le64 resp_addr; 1434 __le32 flags; 1435 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1436 __le32 unused_0; 1437}; 1438 1439/* Output (16 bytes) */ 1440struct hwrm_func_drv_unrgtr_output { 1441 __le16 error_code; 1442 __le16 req_type; 1443 __le16 seq_id; 1444 __le16 resp_len; 1445 __le32 unused_0; 1446 u8 unused_1; 1447 u8 unused_2; 1448 u8 unused_3; 1449 u8 valid; 1450}; 1451 1452/* hwrm_func_buf_rgtr */ 1453/* Input (128 bytes) */ 1454struct hwrm_func_buf_rgtr_input { 1455 __le16 req_type; 1456 __le16 cmpl_ring; 1457 __le16 seq_id; 1458 __le16 target_id; 1459 __le64 resp_addr; 1460 __le32 enables; 1461 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1462 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1463 __le16 vf_id; 1464 __le16 req_buf_num_pages; 1465 __le16 req_buf_page_size; 1466 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1467 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1468 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1469 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1470 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1471 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1472 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1473 __le16 req_buf_len; 1474 __le16 resp_buf_len; 1475 u8 unused_0; 1476 u8 unused_1; 1477 __le64 req_buf_page_addr0; 1478 __le64 req_buf_page_addr1; 1479 __le64 req_buf_page_addr2; 1480 __le64 req_buf_page_addr3; 1481 __le64 req_buf_page_addr4; 1482 __le64 req_buf_page_addr5; 1483 __le64 req_buf_page_addr6; 1484 __le64 req_buf_page_addr7; 1485 __le64 req_buf_page_addr8; 1486 __le64 req_buf_page_addr9; 1487 __le64 error_buf_addr; 1488 __le64 resp_buf_addr; 1489}; 1490 1491/* Output (16 bytes) */ 1492struct hwrm_func_buf_rgtr_output { 1493 __le16 error_code; 1494 __le16 req_type; 1495 __le16 seq_id; 1496 __le16 resp_len; 1497 __le32 unused_0; 1498 u8 unused_1; 1499 u8 unused_2; 1500 u8 unused_3; 1501 u8 valid; 1502}; 1503 1504/* hwrm_func_drv_qver */ 1505/* Input (24 bytes) */ 1506struct hwrm_func_drv_qver_input { 1507 __le16 req_type; 1508 __le16 cmpl_ring; 1509 __le16 seq_id; 1510 __le16 target_id; 1511 __le64 resp_addr; 1512 __le32 reserved; 1513 __le16 fid; 1514 __le16 unused_0; 1515}; 1516 1517/* Output (16 bytes) */ 1518struct hwrm_func_drv_qver_output { 1519 __le16 error_code; 1520 __le16 req_type; 1521 __le16 seq_id; 1522 __le16 resp_len; 1523 __le16 os_type; 1524 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1525 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1526 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1527 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1528 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1529 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1530 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1531 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1532 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1533 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1534 u8 ver_maj; 1535 u8 ver_min; 1536 u8 ver_upd; 1537 u8 unused_0; 1538 u8 unused_1; 1539 u8 valid; 1540}; 1541 1542/* hwrm_port_phy_cfg */ 1543/* Input (56 bytes) */ 1544struct hwrm_port_phy_cfg_input { 1545 __le16 req_type; 1546 __le16 cmpl_ring; 1547 __le16 seq_id; 1548 __le16 target_id; 1549 __le64 resp_addr; 1550 __le32 flags; 1551 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1552 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL 1553 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1554 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1555 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1556 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1557 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1558 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1559 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1560 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1561 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1562 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1563 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1564 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1565 __le32 enables; 1566 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1567 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1568 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1569 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1570 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1571 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1572 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1573 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1574 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1575 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1576 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1577 __le16 port_id; 1578 __le16 force_link_speed; 1579 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1580 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1581 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1582 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1583 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1584 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1585 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1586 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1587 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1588 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1589 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1590 u8 auto_mode; 1591 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1592 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1593 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1594 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1595 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1596 u8 auto_duplex; 1597 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1598 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1599 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1600 u8 auto_pause; 1601 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1602 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1603 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1604 u8 unused_0; 1605 __le16 auto_link_speed; 1606 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1607 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1608 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1609 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1610 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1611 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1612 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1613 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1614 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1615 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1616 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1617 __le16 auto_link_speed_mask; 1618 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1619 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1620 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1621 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1622 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1623 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1624 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1625 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1626 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1627 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1628 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1629 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1630 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1631 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1632 u8 wirespeed; 1633 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1634 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1635 u8 lpbk; 1636 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1637 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1638 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1639 u8 force_pause; 1640 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1641 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1642 u8 unused_1; 1643 __le32 preemphasis; 1644 __le16 eee_link_speed_mask; 1645 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1646 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1647 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1648 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1649 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1650 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1651 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1652 u8 unused_2; 1653 u8 unused_3; 1654 __le32 tx_lpi_timer; 1655 __le32 unused_4; 1656 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1657 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1658}; 1659 1660/* Output (16 bytes) */ 1661struct hwrm_port_phy_cfg_output { 1662 __le16 error_code; 1663 __le16 req_type; 1664 __le16 seq_id; 1665 __le16 resp_len; 1666 __le32 unused_0; 1667 u8 unused_1; 1668 u8 unused_2; 1669 u8 unused_3; 1670 u8 valid; 1671}; 1672 1673/* hwrm_port_phy_qcfg */ 1674/* Input (24 bytes) */ 1675struct hwrm_port_phy_qcfg_input { 1676 __le16 req_type; 1677 __le16 cmpl_ring; 1678 __le16 seq_id; 1679 __le16 target_id; 1680 __le64 resp_addr; 1681 __le16 port_id; 1682 __le16 unused_0[3]; 1683}; 1684 1685/* Output (96 bytes) */ 1686struct hwrm_port_phy_qcfg_output { 1687 __le16 error_code; 1688 __le16 req_type; 1689 __le16 seq_id; 1690 __le16 resp_len; 1691 u8 link; 1692 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1693 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1694 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1695 u8 unused_0; 1696 __le16 link_speed; 1697 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1698 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1699 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1700 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1701 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1702 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1703 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1704 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1705 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1706 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1707 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1708 u8 duplex; 1709 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF 0x0UL 1710 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL 0x1UL 1711 u8 pause; 1712 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1713 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1714 __le16 support_speeds; 1715 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1716 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1717 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1718 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1719 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1720 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1721 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1722 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1723 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1724 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1725 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1726 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1727 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1728 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1729 __le16 force_link_speed; 1730 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1731 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1732 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1733 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1734 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1735 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1736 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1737 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1738 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1739 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1740 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1741 u8 auto_mode; 1742 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1743 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1744 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1745 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1746 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1747 u8 auto_pause; 1748 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1749 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1750 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1751 __le16 auto_link_speed; 1752 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1753 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1754 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1755 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1756 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1757 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1758 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1759 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1760 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1761 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1762 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1763 __le16 auto_link_speed_mask; 1764 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1765 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1766 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1767 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1768 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1769 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1770 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1771 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1772 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1773 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1774 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1775 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1776 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1777 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1778 u8 wirespeed; 1779 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1780 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1781 u8 lpbk; 1782 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1783 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1784 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1785 u8 force_pause; 1786 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1787 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1788 u8 module_status; 1789 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1790 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1791 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1792 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1793 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1794 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1795 __le32 preemphasis; 1796 u8 phy_maj; 1797 u8 phy_min; 1798 u8 phy_bld; 1799 u8 phy_type; 1800 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1801 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1802 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1803 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1804 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1805 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1806 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1807 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1808 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1809 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1810 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1811 u8 media_type; 1812 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1813 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1814 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1815 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1816 u8 xcvr_pkg_type; 1817 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1818 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1819 u8 eee_config_phy_addr; 1820 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1821 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1822 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1823 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1824 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1825 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1826 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1827 u8 parallel_detect; 1828 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1829 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1830 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1831 __le16 link_partner_adv_speeds; 1832 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1833 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1834 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1835 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1836 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1837 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1838 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1839 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1840 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1841 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1842 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1843 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1844 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1845 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1846 u8 link_partner_adv_auto_mode; 1847 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1848 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1849 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1850 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1851 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1852 u8 link_partner_adv_pause; 1853 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1854 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1855 __le16 adv_eee_link_speed_mask; 1856 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1857 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1858 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1859 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1860 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1861 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1862 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1863 __le16 link_partner_adv_eee_link_speed_mask; 1864 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1865 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1866 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1867 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1868 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1869 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1870 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1871 __le32 xcvr_identifier_type_tx_lpi_timer; 1872 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1873 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1874 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1875 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1876 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1877 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1878 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1879 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1880 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1881 __le16 fec_cfg; 1882 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1883 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1884 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1885 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1886 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1887 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1888 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1889 u8 unused_1; 1890 u8 unused_2; 1891 char phy_vendor_name[16]; 1892 char phy_vendor_partnumber[16]; 1893 __le32 unused_3; 1894 u8 unused_4; 1895 u8 unused_5; 1896 u8 unused_6; 1897 u8 valid; 1898}; 1899 1900/* hwrm_port_mac_cfg */ 1901/* Input (40 bytes) */ 1902struct hwrm_port_mac_cfg_input { 1903 __le16 req_type; 1904 __le16 cmpl_ring; 1905 __le16 seq_id; 1906 __le16 target_id; 1907 __le64 resp_addr; 1908 __le32 flags; 1909 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1910 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1911 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1912 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1913 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1914 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1915 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1916 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1917 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1918 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1919 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1920 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1921 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1922 __le32 enables; 1923 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1924 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1925 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1926 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1927 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1928 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1929 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1930 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1931 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1932 __le16 port_id; 1933 u8 ipg; 1934 u8 lpbk; 1935 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1936 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1937 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1938 u8 vlan_pri2cos_map_pri; 1939 u8 reserved1; 1940 u8 tunnel_pri2cos_map_pri; 1941 u8 dscp2pri_map_pri; 1942 __le16 rx_ts_capture_ptp_msg_type; 1943 __le16 tx_ts_capture_ptp_msg_type; 1944 u8 cos_field_cfg; 1945 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1946 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1947 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1948 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1949 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1950 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1951 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1952 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1953 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1954 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1955 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1956 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1957 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1958 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1959 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1960 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1961 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1962 u8 unused_0[3]; 1963}; 1964 1965/* Output (16 bytes) */ 1966struct hwrm_port_mac_cfg_output { 1967 __le16 error_code; 1968 __le16 req_type; 1969 __le16 seq_id; 1970 __le16 resp_len; 1971 __le16 mru; 1972 __le16 mtu; 1973 u8 ipg; 1974 u8 lpbk; 1975 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1976 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1977 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1978 u8 unused_0; 1979 u8 valid; 1980}; 1981 1982/* hwrm_port_qstats */ 1983/* Input (40 bytes) */ 1984struct hwrm_port_qstats_input { 1985 __le16 req_type; 1986 __le16 cmpl_ring; 1987 __le16 seq_id; 1988 __le16 target_id; 1989 __le64 resp_addr; 1990 __le16 port_id; 1991 u8 unused_0; 1992 u8 unused_1; 1993 u8 unused_2[3]; 1994 u8 unused_3; 1995 __le64 tx_stat_host_addr; 1996 __le64 rx_stat_host_addr; 1997}; 1998 1999/* Output (16 bytes) */ 2000struct hwrm_port_qstats_output {
2001 __le16 error_code; 2002 __le16 req_type; 2003 __le16 seq_id; 2004 __le16 resp_len; 2005 __le16 tx_stat_size; 2006 __le16 rx_stat_size; 2007 u8 unused_0; 2008 u8 unused_1; 2009 u8 unused_2; 2010 u8 valid; 2011}; 2012 2013/* hwrm_port_lpbk_qstats */ 2014/* Input (16 bytes) */ 2015struct hwrm_port_lpbk_qstats_input { 2016 __le16 req_type; 2017 __le16 cmpl_ring; 2018 __le16 seq_id; 2019 __le16 target_id; 2020 __le64 resp_addr; 2021}; 2022 2023/* Output (96 bytes) */ 2024struct hwrm_port_lpbk_qstats_output { 2025 __le16 error_code; 2026 __le16 req_type; 2027 __le16 seq_id; 2028 __le16 resp_len; 2029 __le64 lpbk_ucast_frames; 2030 __le64 lpbk_mcast_frames; 2031 __le64 lpbk_bcast_frames; 2032 __le64 lpbk_ucast_bytes; 2033 __le64 lpbk_mcast_bytes; 2034 __le64 lpbk_bcast_bytes; 2035 __le64 tx_stat_discard; 2036 __le64 tx_stat_error; 2037 __le64 rx_stat_discard; 2038 __le64 rx_stat_error; 2039 __le32 unused_0; 2040 u8 unused_1; 2041 u8 unused_2; 2042 u8 unused_3; 2043 u8 valid; 2044}; 2045 2046/* hwrm_port_clr_stats */ 2047/* Input (24 bytes) */ 2048struct hwrm_port_clr_stats_input { 2049 __le16 req_type; 2050 __le16 cmpl_ring; 2051 __le16 seq_id; 2052 __le16 target_id; 2053 __le64 resp_addr; 2054 __le16 port_id; 2055 __le16 unused_0[3]; 2056}; 2057 2058/* Output (16 bytes) */ 2059struct hwrm_port_clr_stats_output { 2060 __le16 error_code; 2061 __le16 req_type; 2062 __le16 seq_id; 2063 __le16 resp_len; 2064 __le32 unused_0; 2065 u8 unused_1; 2066 u8 unused_2; 2067 u8 unused_3; 2068 u8 valid; 2069}; 2070 2071/* hwrm_port_lpbk_clr_stats */ 2072/* Input (16 bytes) */ 2073struct hwrm_port_lpbk_clr_stats_input { 2074 __le16 req_type; 2075 __le16 cmpl_ring; 2076 __le16 seq_id; 2077 __le16 target_id; 2078 __le64 resp_addr; 2079}; 2080 2081/* Output (16 bytes) */ 2082struct hwrm_port_lpbk_clr_stats_output { 2083 __le16 error_code; 2084 __le16 req_type; 2085 __le16 seq_id; 2086 __le16 resp_len; 2087 __le32 unused_0; 2088 u8 unused_1; 2089 u8 unused_2; 2090 u8 unused_3; 2091 u8 valid; 2092}; 2093 2094/* hwrm_port_blink_led */ 2095/* Input (24 bytes) */ 2096struct hwrm_port_blink_led_input { 2097 __le16 req_type; 2098 __le16 cmpl_ring; 2099 __le16 seq_id; 2100 __le16 target_id; 2101 __le64 resp_addr; 2102 __le32 num_blinks; 2103 __le32 unused_0; 2104}; 2105 2106/* Output (16 bytes) */ 2107struct hwrm_port_blink_led_output { 2108 __le16 error_code; 2109 __le16 req_type; 2110 __le16 seq_id; 2111 __le16 resp_len; 2112 __le32 unused_0; 2113 u8 unused_1; 2114 u8 unused_2; 2115 u8 unused_3; 2116 u8 valid; 2117}; 2118 2119/* hwrm_port_phy_qcaps */ 2120/* Input (24 bytes) */ 2121struct hwrm_port_phy_qcaps_input { 2122 __le16 req_type; 2123 __le16 cmpl_ring; 2124 __le16 seq_id; 2125 __le16 target_id; 2126 __le64 resp_addr; 2127 __le16 port_id; 2128 __le16 unused_0[3]; 2129}; 2130 2131/* Output (24 bytes) */ 2132struct hwrm_port_phy_qcaps_output { 2133 __le16 error_code; 2134 __le16 req_type; 2135 __le16 seq_id; 2136 __le16 resp_len; 2137 u8 eee_supported; 2138 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 2139 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 2140 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 2141 u8 unused_0; 2142 __le16 supported_speeds_force_mode; 2143 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2144 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2145 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2146 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2147 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2148 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2149 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2150 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2151 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2152 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2153 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2154 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2155 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2156 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2157 __le16 supported_speeds_auto_mode; 2158 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2159 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2160 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2162 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2163 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2164 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2165 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2166 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2168 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2169 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2170 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2171 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2172 __le16 supported_speeds_eee_mode; 2173 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2174 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2175 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2176 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2177 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2178 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2179 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2180 __le32 tx_lpi_timer_low; 2181 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2182 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2183 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2184 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2185 __le32 valid_tx_lpi_timer_high; 2186 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2187 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2188 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2189 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2190}; 2191 2192/* hwrm_port_phy_i2c_read */ 2193/* Input (40 bytes) */ 2194struct hwrm_port_phy_i2c_read_input { 2195 __le16 req_type; 2196 __le16 cmpl_ring; 2197 __le16 seq_id; 2198 __le16 target_id; 2199 __le64 resp_addr; 2200 __le32 flags; 2201 __le32 enables; 2202 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2203 __le16 port_id; 2204 u8 i2c_slave_addr; 2205 u8 unused_0; 2206 __le16 page_number; 2207 __le16 page_offset; 2208 u8 data_length; 2209 u8 unused_1[7]; 2210}; 2211 2212/* Output (80 bytes) */ 2213struct hwrm_port_phy_i2c_read_output { 2214 __le16 error_code; 2215 __le16 req_type; 2216 __le16 seq_id; 2217 __le16 resp_len; 2218 __le32 data[16]; 2219 __le32 unused_0; 2220 u8 unused_1; 2221 u8 unused_2; 2222 u8 unused_3; 2223 u8 valid; 2224}; 2225 2226/* hwrm_queue_qportcfg */ 2227/* Input (24 bytes) */ 2228struct hwrm_queue_qportcfg_input { 2229 __le16 req_type; 2230 __le16 cmpl_ring; 2231 __le16 seq_id; 2232 __le16 target_id; 2233 __le64 resp_addr; 2234 __le32 flags; 2235 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2236 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2237 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2238 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2239 __le16 port_id; 2240 __le16 unused_0; 2241}; 2242 2243/* Output (32 bytes) */ 2244struct hwrm_queue_qportcfg_output { 2245 __le16 error_code; 2246 __le16 req_type; 2247 __le16 seq_id; 2248 __le16 resp_len; 2249 u8 max_configurable_queues; 2250 u8 max_configurable_lossless_queues; 2251 u8 queue_cfg_allowed; 2252 u8 queue_cfg_info; 2253 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2254 u8 queue_pfcenable_cfg_allowed; 2255 u8 queue_pri2cos_cfg_allowed; 2256 u8 queue_cos2bw_cfg_allowed; 2257 u8 queue_id0; 2258 u8 queue_id0_service_profile; 2259 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2260 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2262 u8 queue_id1; 2263 u8 queue_id1_service_profile; 2264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2267 u8 queue_id2; 2268 u8 queue_id2_service_profile; 2269 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2270 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2271 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2272 u8 queue_id3; 2273 u8 queue_id3_service_profile; 2274 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2275 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2276 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2277 u8 queue_id4; 2278 u8 queue_id4_service_profile; 2279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2281 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2282 u8 queue_id5; 2283 u8 queue_id5_service_profile; 2284 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2285 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2286 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2287 u8 queue_id6; 2288 u8 queue_id6_service_profile; 2289 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2290 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2291 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2292 u8 queue_id7; 2293 u8 queue_id7_service_profile; 2294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2296 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2297 u8 valid; 2298}; 2299 2300/* hwrm_queue_cfg */ 2301/* Input (40 bytes) */ 2302struct hwrm_queue_cfg_input { 2303 __le16 req_type; 2304 __le16 cmpl_ring; 2305 __le16 seq_id; 2306 __le16 target_id; 2307 __le64 resp_addr; 2308 __le32 flags; 2309 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2310 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2311 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2312 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2313 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2314 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2315 __le32 enables; 2316 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2317 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2318 __le32 queue_id; 2319 __le32 dflt_len; 2320 u8 service_profile; 2321 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2322 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2323 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2324 u8 unused_0[7]; 2325}; 2326 2327/* Output (16 bytes) */ 2328struct hwrm_queue_cfg_output { 2329 __le16 error_code; 2330 __le16 req_type; 2331 __le16 seq_id; 2332 __le16 resp_len; 2333 __le32 unused_0; 2334 u8 unused_1; 2335 u8 unused_2; 2336 u8 unused_3; 2337 u8 valid; 2338}; 2339 2340/* hwrm_queue_pfcenable_cfg */ 2341/* Input (24 bytes) */ 2342struct hwrm_queue_pfcenable_cfg_input { 2343 __le16 req_type; 2344 __le16 cmpl_ring; 2345 __le16 seq_id; 2346 __le16 target_id; 2347 __le64 resp_addr; 2348 __le32 flags; 2349 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2350 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2351 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2352 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2353 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2354 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2355 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2356 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2357 __le16 port_id; 2358 __le16 unused_0; 2359}; 2360 2361/* Output (16 bytes) */ 2362struct hwrm_queue_pfcenable_cfg_output { 2363 __le16 error_code; 2364 __le16 req_type; 2365 __le16 seq_id; 2366 __le16 resp_len; 2367 __le32 unused_0; 2368 u8 unused_1; 2369 u8 unused_2; 2370 u8 unused_3; 2371 u8 valid; 2372}; 2373 2374/* hwrm_queue_pri2cos_cfg */ 2375/* Input (40 bytes) */ 2376struct hwrm_queue_pri2cos_cfg_input { 2377 __le16 req_type; 2378 __le16 cmpl_ring; 2379 __le16 seq_id; 2380 __le16 target_id; 2381 __le64 resp_addr; 2382 __le32 flags; 2383 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2384 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2385 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2386 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2387 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2388 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2389 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2390 __le32 enables; 2391 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2392 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2393 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2394 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2395 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2396 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2397 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2398 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2399 u8 port_id; 2400 u8 pri0_cos_queue_id; 2401 u8 pri1_cos_queue_id; 2402 u8 pri2_cos_queue_id; 2403 u8 pri3_cos_queue_id; 2404 u8 pri4_cos_queue_id; 2405 u8 pri5_cos_queue_id; 2406 u8 pri6_cos_queue_id; 2407 u8 pri7_cos_queue_id; 2408 u8 unused_0[7]; 2409}; 2410 2411/* Output (16 bytes) */ 2412struct hwrm_queue_pri2cos_cfg_output { 2413 __le16 error_code; 2414 __le16 req_type; 2415 __le16 seq_id; 2416 __le16 resp_len; 2417 __le32 unused_0; 2418 u8 unused_1; 2419 u8 unused_2; 2420 u8 unused_3; 2421 u8 valid; 2422}; 2423 2424/* hwrm_queue_cos2bw_cfg */ 2425/* Input (128 bytes) */ 2426struct hwrm_queue_cos2bw_cfg_input { 2427 __le16 req_type; 2428 __le16 cmpl_ring; 2429 __le16 seq_id; 2430 __le16 target_id; 2431 __le64 resp_addr; 2432 __le32 flags; 2433 __le32 enables; 2434 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2435 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2436 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2437 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2438 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2439 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2440 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2441 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2442 __le16 port_id; 2443 u8 queue_id0; 2444 u8 unused_0; 2445 __le32 queue_id0_min_bw; 2446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_RSVD 0x10000000UL 2449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2455 __le32 queue_id0_max_bw; 2456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_RSVD 0x10000000UL 2459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2465 u8 queue_id0_tsa_assign; 2466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2470 u8 queue_id0_pri_lvl; 2471 u8 queue_id0_bw_weight; 2472 u8 queue_id1; 2473 __le32 queue_id1_min_bw; 2474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_RSVD 0x10000000UL 2477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2483 __le32 queue_id1_max_bw; 2484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_RSVD 0x10000000UL 2487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2493 u8 queue_id1_tsa_assign; 2494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2498 u8 queue_id1_pri_lvl; 2499 u8 queue_id1_bw_weight; 2500 u8 queue_id2; 2501 __le32 queue_id2_min_bw; 2502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_RSVD 0x10000000UL 2505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2511 __le32 queue_id2_max_bw; 2512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_RSVD 0x10000000UL 2515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2519 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2521 u8 queue_id2_tsa_assign; 2522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2526 u8 queue_id2_pri_lvl; 2527 u8 queue_id2_bw_weight; 2528 u8 queue_id3; 2529 __le32 queue_id3_min_bw; 2530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_RSVD 0x10000000UL 2533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2539 __le32 queue_id3_max_bw; 2540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_RSVD 0x10000000UL 2543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2549 u8 queue_id3_tsa_assign; 2550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2554 u8 queue_id3_pri_lvl; 2555 u8 queue_id3_bw_weight; 2556 u8 queue_id4; 2557 __le32 queue_id4_min_bw; 2558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_RSVD 0x10000000UL 2561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2567 __le32 queue_id4_max_bw; 2568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_RSVD 0x10000000UL 2571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2575 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2577 u8 queue_id4_tsa_assign; 2578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2580 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2582 u8 queue_id4_pri_lvl; 2583 u8 queue_id4_bw_weight; 2584 u8 queue_id5; 2585 __le32 queue_id5_min_bw; 2586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_RSVD 0x10000000UL 2589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2595 __le32 queue_id5_max_bw; 2596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_RSVD 0x10000000UL 2599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2605 u8 queue_id5_tsa_assign; 2606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2610 u8 queue_id5_pri_lvl; 2611 u8 queue_id5_bw_weight; 2612 u8 queue_id6; 2613 __le32 queue_id6_min_bw; 2614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_RSVD 0x10000000UL 2617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2623 __le32 queue_id6_max_bw; 2624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_RSVD 0x10000000UL 2627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2633 u8 queue_id6_tsa_assign; 2634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2638 u8 queue_id6_pri_lvl; 2639 u8 queue_id6_bw_weight; 2640 u8 queue_id7; 2641 __le32 queue_id7_min_bw; 2642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_RSVD 0x10000000UL 2645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2651 __le32 queue_id7_max_bw; 2652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_RSVD 0x10000000UL 2655 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2660 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2661 u8 queue_id7_tsa_assign; 2662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2663 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2666 u8 queue_id7_pri_lvl; 2667 u8 queue_id7_bw_weight; 2668 u8 unused_1[5]; 2669}; 2670 2671/* Output (16 bytes) */ 2672struct hwrm_queue_cos2bw_cfg_output { 2673 __le16 error_code; 2674 __le16 req_type; 2675 __le16 seq_id; 2676 __le16 resp_len; 2677 __le32 unused_0; 2678 u8 unused_1; 2679 u8 unused_2; 2680 u8 unused_3; 2681 u8 valid; 2682}; 2683 2684/* hwrm_vnic_alloc */ 2685/* Input (24 bytes) */ 2686struct hwrm_vnic_alloc_input { 2687 __le16 req_type; 2688 __le16 cmpl_ring; 2689 __le16 seq_id; 2690 __le16 target_id; 2691 __le64 resp_addr; 2692 __le32 flags; 2693 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2694 __le32 unused_0; 2695}; 2696 2697/* Output (16 bytes) */ 2698struct hwrm_vnic_alloc_output { 2699 __le16 error_code; 2700 __le16 req_type; 2701 __le16 seq_id; 2702 __le16 resp_len; 2703 __le32 vnic_id; 2704 u8 unused_0; 2705 u8 unused_1; 2706 u8 unused_2; 2707 u8 valid; 2708}; 2709 2710/* hwrm_vnic_free */ 2711/* Input (24 bytes) */ 2712struct hwrm_vnic_free_input { 2713 __le16 req_type; 2714 __le16 cmpl_ring; 2715 __le16 seq_id; 2716 __le16 target_id; 2717 __le64 resp_addr; 2718 __le32 vnic_id; 2719 __le32 unused_0; 2720}; 2721 2722/* Output (16 bytes) */ 2723struct hwrm_vnic_free_output { 2724 __le16 error_code; 2725 __le16 req_type; 2726 __le16 seq_id; 2727 __le16 resp_len; 2728 __le32 unused_0; 2729 u8 unused_1; 2730 u8 unused_2; 2731 u8 unused_3; 2732 u8 valid; 2733}; 2734 2735/* hwrm_vnic_cfg */ 2736/* Input (40 bytes) */ 2737struct hwrm_vnic_cfg_input { 2738 __le16 req_type; 2739 __le16 cmpl_ring; 2740 __le16 seq_id; 2741 __le16 target_id; 2742 __le64 resp_addr; 2743 __le32 flags; 2744 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2745 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2746 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 2747 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 2748 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 2749 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 2750 __le32 enables; 2751 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2752 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2753 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2754 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2755 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2756 __le16 vnic_id; 2757 __le16 dflt_ring_grp; 2758 __le16 rss_rule; 2759 __le16 cos_rule; 2760 __le16 lb_rule; 2761 __le16 mru; 2762 __le32 unused_0; 2763}; 2764 2765/* Output (16 bytes) */ 2766struct hwrm_vnic_cfg_output { 2767 __le16 error_code; 2768 __le16 req_type; 2769 __le16 seq_id; 2770 __le16 resp_len; 2771 __le32 unused_0; 2772 u8 unused_1; 2773 u8 unused_2; 2774 u8 unused_3; 2775 u8 valid; 2776}; 2777 2778/* hwrm_vnic_tpa_cfg */ 2779/* Input (40 bytes) */ 2780struct hwrm_vnic_tpa_cfg_input { 2781 __le16 req_type; 2782 __le16 cmpl_ring; 2783 __le16 seq_id; 2784 __le16 target_id; 2785 __le64 resp_addr; 2786 __le32 flags; 2787 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2788 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2789 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2790 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2791 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2792 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2793 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2794 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2795 __le32 enables; 2796 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2797 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2798 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2799 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2800 __le16 vnic_id; 2801 __le16 max_agg_segs; 2802 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 2803 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 2804 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 2805 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 2806 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 2807 __le16 max_aggs; 2808 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 2809 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 2810 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 2811 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 2812 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 2813 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 2814 u8 unused_0; 2815 u8 unused_1; 2816 __le32 max_agg_timer; 2817 __le32 min_agg_len; 2818}; 2819 2820/* Output (16 bytes) */ 2821struct hwrm_vnic_tpa_cfg_output { 2822 __le16 error_code; 2823 __le16 req_type; 2824 __le16 seq_id; 2825 __le16 resp_len; 2826 __le32 unused_0; 2827 u8 unused_1; 2828 u8 unused_2; 2829 u8 unused_3; 2830 u8 valid; 2831}; 2832 2833/* hwrm_vnic_rss_cfg */ 2834/* Input (48 bytes) */ 2835struct hwrm_vnic_rss_cfg_input { 2836 __le16 req_type; 2837 __le16 cmpl_ring; 2838 __le16 seq_id; 2839 __le16 target_id; 2840 __le64 resp_addr; 2841 __le32 hash_type; 2842 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2843 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2844 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2845 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2846 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2847 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2848 __le32 unused_0; 2849 __le64 ring_grp_tbl_addr; 2850 __le64 hash_key_tbl_addr; 2851 __le16 rss_ctx_idx; 2852 __le16 unused_1[3]; 2853}; 2854 2855/* Output (16 bytes) */ 2856struct hwrm_vnic_rss_cfg_output { 2857 __le16 error_code; 2858 __le16 req_type; 2859 __le16 seq_id; 2860 __le16 resp_len; 2861 __le32 unused_0; 2862 u8 unused_1; 2863 u8 unused_2; 2864 u8 unused_3; 2865 u8 valid; 2866}; 2867 2868/* hwrm_vnic_plcmodes_cfg */ 2869/* Input (40 bytes) */ 2870struct hwrm_vnic_plcmodes_cfg_input { 2871 __le16 req_type; 2872 __le16 cmpl_ring; 2873 __le16 seq_id; 2874 __le16 target_id; 2875 __le64 resp_addr; 2876 __le32 flags; 2877 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2878 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2879 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2880 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2881 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2882 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2883 __le32 enables; 2884 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2885 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2886 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2887 __le32 vnic_id; 2888 __le16 jumbo_thresh; 2889 __le16 hds_offset; 2890 __le16 hds_threshold; 2891 __le16 unused_0[3]; 2892}; 2893 2894/* Output (16 bytes) */ 2895struct hwrm_vnic_plcmodes_cfg_output { 2896 __le16 error_code; 2897 __le16 req_type; 2898 __le16 seq_id; 2899 __le16 resp_len; 2900 __le32 unused_0; 2901 u8 unused_1; 2902 u8 unused_2; 2903 u8 unused_3; 2904 u8 valid; 2905}; 2906 2907/* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2908/* Input (16 bytes) */ 2909struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2910 __le16 req_type; 2911 __le16 cmpl_ring; 2912 __le16 seq_id; 2913 __le16 target_id; 2914 __le64 resp_addr; 2915}; 2916 2917/* Output (16 bytes) */ 2918struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2919 __le16 error_code; 2920 __le16 req_type; 2921 __le16 seq_id; 2922 __le16 resp_len; 2923 __le16 rss_cos_lb_ctx_id; 2924 u8 unused_0; 2925 u8 unused_1; 2926 u8 unused_2; 2927 u8 unused_3; 2928 u8 unused_4; 2929 u8 valid; 2930}; 2931 2932/* hwrm_vnic_rss_cos_lb_ctx_free */ 2933/* Input (24 bytes) */ 2934struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2935 __le16 req_type; 2936 __le16 cmpl_ring; 2937 __le16 seq_id; 2938 __le16 target_id; 2939 __le64 resp_addr; 2940 __le16 rss_cos_lb_ctx_id; 2941 __le16 unused_0[3]; 2942}; 2943 2944/* Output (16 bytes) */ 2945struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2946 __le16 error_code; 2947 __le16 req_type; 2948 __le16 seq_id; 2949 __le16 resp_len; 2950 __le32 unused_0; 2951 u8 unused_1; 2952 u8 unused_2; 2953 u8 unused_3; 2954 u8 valid; 2955}; 2956 2957/* hwrm_ring_alloc */ 2958/* Input (80 bytes) */ 2959struct hwrm_ring_alloc_input { 2960 __le16 req_type; 2961 __le16 cmpl_ring; 2962 __le16 seq_id; 2963 __le16 target_id; 2964 __le64 resp_addr; 2965 __le32 enables; 2966 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 2967 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 2968 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 2969 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2970 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 2971 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2972 u8 ring_type; 2973 #define RING_ALLOC_REQ_RING_TYPE_CMPL 0x0UL 2974 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 2975 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 2976 u8 unused_0; 2977 __le16 unused_1; 2978 __le64 page_tbl_addr; 2979 __le32 fbo; 2980 u8 page_size; 2981 u8 page_tbl_depth; 2982 u8 unused_2; 2983 u8 unused_3; 2984 __le32 length; 2985 __le16 logical_id; 2986 __le16 cmpl_ring_id; 2987 __le16 queue_id; 2988 u8 unused_4; 2989 u8 unused_5; 2990 __le32 reserved1; 2991 __le16 ring_arb_cfg; 2992 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 2993 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 2994 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 2995 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 2996 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 2997 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 2998 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 2999 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3000 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
3001 u8 unused_6; 3002 u8 unused_7; 3003 __le32 reserved3; 3004 __le32 stat_ctx_id; 3005 __le32 reserved4; 3006 __le32 max_bw; 3007 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3008 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3009 #define RING_ALLOC_REQ_MAX_BW_RSVD 0x10000000UL 3010 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3011 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3012 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 3013 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3014 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3015 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3016 u8 int_mode; 3017 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3018 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3019 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3020 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3021 u8 unused_8[3]; 3022}; 3023 3024/* Output (16 bytes) */ 3025struct hwrm_ring_alloc_output { 3026 __le16 error_code; 3027 __le16 req_type; 3028 __le16 seq_id; 3029 __le16 resp_len; 3030 __le16 ring_id; 3031 __le16 logical_ring_id; 3032 u8 unused_0; 3033 u8 unused_1; 3034 u8 unused_2; 3035 u8 valid; 3036}; 3037 3038/* hwrm_ring_free */ 3039/* Input (24 bytes) */ 3040struct hwrm_ring_free_input { 3041 __le16 req_type; 3042 __le16 cmpl_ring; 3043 __le16 seq_id; 3044 __le16 target_id; 3045 __le64 resp_addr; 3046 u8 ring_type; 3047 #define RING_FREE_REQ_RING_TYPE_CMPL 0x0UL 3048 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3049 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3050 u8 unused_0; 3051 __le16 ring_id; 3052 __le32 unused_1; 3053}; 3054 3055/* Output (16 bytes) */ 3056struct hwrm_ring_free_output { 3057 __le16 error_code; 3058 __le16 req_type; 3059 __le16 seq_id; 3060 __le16 resp_len; 3061 __le32 unused_0; 3062 u8 unused_1; 3063 u8 unused_2; 3064 u8 unused_3; 3065 u8 valid; 3066}; 3067 3068/* hwrm_ring_cmpl_ring_qaggint_params */ 3069/* Input (24 bytes) */ 3070struct hwrm_ring_cmpl_ring_qaggint_params_input { 3071 __le16 req_type; 3072 __le16 cmpl_ring; 3073 __le16 seq_id; 3074 __le16 target_id; 3075 __le64 resp_addr; 3076 __le16 ring_id; 3077 __le16 unused_0[3]; 3078}; 3079 3080/* Output (32 bytes) */ 3081struct hwrm_ring_cmpl_ring_qaggint_params_output { 3082 __le16 error_code; 3083 __le16 req_type; 3084 __le16 seq_id; 3085 __le16 resp_len; 3086 __le16 flags; 3087 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3088 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3089 __le16 num_cmpl_dma_aggr; 3090 __le16 num_cmpl_dma_aggr_during_int; 3091 __le16 cmpl_aggr_dma_tmr; 3092 __le16 cmpl_aggr_dma_tmr_during_int; 3093 __le16 int_lat_tmr_min; 3094 __le16 int_lat_tmr_max; 3095 __le16 num_cmpl_aggr_int; 3096 __le32 unused_0; 3097 u8 unused_1; 3098 u8 unused_2; 3099 u8 unused_3; 3100 u8 valid; 3101}; 3102 3103/* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3104/* Input (40 bytes) */ 3105struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3106 __le16 req_type; 3107 __le16 cmpl_ring; 3108 __le16 seq_id; 3109 __le16 target_id; 3110 __le64 resp_addr; 3111 __le16 ring_id; 3112 __le16 flags; 3113 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3114 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3115 __le16 num_cmpl_dma_aggr; 3116 __le16 num_cmpl_dma_aggr_during_int; 3117 __le16 cmpl_aggr_dma_tmr; 3118 __le16 cmpl_aggr_dma_tmr_during_int; 3119 __le16 int_lat_tmr_min; 3120 __le16 int_lat_tmr_max; 3121 __le16 num_cmpl_aggr_int; 3122 __le16 unused_0[3]; 3123}; 3124 3125/* Output (16 bytes) */ 3126struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3127 __le16 error_code; 3128 __le16 req_type; 3129 __le16 seq_id; 3130 __le16 resp_len; 3131 __le32 unused_0; 3132 u8 unused_1; 3133 u8 unused_2; 3134 u8 unused_3; 3135 u8 valid; 3136}; 3137 3138/* hwrm_ring_reset */ 3139/* Input (24 bytes) */ 3140struct hwrm_ring_reset_input { 3141 __le16 req_type; 3142 __le16 cmpl_ring; 3143 __le16 seq_id; 3144 __le16 target_id; 3145 __le64 resp_addr; 3146 u8 ring_type; 3147 #define RING_RESET_REQ_RING_TYPE_CMPL 0x0UL 3148 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3149 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3150 u8 unused_0; 3151 __le16 ring_id; 3152 __le32 unused_1; 3153}; 3154 3155/* Output (16 bytes) */ 3156struct hwrm_ring_reset_output { 3157 __le16 error_code; 3158 __le16 req_type; 3159 __le16 seq_id; 3160 __le16 resp_len; 3161 __le32 unused_0; 3162 u8 unused_1; 3163 u8 unused_2; 3164 u8 unused_3; 3165 u8 valid; 3166}; 3167 3168/* hwrm_ring_grp_alloc */ 3169/* Input (24 bytes) */ 3170struct hwrm_ring_grp_alloc_input { 3171 __le16 req_type; 3172 __le16 cmpl_ring; 3173 __le16 seq_id; 3174 __le16 target_id; 3175 __le64 resp_addr; 3176 __le16 cr; 3177 __le16 rr; 3178 __le16 ar; 3179 __le16 sc; 3180}; 3181 3182/* Output (16 bytes) */ 3183struct hwrm_ring_grp_alloc_output { 3184 __le16 error_code; 3185 __le16 req_type; 3186 __le16 seq_id; 3187 __le16 resp_len; 3188 __le32 ring_group_id; 3189 u8 unused_0; 3190 u8 unused_1; 3191 u8 unused_2; 3192 u8 valid; 3193}; 3194 3195/* hwrm_ring_grp_free */ 3196/* Input (24 bytes) */ 3197struct hwrm_ring_grp_free_input { 3198 __le16 req_type; 3199 __le16 cmpl_ring; 3200 __le16 seq_id; 3201 __le16 target_id; 3202 __le64 resp_addr; 3203 __le32 ring_group_id; 3204 __le32 unused_0; 3205}; 3206 3207/* Output (16 bytes) */ 3208struct hwrm_ring_grp_free_output { 3209 __le16 error_code; 3210 __le16 req_type; 3211 __le16 seq_id; 3212 __le16 resp_len; 3213 __le32 unused_0; 3214 u8 unused_1; 3215 u8 unused_2; 3216 u8 unused_3; 3217 u8 valid; 3218}; 3219 3220/* hwrm_cfa_l2_filter_alloc */ 3221/* Input (96 bytes) */ 3222struct hwrm_cfa_l2_filter_alloc_input { 3223 __le16 req_type; 3224 __le16 cmpl_ring; 3225 __le16 seq_id; 3226 __le16 target_id; 3227 __le64 resp_addr; 3228 __le32 flags; 3229 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3230 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3231 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3232 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3233 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3234 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3235 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3236 __le32 enables; 3237 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3238 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3239 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3240 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3241 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3242 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3243 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3244 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3245 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3246 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3247 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3248 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3249 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3250 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3251 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3252 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3253 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3254 u8 l2_addr[6]; 3255 u8 unused_0; 3256 u8 unused_1; 3257 u8 l2_addr_mask[6]; 3258 __le16 l2_ovlan; 3259 __le16 l2_ovlan_mask; 3260 __le16 l2_ivlan; 3261 __le16 l2_ivlan_mask; 3262 u8 unused_2; 3263 u8 unused_3; 3264 u8 t_l2_addr[6]; 3265 u8 unused_4; 3266 u8 unused_5; 3267 u8 t_l2_addr_mask[6]; 3268 __le16 t_l2_ovlan; 3269 __le16 t_l2_ovlan_mask; 3270 __le16 t_l2_ivlan; 3271 __le16 t_l2_ivlan_mask; 3272 u8 src_type; 3273 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3274 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3275 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3276 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3277 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3278 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3279 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3280 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3281 u8 unused_6; 3282 __le32 src_id; 3283 u8 tunnel_type; 3284 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3285 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3286 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3287 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3288 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3289 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3290 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3291 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3292 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3293 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3294 u8 unused_7; 3295 __le16 dst_id; 3296 __le16 mirror_vnic_id; 3297 u8 pri_hint; 3298 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3299 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3300 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3301 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 3302 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 3303 u8 unused_8; 3304 __le32 unused_9; 3305 __le64 l2_filter_id_hint; 3306}; 3307 3308/* Output (24 bytes) */ 3309struct hwrm_cfa_l2_filter_alloc_output { 3310 __le16 error_code; 3311 __le16 req_type; 3312 __le16 seq_id; 3313 __le16 resp_len; 3314 __le64 l2_filter_id; 3315 __le32 flow_id; 3316 u8 unused_0; 3317 u8 unused_1; 3318 u8 unused_2; 3319 u8 valid; 3320}; 3321 3322/* hwrm_cfa_l2_filter_free */ 3323/* Input (24 bytes) */ 3324struct hwrm_cfa_l2_filter_free_input { 3325 __le16 req_type; 3326 __le16 cmpl_ring; 3327 __le16 seq_id; 3328 __le16 target_id; 3329 __le64 resp_addr; 3330 __le64 l2_filter_id; 3331}; 3332 3333/* Output (16 bytes) */ 3334struct hwrm_cfa_l2_filter_free_output { 3335 __le16 error_code; 3336 __le16 req_type; 3337 __le16 seq_id; 3338 __le16 resp_len; 3339 __le32 unused_0; 3340 u8 unused_1; 3341 u8 unused_2; 3342 u8 unused_3; 3343 u8 valid; 3344}; 3345 3346/* hwrm_cfa_l2_filter_cfg */ 3347/* Input (40 bytes) */ 3348struct hwrm_cfa_l2_filter_cfg_input { 3349 __le16 req_type; 3350 __le16 cmpl_ring; 3351 __le16 seq_id; 3352 __le16 target_id; 3353 __le64 resp_addr; 3354 __le32 flags; 3355 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3356 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3357 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3358 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3359 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3360 __le32 enables; 3361 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3362 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3363 __le64 l2_filter_id; 3364 __le32 dst_id; 3365 __le32 new_mirror_vnic_id; 3366}; 3367 3368/* Output (16 bytes) */ 3369struct hwrm_cfa_l2_filter_cfg_output { 3370 __le16 error_code; 3371 __le16 req_type; 3372 __le16 seq_id; 3373 __le16 resp_len; 3374 __le32 unused_0; 3375 u8 unused_1; 3376 u8 unused_2; 3377 u8 unused_3; 3378 u8 valid; 3379}; 3380 3381/* hwrm_cfa_l2_set_rx_mask */ 3382/* Input (56 bytes) */ 3383struct hwrm_cfa_l2_set_rx_mask_input { 3384 __le16 req_type; 3385 __le16 cmpl_ring; 3386 __le16 seq_id; 3387 __le16 target_id; 3388 __le64 resp_addr; 3389 __le32 vnic_id; 3390 __le32 mask; 3391 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3392 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3393 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3394 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3395 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3396 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3397 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 3398 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 3399 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 3400 __le64 mc_tbl_addr; 3401 __le32 num_mc_entries; 3402 __le32 unused_0; 3403 __le64 vlan_tag_tbl_addr; 3404 __le32 num_vlan_tags; 3405 __le32 unused_1; 3406}; 3407 3408/* Output (16 bytes) */ 3409struct hwrm_cfa_l2_set_rx_mask_output { 3410 __le16 error_code; 3411 __le16 req_type; 3412 __le16 seq_id; 3413 __le16 resp_len; 3414 __le32 unused_0; 3415 u8 unused_1; 3416 u8 unused_2; 3417 u8 unused_3; 3418 u8 valid; 3419}; 3420 3421/* hwrm_cfa_tunnel_filter_alloc */ 3422/* Input (88 bytes) */ 3423struct hwrm_cfa_tunnel_filter_alloc_input { 3424 __le16 req_type; 3425 __le16 cmpl_ring; 3426 __le16 seq_id; 3427 __le16 target_id; 3428 __le64 resp_addr; 3429 __le32 flags; 3430 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3431 __le32 enables; 3432 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3433 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3434 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3435 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3436 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3437 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3438 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3439 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3440 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3441 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3442 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3443 __le64 l2_filter_id; 3444 u8 l2_addr[6]; 3445 __le16 l2_ivlan; 3446 __le32 l3_addr[4]; 3447 __le32 t_l3_addr[4]; 3448 u8 l3_addr_type; 3449 u8 t_l3_addr_type; 3450 u8 tunnel_type; 3451 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3452 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3453 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3454 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3455 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3456 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3457 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3458 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3459 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3460 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3461 u8 unused_0; 3462 __le32 vni; 3463 __le32 dst_vnic_id; 3464 __le32 mirror_vnic_id; 3465}; 3466 3467/* Output (24 bytes) */ 3468struct hwrm_cfa_tunnel_filter_alloc_output { 3469 __le16 error_code; 3470 __le16 req_type; 3471 __le16 seq_id; 3472 __le16 resp_len; 3473 __le64 tunnel_filter_id; 3474 __le32 flow_id; 3475 u8 unused_0; 3476 u8 unused_1; 3477 u8 unused_2; 3478 u8 valid; 3479}; 3480 3481/* hwrm_cfa_tunnel_filter_free */ 3482/* Input (24 bytes) */ 3483struct hwrm_cfa_tunnel_filter_free_input { 3484 __le16 req_type; 3485 __le16 cmpl_ring; 3486 __le16 seq_id; 3487 __le16 target_id; 3488 __le64 resp_addr; 3489 __le64 tunnel_filter_id; 3490}; 3491 3492/* Output (16 bytes) */ 3493struct hwrm_cfa_tunnel_filter_free_output { 3494 __le16 error_code; 3495 __le16 req_type; 3496 __le16 seq_id; 3497 __le16 resp_len; 3498 __le32 unused_0; 3499 u8 unused_1; 3500 u8 unused_2; 3501 u8 unused_3; 3502 u8 valid; 3503}; 3504 3505/* hwrm_cfa_encap_record_alloc */ 3506/* Input (32 bytes) */ 3507struct hwrm_cfa_encap_record_alloc_input { 3508 __le16 req_type; 3509 __le16 cmpl_ring; 3510 __le16 seq_id; 3511 __le16 target_id; 3512 __le64 resp_addr; 3513 __le32 flags; 3514 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3515 u8 encap_type; 3516 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 3517 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 3518 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 3519 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 3520 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 3521 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 3522 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 3523 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 3524 u8 unused_0; 3525 __le16 unused_1; 3526 __le32 encap_data[16]; 3527}; 3528 3529/* Output (16 bytes) */ 3530struct hwrm_cfa_encap_record_alloc_output { 3531 __le16 error_code; 3532 __le16 req_type; 3533 __le16 seq_id; 3534 __le16 resp_len; 3535 __le32 encap_record_id; 3536 u8 unused_0; 3537 u8 unused_1; 3538 u8 unused_2; 3539 u8 valid; 3540}; 3541 3542/* hwrm_cfa_encap_record_free */ 3543/* Input (24 bytes) */ 3544struct hwrm_cfa_encap_record_free_input { 3545 __le16 req_type; 3546 __le16 cmpl_ring; 3547 __le16 seq_id; 3548 __le16 target_id; 3549 __le64 resp_addr; 3550 __le32 encap_record_id; 3551 __le32 unused_0; 3552}; 3553 3554/* Output (16 bytes) */ 3555struct hwrm_cfa_encap_record_free_output { 3556 __le16 error_code; 3557 __le16 req_type; 3558 __le16 seq_id; 3559 __le16 resp_len; 3560 __le32 unused_0; 3561 u8 unused_1; 3562 u8 unused_2; 3563 u8 unused_3; 3564 u8 valid; 3565}; 3566 3567/* hwrm_cfa_ntuple_filter_alloc */ 3568/* Input (128 bytes) */ 3569struct hwrm_cfa_ntuple_filter_alloc_input { 3570 __le16 req_type; 3571 __le16 cmpl_ring; 3572 __le16 seq_id; 3573 __le16 target_id; 3574 __le64 resp_addr; 3575 __le32 flags; 3576 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3577 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3578 __le32 enables; 3579 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3580 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3581 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3582 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3583 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3584 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3585 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3586 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3587 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3588 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3589 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3590 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3591 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3592 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3593 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3594 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3595 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 3596 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3597 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 3598 __le64 l2_filter_id; 3599 u8 src_macaddr[6]; 3600 __be16 ethertype; 3601 u8 ip_addr_type; 3602 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 3603 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 3604 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 3605 u8 ip_protocol; 3606 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 3607 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x6UL 3608 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x11UL 3609 __le16 dst_id; 3610 __le16 mirror_vnic_id; 3611 u8 tunnel_type; 3612 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3613 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3614 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3615 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3616 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3617 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3618 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3619 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3620 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3621 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3622 u8 pri_hint; 3623 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3624 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 3625 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 3626 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 3627 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 3628 __be32 src_ipaddr[4]; 3629 __be32 src_ipaddr_mask[4]; 3630 __be32 dst_ipaddr[4]; 3631 __be32 dst_ipaddr_mask[4]; 3632 __be16 src_port; 3633 __be16 src_port_mask; 3634 __be16 dst_port; 3635 __be16 dst_port_mask; 3636 __le64 ntuple_filter_id_hint; 3637}; 3638 3639/* Output (24 bytes) */ 3640struct hwrm_cfa_ntuple_filter_alloc_output { 3641 __le16 error_code; 3642 __le16 req_type; 3643 __le16 seq_id; 3644 __le16 resp_len; 3645 __le64 ntuple_filter_id; 3646 __le32 flow_id; 3647 u8 unused_0; 3648 u8 unused_1; 3649 u8 unused_2; 3650 u8 valid; 3651}; 3652 3653/* hwrm_cfa_ntuple_filter_free */ 3654/* Input (24 bytes) */ 3655struct hwrm_cfa_ntuple_filter_free_input { 3656 __le16 req_type; 3657 __le16 cmpl_ring; 3658 __le16 seq_id; 3659 __le16 target_id; 3660 __le64 resp_addr; 3661 __le64 ntuple_filter_id; 3662}; 3663 3664/* Output (16 bytes) */ 3665struct hwrm_cfa_ntuple_filter_free_output { 3666 __le16 error_code; 3667 __le16 req_type; 3668 __le16 seq_id; 3669 __le16 resp_len; 3670 __le32 unused_0; 3671 u8 unused_1; 3672 u8 unused_2; 3673 u8 unused_3; 3674 u8 valid; 3675}; 3676 3677/* hwrm_cfa_ntuple_filter_cfg */ 3678/* Input (40 bytes) */ 3679struct hwrm_cfa_ntuple_filter_cfg_input { 3680 __le16 req_type; 3681 __le16 cmpl_ring; 3682 __le16 seq_id; 3683 __le16 target_id; 3684 __le64 resp_addr; 3685 __le32 enables; 3686 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 3687 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3688 __le32 unused_0; 3689 __le64 ntuple_filter_id; 3690 __le32 new_dst_id; 3691 __le32 new_mirror_vnic_id; 3692}; 3693 3694/* Output (16 bytes) */ 3695struct hwrm_cfa_ntuple_filter_cfg_output { 3696 __le16 error_code; 3697 __le16 req_type; 3698 __le16 seq_id; 3699 __le16 resp_len; 3700 __le32 unused_0; 3701 u8 unused_1; 3702 u8 unused_2; 3703 u8 unused_3; 3704 u8 valid; 3705}; 3706 3707/* hwrm_tunnel_dst_port_query */ 3708/* Input (24 bytes) */ 3709struct hwrm_tunnel_dst_port_query_input { 3710 __le16 req_type; 3711 __le16 cmpl_ring; 3712 __le16 seq_id; 3713 __le16 target_id; 3714 __le64 resp_addr; 3715 u8 tunnel_type; 3716 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3717 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3718 u8 unused_0[7]; 3719}; 3720 3721/* Output (16 bytes) */ 3722struct hwrm_tunnel_dst_port_query_output { 3723 __le16 error_code; 3724 __le16 req_type; 3725 __le16 seq_id; 3726 __le16 resp_len; 3727 __le16 tunnel_dst_port_id; 3728 __be16 tunnel_dst_port_val; 3729 u8 unused_0; 3730 u8 unused_1; 3731 u8 unused_2; 3732 u8 valid; 3733}; 3734 3735/* hwrm_tunnel_dst_port_alloc */ 3736/* Input (24 bytes) */ 3737struct hwrm_tunnel_dst_port_alloc_input { 3738 __le16 req_type; 3739 __le16 cmpl_ring; 3740 __le16 seq_id; 3741 __le16 target_id; 3742 __le64 resp_addr; 3743 u8 tunnel_type; 3744 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3745 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3746 u8 unused_0; 3747 __be16 tunnel_dst_port_val; 3748 __le32 unused_1; 3749}; 3750 3751/* Output (16 bytes) */ 3752struct hwrm_tunnel_dst_port_alloc_output { 3753 __le16 error_code; 3754 __le16 req_type; 3755 __le16 seq_id; 3756 __le16 resp_len; 3757 __le16 tunnel_dst_port_id; 3758 u8 unused_0; 3759 u8 unused_1; 3760 u8 unused_2; 3761 u8 unused_3; 3762 u8 unused_4; 3763 u8 valid; 3764}; 3765 3766/* hwrm_tunnel_dst_port_free */ 3767/* Input (24 bytes) */ 3768struct hwrm_tunnel_dst_port_free_input { 3769 __le16 req_type; 3770 __le16 cmpl_ring; 3771 __le16 seq_id; 3772 __le16 target_id; 3773 __le64 resp_addr; 3774 u8 tunnel_type; 3775 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3776 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3777 u8 unused_0; 3778 __le16 tunnel_dst_port_id; 3779 __le32 unused_1; 3780}; 3781 3782/* Output (16 bytes) */ 3783struct hwrm_tunnel_dst_port_free_output { 3784 __le16 error_code; 3785 __le16 req_type; 3786 __le16 seq_id; 3787 __le16 resp_len; 3788 __le32 unused_0; 3789 u8 unused_1; 3790 u8 unused_2; 3791 u8 unused_3; 3792 u8 valid; 3793}; 3794 3795/* hwrm_stat_ctx_alloc */ 3796/* Input (32 bytes) */ 3797struct hwrm_stat_ctx_alloc_input { 3798 __le16 req_type; 3799 __le16 cmpl_ring; 3800 __le16 seq_id; 3801 __le16 target_id; 3802 __le64 resp_addr; 3803 __le64 stats_dma_addr; 3804 __le32 update_period_ms; 3805 __le32 unused_0; 3806}; 3807 3808/* Output (16 bytes) */ 3809struct hwrm_stat_ctx_alloc_output { 3810 __le16 error_code; 3811 __le16 req_type; 3812 __le16 seq_id; 3813 __le16 resp_len; 3814 __le32 stat_ctx_id; 3815 u8 unused_0; 3816 u8 unused_1; 3817 u8 unused_2; 3818 u8 valid; 3819}; 3820 3821/* hwrm_stat_ctx_free */ 3822/* Input (24 bytes) */ 3823struct hwrm_stat_ctx_free_input { 3824 __le16 req_type; 3825 __le16 cmpl_ring; 3826 __le16 seq_id; 3827 __le16 target_id; 3828 __le64 resp_addr; 3829 __le32 stat_ctx_id; 3830 __le32 unused_0; 3831}; 3832 3833/* Output (16 bytes) */ 3834struct hwrm_stat_ctx_free_output { 3835 __le16 error_code; 3836 __le16 req_type; 3837 __le16 seq_id; 3838 __le16 resp_len; 3839 __le32 stat_ctx_id; 3840 u8 unused_0; 3841 u8 unused_1; 3842 u8 unused_2; 3843 u8 valid; 3844}; 3845 3846/* hwrm_stat_ctx_query */ 3847/* Input (24 bytes) */ 3848struct hwrm_stat_ctx_query_input { 3849 __le16 req_type; 3850 __le16 cmpl_ring; 3851 __le16 seq_id; 3852 __le16 target_id; 3853 __le64 resp_addr; 3854 __le32 stat_ctx_id; 3855 __le32 unused_0; 3856}; 3857 3858/* Output (176 bytes) */ 3859struct hwrm_stat_ctx_query_output { 3860 __le16 error_code; 3861 __le16 req_type; 3862 __le16 seq_id; 3863 __le16 resp_len; 3864 __le64 tx_ucast_pkts; 3865 __le64 tx_mcast_pkts; 3866 __le64 tx_bcast_pkts; 3867 __le64 tx_err_pkts; 3868 __le64 tx_drop_pkts; 3869 __le64 tx_ucast_bytes; 3870 __le64 tx_mcast_bytes; 3871 __le64 tx_bcast_bytes; 3872 __le64 rx_ucast_pkts; 3873 __le64 rx_mcast_pkts; 3874 __le64 rx_bcast_pkts; 3875 __le64 rx_err_pkts; 3876 __le64 rx_drop_pkts; 3877 __le64 rx_ucast_bytes; 3878 __le64 rx_mcast_bytes; 3879 __le64 rx_bcast_bytes; 3880 __le64 rx_agg_pkts; 3881 __le64 rx_agg_bytes; 3882 __le64 rx_agg_events; 3883 __le64 rx_agg_aborts; 3884 __le32 unused_0; 3885 u8 unused_1; 3886 u8 unused_2; 3887 u8 unused_3; 3888 u8 valid; 3889}; 3890 3891/* hwrm_stat_ctx_clr_stats */ 3892/* Input (24 bytes) */ 3893struct hwrm_stat_ctx_clr_stats_input { 3894 __le16 req_type; 3895 __le16 cmpl_ring; 3896 __le16 seq_id; 3897 __le16 target_id; 3898 __le64 resp_addr; 3899 __le32 stat_ctx_id; 3900 __le32 unused_0; 3901}; 3902 3903/* Output (16 bytes) */ 3904struct hwrm_stat_ctx_clr_stats_output { 3905 __le16 error_code; 3906 __le16 req_type; 3907 __le16 seq_id; 3908 __le16 resp_len; 3909 __le32 unused_0; 3910 u8 unused_1; 3911 u8 unused_2; 3912 u8 unused_3; 3913 u8 valid; 3914}; 3915 3916/* hwrm_fw_reset */ 3917/* Input (24 bytes) */ 3918struct hwrm_fw_reset_input { 3919 __le16 req_type; 3920 __le16 cmpl_ring; 3921 __le16 seq_id; 3922 __le16 target_id; 3923 __le64 resp_addr; 3924 u8 embedded_proc_type; 3925 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3926 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3927 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3928 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3929 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3930 u8 selfrst_status; 3931 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 3932 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 3933 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3934 __le16 unused_0[3]; 3935}; 3936 3937/* Output (16 bytes) */ 3938struct hwrm_fw_reset_output { 3939 __le16 error_code; 3940 __le16 req_type; 3941 __le16 seq_id; 3942 __le16 resp_len; 3943 u8 selfrst_status; 3944 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 3945 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 3946 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3947 u8 unused_0; 3948 __le16 unused_1; 3949 u8 unused_2; 3950 u8 unused_3; 3951 u8 unused_4; 3952 u8 valid; 3953}; 3954 3955/* hwrm_fw_qstatus */ 3956/* Input (24 bytes) */ 3957struct hwrm_fw_qstatus_input { 3958 __le16 req_type; 3959 __le16 cmpl_ring; 3960 __le16 seq_id; 3961 __le16 target_id; 3962 __le64 resp_addr; 3963 u8 embedded_proc_type; 3964 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3965 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3966 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3967 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3968 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3969 u8 unused_0[7]; 3970}; 3971 3972/* Output (16 bytes) */ 3973struct hwrm_fw_qstatus_output { 3974 __le16 error_code; 3975 __le16 req_type; 3976 __le16 seq_id; 3977 __le16 resp_len; 3978 u8 selfrst_status; 3979 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 3980 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 3981 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3982 u8 unused_0; 3983 __le16 unused_1; 3984 u8 unused_2; 3985 u8 unused_3; 3986 u8 unused_4; 3987 u8 valid; 3988}; 3989 3990/* hwrm_fw_set_time */ 3991/* Input (32 bytes) */ 3992struct hwrm_fw_set_time_input { 3993 __le16 req_type; 3994 __le16 cmpl_ring; 3995 __le16 seq_id; 3996 __le16 target_id; 3997 __le64 resp_addr; 3998 __le16 year; 3999 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4000 u8 month;
4001 u8 day; 4002 u8 hour; 4003 u8 minute; 4004 u8 second; 4005 u8 unused_0; 4006 __le16 millisecond; 4007 __le16 zone; 4008 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4009 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4010 __le32 unused_1; 4011}; 4012 4013/* Output (16 bytes) */ 4014struct hwrm_fw_set_time_output { 4015 __le16 error_code; 4016 __le16 req_type; 4017 __le16 seq_id; 4018 __le16 resp_len; 4019 __le32 unused_0; 4020 u8 unused_1; 4021 u8 unused_2; 4022 u8 unused_3; 4023 u8 valid; 4024}; 4025 4026/* hwrm_exec_fwd_resp */ 4027/* Input (128 bytes) */ 4028struct hwrm_exec_fwd_resp_input { 4029 __le16 req_type; 4030 __le16 cmpl_ring; 4031 __le16 seq_id; 4032 __le16 target_id; 4033 __le64 resp_addr; 4034 __le32 encap_request[26]; 4035 __le16 encap_resp_target_id; 4036 __le16 unused_0[3]; 4037}; 4038 4039/* Output (16 bytes) */ 4040struct hwrm_exec_fwd_resp_output { 4041 __le16 error_code; 4042 __le16 req_type; 4043 __le16 seq_id; 4044 __le16 resp_len; 4045 __le32 unused_0; 4046 u8 unused_1; 4047 u8 unused_2; 4048 u8 unused_3; 4049 u8 valid; 4050}; 4051 4052/* hwrm_reject_fwd_resp */ 4053/* Input (128 bytes) */ 4054struct hwrm_reject_fwd_resp_input { 4055 __le16 req_type; 4056 __le16 cmpl_ring; 4057 __le16 seq_id; 4058 __le16 target_id; 4059 __le64 resp_addr; 4060 __le32 encap_request[26]; 4061 __le16 encap_resp_target_id; 4062 __le16 unused_0[3]; 4063}; 4064 4065/* Output (16 bytes) */ 4066struct hwrm_reject_fwd_resp_output { 4067 __le16 error_code; 4068 __le16 req_type; 4069 __le16 seq_id; 4070 __le16 resp_len; 4071 __le32 unused_0; 4072 u8 unused_1; 4073 u8 unused_2; 4074 u8 unused_3; 4075 u8 valid; 4076}; 4077 4078/* hwrm_fwd_resp */ 4079/* Input (40 bytes) */ 4080struct hwrm_fwd_resp_input { 4081 __le16 req_type; 4082 __le16 cmpl_ring; 4083 __le16 seq_id; 4084 __le16 target_id; 4085 __le64 resp_addr; 4086 __le16 encap_resp_target_id; 4087 __le16 encap_resp_cmpl_ring; 4088 __le16 encap_resp_len; 4089 u8 unused_0; 4090 u8 unused_1; 4091 __le64 encap_resp_addr; 4092 __le32 encap_resp[24]; 4093}; 4094 4095/* Output (16 bytes) */ 4096struct hwrm_fwd_resp_output { 4097 __le16 error_code; 4098 __le16 req_type; 4099 __le16 seq_id; 4100 __le16 resp_len; 4101 __le32 unused_0; 4102 u8 unused_1; 4103 u8 unused_2; 4104 u8 unused_3; 4105 u8 valid; 4106}; 4107 4108/* hwrm_fwd_async_event_cmpl */ 4109/* Input (32 bytes) */ 4110struct hwrm_fwd_async_event_cmpl_input { 4111 __le16 req_type; 4112 __le16 cmpl_ring; 4113 __le16 seq_id; 4114 __le16 target_id; 4115 __le64 resp_addr; 4116 __le16 encap_async_event_target_id; 4117 u8 unused_0; 4118 u8 unused_1; 4119 u8 unused_2[3]; 4120 u8 unused_3; 4121 __le32 encap_async_event_cmpl[4]; 4122}; 4123 4124/* Output (16 bytes) */ 4125struct hwrm_fwd_async_event_cmpl_output { 4126 __le16 error_code; 4127 __le16 req_type; 4128 __le16 seq_id; 4129 __le16 resp_len; 4130 __le32 unused_0; 4131 u8 unused_1; 4132 u8 unused_2; 4133 u8 unused_3; 4134 u8 valid; 4135}; 4136 4137/* hwrm_temp_monitor_query */ 4138/* Input (16 bytes) */ 4139struct hwrm_temp_monitor_query_input { 4140 __le16 req_type; 4141 __le16 cmpl_ring; 4142 __le16 seq_id; 4143 __le16 target_id; 4144 __le64 resp_addr; 4145}; 4146 4147/* Output (16 bytes) */ 4148struct hwrm_temp_monitor_query_output { 4149 __le16 error_code; 4150 __le16 req_type; 4151 __le16 seq_id; 4152 __le16 resp_len; 4153 u8 temp; 4154 u8 unused_0; 4155 __le16 unused_1; 4156 u8 unused_2; 4157 u8 unused_3; 4158 u8 unused_4; 4159 u8 valid; 4160}; 4161 4162/* hwrm_nvm_read */ 4163/* Input (40 bytes) */ 4164struct hwrm_nvm_read_input { 4165 __le16 req_type; 4166 __le16 cmpl_ring; 4167 __le16 seq_id; 4168 __le16 target_id; 4169 __le64 resp_addr; 4170 __le64 host_dest_addr; 4171 __le16 dir_idx; 4172 u8 unused_0; 4173 u8 unused_1; 4174 __le32 offset; 4175 __le32 len; 4176 __le32 unused_2; 4177}; 4178 4179/* Output (16 bytes) */ 4180struct hwrm_nvm_read_output { 4181 __le16 error_code; 4182 __le16 req_type; 4183 __le16 seq_id; 4184 __le16 resp_len; 4185 __le32 unused_0; 4186 u8 unused_1; 4187 u8 unused_2; 4188 u8 unused_3; 4189 u8 valid; 4190}; 4191 4192/* hwrm_nvm_raw_dump */ 4193/* Input (32 bytes) */ 4194struct hwrm_nvm_raw_dump_input { 4195 __le16 req_type; 4196 __le16 cmpl_ring; 4197 __le16 seq_id; 4198 __le16 target_id; 4199 __le64 resp_addr; 4200 __le64 host_dest_addr; 4201 __le32 offset; 4202 __le32 len; 4203}; 4204 4205/* Output (16 bytes) */ 4206struct hwrm_nvm_raw_dump_output { 4207 __le16 error_code; 4208 __le16 req_type; 4209 __le16 seq_id; 4210 __le16 resp_len; 4211 __le32 unused_0; 4212 u8 unused_1; 4213 u8 unused_2; 4214 u8 unused_3; 4215 u8 valid; 4216}; 4217 4218/* hwrm_nvm_get_dir_entries */ 4219/* Input (24 bytes) */ 4220struct hwrm_nvm_get_dir_entries_input { 4221 __le16 req_type; 4222 __le16 cmpl_ring; 4223 __le16 seq_id; 4224 __le16 target_id; 4225 __le64 resp_addr; 4226 __le64 host_dest_addr; 4227}; 4228 4229/* Output (16 bytes) */ 4230struct hwrm_nvm_get_dir_entries_output { 4231 __le16 error_code; 4232 __le16 req_type; 4233 __le16 seq_id; 4234 __le16 resp_len; 4235 __le32 unused_0; 4236 u8 unused_1; 4237 u8 unused_2; 4238 u8 unused_3; 4239 u8 valid; 4240}; 4241 4242/* hwrm_nvm_get_dir_info */ 4243/* Input (16 bytes) */ 4244struct hwrm_nvm_get_dir_info_input { 4245 __le16 req_type; 4246 __le16 cmpl_ring; 4247 __le16 seq_id; 4248 __le16 target_id; 4249 __le64 resp_addr; 4250}; 4251 4252/* Output (24 bytes) */ 4253struct hwrm_nvm_get_dir_info_output { 4254 __le16 error_code; 4255 __le16 req_type; 4256 __le16 seq_id; 4257 __le16 resp_len; 4258 __le32 entries; 4259 __le32 entry_length; 4260 __le32 unused_0; 4261 u8 unused_1; 4262 u8 unused_2; 4263 u8 unused_3; 4264 u8 valid; 4265}; 4266 4267/* hwrm_nvm_write */ 4268/* Input (48 bytes) */ 4269struct hwrm_nvm_write_input { 4270 __le16 req_type; 4271 __le16 cmpl_ring; 4272 __le16 seq_id; 4273 __le16 target_id; 4274 __le64 resp_addr; 4275 __le64 host_src_addr; 4276 __le16 dir_type; 4277 __le16 dir_ordinal; 4278 __le16 dir_ext; 4279 __le16 dir_attr; 4280 __le32 dir_data_length; 4281 __le16 option; 4282 __le16 flags; 4283 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4284 __le32 dir_item_length; 4285 __le32 unused_0; 4286}; 4287 4288/* Output (16 bytes) */ 4289struct hwrm_nvm_write_output { 4290 __le16 error_code; 4291 __le16 req_type; 4292 __le16 seq_id; 4293 __le16 resp_len; 4294 __le32 dir_item_length; 4295 __le16 dir_idx; 4296 u8 unused_0; 4297 u8 valid; 4298}; 4299 4300/* hwrm_nvm_modify */ 4301/* Input (40 bytes) */ 4302struct hwrm_nvm_modify_input { 4303 __le16 req_type; 4304 __le16 cmpl_ring; 4305 __le16 seq_id; 4306 __le16 target_id; 4307 __le64 resp_addr; 4308 __le64 host_src_addr; 4309 __le16 dir_idx; 4310 u8 unused_0; 4311 u8 unused_1; 4312 __le32 offset; 4313 __le32 len; 4314 __le32 unused_2; 4315}; 4316 4317/* Output (16 bytes) */ 4318struct hwrm_nvm_modify_output { 4319 __le16 error_code; 4320 __le16 req_type; 4321 __le16 seq_id; 4322 __le16 resp_len; 4323 __le32 unused_0; 4324 u8 unused_1; 4325 u8 unused_2; 4326 u8 unused_3; 4327 u8 valid; 4328}; 4329 4330/* hwrm_nvm_find_dir_entry */ 4331/* Input (32 bytes) */ 4332struct hwrm_nvm_find_dir_entry_input { 4333 __le16 req_type; 4334 __le16 cmpl_ring; 4335 __le16 seq_id; 4336 __le16 target_id; 4337 __le64 resp_addr; 4338 __le32 enables; 4339 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4340 __le16 dir_idx; 4341 __le16 dir_type; 4342 __le16 dir_ordinal; 4343 __le16 dir_ext; 4344 u8 opt_ordinal; 4345 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4346 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4347 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 4348 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 4349 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 4350 u8 unused_1[3]; 4351}; 4352 4353/* Output (32 bytes) */ 4354struct hwrm_nvm_find_dir_entry_output { 4355 __le16 error_code; 4356 __le16 req_type; 4357 __le16 seq_id; 4358 __le16 resp_len; 4359 __le32 dir_item_length; 4360 __le32 dir_data_length; 4361 __le32 fw_ver; 4362 __le16 dir_ordinal; 4363 __le16 dir_idx; 4364 __le32 unused_0; 4365 u8 unused_1; 4366 u8 unused_2; 4367 u8 unused_3; 4368 u8 valid; 4369}; 4370 4371/* hwrm_nvm_erase_dir_entry */ 4372/* Input (24 bytes) */ 4373struct hwrm_nvm_erase_dir_entry_input { 4374 __le16 req_type; 4375 __le16 cmpl_ring; 4376 __le16 seq_id; 4377 __le16 target_id; 4378 __le64 resp_addr; 4379 __le16 dir_idx; 4380 __le16 unused_0[3]; 4381}; 4382 4383/* Output (16 bytes) */ 4384struct hwrm_nvm_erase_dir_entry_output { 4385 __le16 error_code; 4386 __le16 req_type; 4387 __le16 seq_id; 4388 __le16 resp_len; 4389 __le32 unused_0; 4390 u8 unused_1; 4391 u8 unused_2; 4392 u8 unused_3; 4393 u8 valid; 4394}; 4395 4396/* hwrm_nvm_get_dev_info */ 4397/* Input (16 bytes) */ 4398struct hwrm_nvm_get_dev_info_input { 4399 __le16 req_type; 4400 __le16 cmpl_ring; 4401 __le16 seq_id; 4402 __le16 target_id; 4403 __le64 resp_addr; 4404}; 4405 4406/* Output (32 bytes) */ 4407struct hwrm_nvm_get_dev_info_output { 4408 __le16 error_code; 4409 __le16 req_type; 4410 __le16 seq_id; 4411 __le16 resp_len; 4412 __le16 manufacturer_id; 4413 __le16 device_id; 4414 __le32 sector_size; 4415 __le32 nvram_size; 4416 __le32 reserved_size; 4417 __le32 available_size; 4418 u8 unused_0; 4419 u8 unused_1; 4420 u8 unused_2; 4421 u8 valid; 4422}; 4423 4424/* hwrm_nvm_mod_dir_entry */ 4425/* Input (32 bytes) */ 4426struct hwrm_nvm_mod_dir_entry_input { 4427 __le16 req_type; 4428 __le16 cmpl_ring; 4429 __le16 seq_id; 4430 __le16 target_id; 4431 __le64 resp_addr; 4432 __le32 enables; 4433 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 4434 __le16 dir_idx; 4435 __le16 dir_ordinal; 4436 __le16 dir_ext; 4437 __le16 dir_attr; 4438 __le32 checksum; 4439}; 4440 4441/* Output (16 bytes) */ 4442struct hwrm_nvm_mod_dir_entry_output { 4443 __le16 error_code; 4444 __le16 req_type; 4445 __le16 seq_id; 4446 __le16 resp_len; 4447 __le32 unused_0; 4448 u8 unused_1; 4449 u8 unused_2; 4450 u8 unused_3; 4451 u8 valid; 4452}; 4453 4454/* hwrm_nvm_verify_update */ 4455/* Input (24 bytes) */ 4456struct hwrm_nvm_verify_update_input { 4457 __le16 req_type; 4458 __le16 cmpl_ring; 4459 __le16 seq_id; 4460 __le16 target_id; 4461 __le64 resp_addr; 4462 __le16 dir_type; 4463 __le16 dir_ordinal; 4464 __le16 dir_ext; 4465 __le16 unused_0; 4466}; 4467 4468/* Output (16 bytes) */ 4469struct hwrm_nvm_verify_update_output { 4470 __le16 error_code; 4471 __le16 req_type; 4472 __le16 seq_id; 4473 __le16 resp_len; 4474 __le32 unused_0; 4475 u8 unused_1; 4476 u8 unused_2; 4477 u8 unused_3; 4478 u8 valid; 4479}; 4480 4481/* hwrm_nvm_install_update */ 4482/* Input (24 bytes) */ 4483struct hwrm_nvm_install_update_input { 4484 __le16 req_type; 4485 __le16 cmpl_ring; 4486 __le16 seq_id; 4487 __le16 target_id; 4488 __le64 resp_addr; 4489 __le32 install_type; 4490 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 4491 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 4492 __le32 unused_0; 4493}; 4494 4495/* Output (24 bytes) */ 4496struct hwrm_nvm_install_update_output { 4497 __le16 error_code; 4498 __le16 req_type; 4499 __le16 seq_id; 4500 __le16 resp_len; 4501 __le64 installed_items; 4502 u8 result; 4503 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 4504 u8 problem_item; 4505 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 4506 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 4507 u8 reset_required; 4508 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 4509 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 4510 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 4511 u8 unused_0; 4512 u8 unused_1; 4513 u8 unused_2; 4514 u8 unused_3; 4515 u8 valid; 4516}; 4517 4518#endif 4519