1/******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#ifndef _DCB_82598_CONFIG_H_ 30#define _DCB_82598_CONFIG_H_ 31 32/* DCB register definitions */ 33 34#define IXGBE_DPMCS_MTSOS_SHIFT 16 35#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */ 36#define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */ 37#define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 38#define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */ 39 40#define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */ 41 42#define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */ 43#define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */ 44 45#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */ 46#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */ 47 48#define IXGBE_TDTQ2TCCR_MCL_SHIFT 12 49#define IXGBE_TDTQ2TCCR_BWG_SHIFT 9 50#define IXGBE_TDTQ2TCCR_GSP 0x40000000 51#define IXGBE_TDTQ2TCCR_LSP 0x80000000 52 53#define IXGBE_TDPT2TCCR_MCL_SHIFT 12 54#define IXGBE_TDPT2TCCR_BWG_SHIFT 9 55#define IXGBE_TDPT2TCCR_GSP 0x40000000 56#define IXGBE_TDPT2TCCR_LSP 0x80000000 57 58#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */ 59#define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */ 60#define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */ 61 62#define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */ 63 64#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 65#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 66#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 67#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 68 69#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 70 71/* DCB hardware-specific driver APIs */ 72 73/* DCB PFC functions */ 74s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en); 75 76/* DCB hw initialization */ 77s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, 78 u16 *refill, 79 u16 *max, 80 u8 *prio_type); 81 82s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, 83 u16 *refill, 84 u16 *max, 85 u8 *bwg_id, 86 u8 *prio_type); 87 88s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, 89 u16 *refill, 90 u16 *max, 91 u8 *bwg_id, 92 u8 *prio_type); 93 94s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill, 95 u16 *max, u8 *bwg_id, u8 *prio_type); 96 97#endif /* _DCB_82598_CONFIG_H */ 98