1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16#include <linux/platform_device.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/serial_sci.h>
20#include <linux/io.h>
21#include <linux/mm.h>
22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h>
24#include <linux/sh_dma.h>
25#include <linux/sh_intc.h>
26#include <linux/usb/ohci_pdriver.h>
27#include <cpu/dma-register.h>
28#include <asm/mmzone.h>
29
30static struct plat_sci_port scif0_platform_data = {
31 .scscr = SCSCR_REIE | SCSCR_CKE1,
32 .type = PORT_SCIF,
33 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
34};
35
36static struct resource scif0_resources[] = {
37 DEFINE_RES_MEM(0xffea0000, 0x100),
38 DEFINE_RES_IRQ(evt2irq(0x700)),
39 DEFINE_RES_IRQ(evt2irq(0x720)),
40 DEFINE_RES_IRQ(evt2irq(0x760)),
41 DEFINE_RES_IRQ(evt2irq(0x740)),
42};
43
44static struct platform_device scif0_device = {
45 .name = "sh-sci",
46 .id = 0,
47 .resource = scif0_resources,
48 .num_resources = ARRAY_SIZE(scif0_resources),
49 .dev = {
50 .platform_data = &scif0_platform_data,
51 },
52};
53
54
55
56
57static struct plat_sci_port scif1_platform_data = {
58 .scscr = SCSCR_REIE | SCSCR_CKE1,
59 .type = PORT_SCIF,
60 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
61};
62
63static struct resource scif1_resources[] = {
64 DEFINE_RES_MEM(0xffeb0000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0x780)),
66};
67
68static struct resource scif1_demux_resources[] = {
69 DEFINE_RES_MEM(0xffeb0000, 0x100),
70
71 DEFINE_RES_IRQ(0),
72 DEFINE_RES_IRQ(0),
73 DEFINE_RES_IRQ(0),
74 DEFINE_RES_IRQ(0),
75};
76
77static struct platform_device scif1_device = {
78 .name = "sh-sci",
79 .id = 1,
80 .resource = scif1_resources,
81 .num_resources = ARRAY_SIZE(scif1_resources),
82 .dev = {
83 .platform_data = &scif1_platform_data,
84 },
85};
86
87static struct plat_sci_port scif2_platform_data = {
88 .scscr = SCSCR_REIE | SCSCR_CKE1,
89 .type = PORT_SCIF,
90 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
91};
92
93static struct resource scif2_resources[] = {
94 DEFINE_RES_MEM(0xffec0000, 0x100),
95 DEFINE_RES_IRQ(evt2irq(0x840)),
96};
97
98static struct platform_device scif2_device = {
99 .name = "sh-sci",
100 .id = 2,
101 .resource = scif2_resources,
102 .num_resources = ARRAY_SIZE(scif2_resources),
103 .dev = {
104 .platform_data = &scif2_platform_data,
105 },
106};
107
108static struct plat_sci_port scif3_platform_data = {
109 .scscr = SCSCR_REIE | SCSCR_CKE1,
110 .type = PORT_SCIF,
111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
112};
113
114static struct resource scif3_resources[] = {
115 DEFINE_RES_MEM(0xffed0000, 0x100),
116 DEFINE_RES_IRQ(evt2irq(0x860)),
117};
118
119static struct platform_device scif3_device = {
120 .name = "sh-sci",
121 .id = 3,
122 .resource = scif3_resources,
123 .num_resources = ARRAY_SIZE(scif3_resources),
124 .dev = {
125 .platform_data = &scif3_platform_data,
126 },
127};
128
129static struct plat_sci_port scif4_platform_data = {
130 .scscr = SCSCR_REIE | SCSCR_CKE1,
131 .type = PORT_SCIF,
132 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
133};
134
135static struct resource scif4_resources[] = {
136 DEFINE_RES_MEM(0xffee0000, 0x100),
137 DEFINE_RES_IRQ(evt2irq(0x880)),
138};
139
140static struct platform_device scif4_device = {
141 .name = "sh-sci",
142 .id = 4,
143 .resource = scif4_resources,
144 .num_resources = ARRAY_SIZE(scif4_resources),
145 .dev = {
146 .platform_data = &scif4_platform_data,
147 },
148};
149
150static struct plat_sci_port scif5_platform_data = {
151 .scscr = SCSCR_REIE | SCSCR_CKE1,
152 .type = PORT_SCIF,
153 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
154};
155
156static struct resource scif5_resources[] = {
157 DEFINE_RES_MEM(0xffef0000, 0x100),
158 DEFINE_RES_IRQ(evt2irq(0x8a0)),
159};
160
161static struct platform_device scif5_device = {
162 .name = "sh-sci",
163 .id = 5,
164 .resource = scif5_resources,
165 .num_resources = ARRAY_SIZE(scif5_resources),
166 .dev = {
167 .platform_data = &scif5_platform_data,
168 },
169};
170
171static struct sh_timer_config tmu0_platform_data = {
172 .channels_mask = 7,
173};
174
175static struct resource tmu0_resources[] = {
176 DEFINE_RES_MEM(0xffd80000, 0x30),
177 DEFINE_RES_IRQ(evt2irq(0x400)),
178 DEFINE_RES_IRQ(evt2irq(0x420)),
179 DEFINE_RES_IRQ(evt2irq(0x440)),
180};
181
182static struct platform_device tmu0_device = {
183 .name = "sh-tmu",
184 .id = 0,
185 .dev = {
186 .platform_data = &tmu0_platform_data,
187 },
188 .resource = tmu0_resources,
189 .num_resources = ARRAY_SIZE(tmu0_resources),
190};
191
192static struct sh_timer_config tmu1_platform_data = {
193 .channels_mask = 7,
194};
195
196static struct resource tmu1_resources[] = {
197 DEFINE_RES_MEM(0xffda0000, 0x2c),
198 DEFINE_RES_IRQ(evt2irq(0x480)),
199 DEFINE_RES_IRQ(evt2irq(0x4a0)),
200 DEFINE_RES_IRQ(evt2irq(0x4c0)),
201};
202
203static struct platform_device tmu1_device = {
204 .name = "sh-tmu",
205 .id = 1,
206 .dev = {
207 .platform_data = &tmu1_platform_data,
208 },
209 .resource = tmu1_resources,
210 .num_resources = ARRAY_SIZE(tmu1_resources),
211};
212
213static struct sh_timer_config tmu2_platform_data = {
214 .channels_mask = 7,
215};
216
217static struct resource tmu2_resources[] = {
218 DEFINE_RES_MEM(0xffdc0000, 0x2c),
219 DEFINE_RES_IRQ(evt2irq(0x7a0)),
220 DEFINE_RES_IRQ(evt2irq(0x7a0)),
221 DEFINE_RES_IRQ(evt2irq(0x7a0)),
222};
223
224static struct platform_device tmu2_device = {
225 .name = "sh-tmu",
226 .id = 2,
227 .dev = {
228 .platform_data = &tmu2_platform_data,
229 },
230 .resource = tmu2_resources,
231 .num_resources = ARRAY_SIZE(tmu2_resources),
232};
233
234static struct sh_timer_config tmu3_platform_data = {
235 .channels_mask = 7,
236};
237
238static struct resource tmu3_resources[] = {
239 DEFINE_RES_MEM(0xffde0000, 0x2c),
240 DEFINE_RES_IRQ(evt2irq(0x7c0)),
241 DEFINE_RES_IRQ(evt2irq(0x7c0)),
242 DEFINE_RES_IRQ(evt2irq(0x7c0)),
243};
244
245static struct platform_device tmu3_device = {
246 .name = "sh-tmu",
247 .id = 3,
248 .dev = {
249 .platform_data = &tmu3_platform_data,
250 },
251 .resource = tmu3_resources,
252 .num_resources = ARRAY_SIZE(tmu3_resources),
253};
254
255static const struct sh_dmae_channel dmac0_channels[] = {
256 {
257 .offset = 0,
258 .dmars = 0,
259 .dmars_bit = 0,
260 }, {
261 .offset = 0x10,
262 .dmars = 0,
263 .dmars_bit = 8,
264 }, {
265 .offset = 0x20,
266 .dmars = 4,
267 .dmars_bit = 0,
268 }, {
269 .offset = 0x30,
270 .dmars = 4,
271 .dmars_bit = 8,
272 }, {
273 .offset = 0x50,
274 .dmars = 8,
275 .dmars_bit = 0,
276 }, {
277 .offset = 0x60,
278 .dmars = 8,
279 .dmars_bit = 8,
280 }
281};
282
283static const unsigned int ts_shift[] = TS_SHIFT;
284
285static struct sh_dmae_pdata dma0_platform_data = {
286 .channel = dmac0_channels,
287 .channel_num = ARRAY_SIZE(dmac0_channels),
288 .ts_low_shift = CHCR_TS_LOW_SHIFT,
289 .ts_low_mask = CHCR_TS_LOW_MASK,
290 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
291 .ts_high_mask = CHCR_TS_HIGH_MASK,
292 .ts_shift = ts_shift,
293 .ts_shift_num = ARRAY_SIZE(ts_shift),
294 .dmaor_init = DMAOR_INIT,
295};
296
297
298static struct resource dmac0_resources[] = {
299 {
300
301 .start = 0xfe008020,
302 .end = 0xfe00808f,
303 .flags = IORESOURCE_MEM,
304 }, {
305
306 .start = 0xfe009000,
307 .end = 0xfe00900b,
308 .flags = IORESOURCE_MEM,
309 }, {
310 .name = "error_irq",
311 .start = evt2irq(0x5c0),
312 .end = evt2irq(0x5c0),
313 .flags = IORESOURCE_IRQ,
314 }, {
315
316 .start = evt2irq(0x500),
317 .end = evt2irq(0x5a0),
318 .flags = IORESOURCE_IRQ,
319 },
320};
321
322static struct platform_device dma0_device = {
323 .name = "sh-dma-engine",
324 .id = 0,
325 .resource = dmac0_resources,
326 .num_resources = ARRAY_SIZE(dmac0_resources),
327 .dev = {
328 .platform_data = &dma0_platform_data,
329 },
330};
331
332#define USB_EHCI_START 0xffe70000
333#define USB_OHCI_START 0xffe70400
334
335static struct resource usb_ehci_resources[] = {
336 [0] = {
337 .start = USB_EHCI_START,
338 .end = USB_EHCI_START + 0x3ff,
339 .flags = IORESOURCE_MEM,
340 },
341 [1] = {
342 .start = evt2irq(0xba0),
343 .end = evt2irq(0xba0),
344 .flags = IORESOURCE_IRQ,
345 },
346};
347
348static struct platform_device usb_ehci_device = {
349 .name = "sh_ehci",
350 .id = -1,
351 .dev = {
352 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
353 .coherent_dma_mask = DMA_BIT_MASK(32),
354 },
355 .num_resources = ARRAY_SIZE(usb_ehci_resources),
356 .resource = usb_ehci_resources,
357};
358
359static struct resource usb_ohci_resources[] = {
360 [0] = {
361 .start = USB_OHCI_START,
362 .end = USB_OHCI_START + 0x3ff,
363 .flags = IORESOURCE_MEM,
364 },
365 [1] = {
366 .start = evt2irq(0xba0),
367 .end = evt2irq(0xba0),
368 .flags = IORESOURCE_IRQ,
369 },
370};
371
372static struct usb_ohci_pdata usb_ohci_pdata;
373
374static struct platform_device usb_ohci_device = {
375 .name = "ohci-platform",
376 .id = -1,
377 .dev = {
378 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
379 .coherent_dma_mask = DMA_BIT_MASK(32),
380 .platform_data = &usb_ohci_pdata,
381 },
382 .num_resources = ARRAY_SIZE(usb_ohci_resources),
383 .resource = usb_ohci_resources,
384};
385
386static struct platform_device *sh7786_early_devices[] __initdata = {
387 &scif0_device,
388 &scif1_device,
389 &scif2_device,
390 &scif3_device,
391 &scif4_device,
392 &scif5_device,
393 &tmu0_device,
394 &tmu1_device,
395 &tmu2_device,
396};
397
398static struct platform_device *sh7786_devices[] __initdata = {
399 &dma0_device,
400 &usb_ehci_device,
401 &usb_ohci_device,
402};
403
404
405
406
407
408#define USBCTL0 0xffe70858
409#define CLOCK_MODE_MASK 0xffffff7f
410#define EXT_CLOCK_MODE 0x00000080
411
412void __init sh7786_usb_use_exclock(void)
413{
414 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
415 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
416}
417
418#define USBINITREG1 0xffe70094
419#define USBINITREG2 0xffe7009c
420#define USBINITVAL1 0x00ff0040
421#define USBINITVAL2 0x00000001
422
423#define USBPCTL1 0xffe70804
424#define USBST 0xffe70808
425#define PHY_ENB 0x00000001
426#define PLL_ENB 0x00000002
427#define PHY_RST 0x00000004
428#define ACT_PLL_STATUS 0xc0000000
429
430static void __init sh7786_usb_setup(void)
431{
432 int i = 1000000;
433
434
435
436
437
438
439
440
441
442 __raw_writel(USBINITVAL1, USBINITREG1);
443 __raw_writel(USBINITVAL2, USBINITREG2);
444
445
446
447
448 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
449 while (i--) {
450 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
451
452 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
453 printk(KERN_INFO "sh7786 usb setup done\n");
454 break;
455 }
456 cpu_relax();
457 }
458}
459
460enum {
461 UNUSED = 0,
462
463
464 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
465 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
466 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
467 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
468
469 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
470 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
471 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
472 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
473
474 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
475 WDT,
476 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
477 TMU1_0, TMU1_1, TMU1_2,
478 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
479 HUDI1, HUDI0,
480 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
481 HPB_0, HPB_1, HPB_2,
482 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
483 SCIF1,
484 TMU2, TMU3,
485 SCIF2, SCIF3, SCIF4, SCIF5,
486 Eth_0, Eth_1,
487 PCIeC0_0, PCIeC0_1, PCIeC0_2,
488 PCIeC1_0, PCIeC1_1, PCIeC1_2,
489 USB,
490 I2C0, I2C1,
491 DU,
492 SSI0, SSI1, SSI2, SSI3,
493 PCIeC2_0, PCIeC2_1, PCIeC2_2,
494 HAC0, HAC1,
495 FLCTL,
496 HSPI,
497 GPIO0, GPIO1,
498 Thermal,
499 INTICI0, INTICI1, INTICI2, INTICI3,
500 INTICI4, INTICI5, INTICI6, INTICI7,
501
502
503 TXI1, BRI1, RXI1, ERI1,
504};
505
506static struct intc_vect sh7786_vectors[] __initdata = {
507 INTC_VECT(WDT, 0x3e0),
508 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
509 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
510 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
511 INTC_VECT(TMU1_2, 0x4c0),
512 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
513 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
514 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
515 INTC_VECT(DMAC0_6, 0x5c0),
516 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
517 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
518 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
519 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
520 INTC_VECT(HPB_2, 0x6e0),
521 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
522 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
523 INTC_VECT(SCIF1, 0x780),
524 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
525 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
526 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
527 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
528 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
529 INTC_VECT(PCIeC0_2, 0xb20),
530 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
531 INTC_VECT(PCIeC1_2, 0xb80),
532 INTC_VECT(USB, 0xba0),
533 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
534 INTC_VECT(DU, 0xd00),
535 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
536 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
537 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
538 INTC_VECT(PCIeC2_2, 0xde0),
539 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
540 INTC_VECT(FLCTL, 0xe40),
541 INTC_VECT(HSPI, 0xe80),
542 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
543 INTC_VECT(Thermal, 0xee0),
544 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
545 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
546 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
547 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
548};
549
550#define CnINTMSK0 0xfe410030
551#define CnINTMSK1 0xfe410040
552#define CnINTMSKCLR0 0xfe410050
553#define CnINTMSKCLR1 0xfe410060
554#define CnINT2MSKR0 0xfe410a20
555#define CnINT2MSKR1 0xfe410a24
556#define CnINT2MSKR2 0xfe410a28
557#define CnINT2MSKR3 0xfe410a2c
558#define CnINT2MSKCR0 0xfe410a30
559#define CnINT2MSKCR1 0xfe410a34
560#define CnINT2MSKCR2 0xfe410a38
561#define CnINT2MSKCR3 0xfe410a3c
562#define INTMSK2 0xfe410068
563#define INTMSKCLR2 0xfe41006c
564
565#define INTDISTCR0 0xfe4100b0
566#define INTDISTCR1 0xfe4100b4
567#define INT2DISTCR0 0xfe410900
568#define INT2DISTCR1 0xfe410904
569#define INT2DISTCR2 0xfe410908
570#define INT2DISTCR3 0xfe41090c
571
572static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
573 { CnINTMSK0, CnINTMSKCLR0, 32,
574 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
575 INTC_SMP_BALANCING(INTDISTCR0) },
576 { INTMSK2, INTMSKCLR2, 32,
577 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
578 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
579 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
580 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
581 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
582 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
583 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
584 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
585 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
586 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
588 INTC_SMP_BALANCING(INT2DISTCR0) },
589 { CnINT2MSKR1, CnINT2MSKCR1, 32,
590 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
591 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
592 HUDI1, HUDI0,
593 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
594 HPB_0, HPB_1, HPB_2,
595 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
596 SCIF1,
597 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
598 { CnINT2MSKR2, CnINT2MSKCR2, 32,
599 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
600 Eth_0, Eth_1,
601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
602 PCIeC0_0, PCIeC0_1, PCIeC0_2,
603 PCIeC1_0, PCIeC1_1, PCIeC1_2,
604 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
605 { CnINT2MSKR3, CnINT2MSKCR3, 32,
606 { 0, 0, 0, 0, 0, 0,
607 I2C0, I2C1,
608 DU, SSI0, SSI1, SSI2, SSI3,
609 PCIeC2_0, PCIeC2_1, PCIeC2_2,
610 HAC0, HAC1,
611 FLCTL, 0,
612 HSPI, GPIO0, GPIO1, Thermal,
613 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
614};
615
616static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
617 { 0xfe410010, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
618 IRQ4, IRQ5, IRQ6, IRQ7 } },
619 { 0xfe410800, 0, 32, 8, { 0, 0, 0, WDT } },
620 { 0xfe410804, 0, 32, 8, { TMU0_0, TMU0_1,
621 TMU0_2, TMU0_3 } },
622 { 0xfe410808, 0, 32, 8, { TMU1_0, TMU1_1,
623 TMU1_2, 0 } },
624 { 0xfe41080c, 0, 32, 8, { DMAC0_0, DMAC0_1,
625 DMAC0_2, DMAC0_3 } },
626 { 0xfe410810, 0, 32, 8, { DMAC0_4, DMAC0_5,
627 DMAC0_6, HUDI1 } },
628 { 0xfe410814, 0, 32, 8, { HUDI0, DMAC1_0,
629 DMAC1_1, DMAC1_2 } },
630 { 0xfe410818, 0, 32, 8, { DMAC1_3, HPB_0,
631 HPB_1, HPB_2 } },
632 { 0xfe41081c, 0, 32, 8, { SCIF0_0, SCIF0_1,
633 SCIF0_2, SCIF0_3 } },
634 { 0xfe410820, 0, 32, 8, { SCIF1, TMU2, TMU3, 0 } },
635 { 0xfe410824, 0, 32, 8, { 0, 0, SCIF2, SCIF3 } },
636 { 0xfe410828, 0, 32, 8, { SCIF4, SCIF5,
637 Eth_0, Eth_1 } },
638 { 0xfe41082c, 0, 32, 8, { 0, 0, 0, 0 } },
639 { 0xfe410830, 0, 32, 8, { 0, 0, 0, 0 } },
640 { 0xfe410834, 0, 32, 8, { 0, 0, 0, 0 } },
641 { 0xfe410838, 0, 32, 8, { 0, 0, 0, PCIeC0_0 } },
642 { 0xfe41083c, 0, 32, 8, { PCIeC0_1, PCIeC0_2,
643 PCIeC1_0, PCIeC1_1 } },
644 { 0xfe410840, 0, 32, 8, { PCIeC1_2, USB, 0, 0 } },
645 { 0xfe410844, 0, 32, 8, { 0, 0, 0, 0 } },
646 { 0xfe410848, 0, 32, 8, { 0, 0, I2C0, I2C1 } },
647 { 0xfe41084c, 0, 32, 8, { DU, SSI0, SSI1, SSI2 } },
648 { 0xfe410850, 0, 32, 8, { SSI3, PCIeC2_0,
649 PCIeC2_1, PCIeC2_2 } },
650 { 0xfe410854, 0, 32, 8, { HAC0, HAC1, FLCTL, 0 } },
651 { 0xfe410858, 0, 32, 8, { HSPI, GPIO0,
652 GPIO1, Thermal } },
653 { 0xfe41085c, 0, 32, 8, { 0, 0, 0, 0 } },
654 { 0xfe410860, 0, 32, 8, { 0, 0, 0, 0 } },
655 { 0xfe410090, 0xfe4100a0, 32, 4,
656 { INTICI7, INTICI6, INTICI5, INTICI4,
657 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
658};
659
660static struct intc_subgroup sh7786_subgroups[] __initdata = {
661 { 0xfe410c20, 32, SCIF1,
662 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
663 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
664};
665
666static struct intc_desc sh7786_intc_desc __initdata = {
667 .name = "sh7786",
668 .hw = {
669 .vectors = sh7786_vectors,
670 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
671 .mask_regs = sh7786_mask_registers,
672 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
673 .subgroups = sh7786_subgroups,
674 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
675 .prio_regs = sh7786_prio_registers,
676 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
677 },
678};
679
680
681static struct intc_vect vectors_irq0123[] __initdata = {
682 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
683 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
684};
685
686static struct intc_vect vectors_irq4567[] __initdata = {
687 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
688 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
689};
690
691static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
692 { 0xfe41001c, 32, 2, { IRQ0, IRQ1, IRQ2, IRQ3,
693 IRQ4, IRQ5, IRQ6, IRQ7 } },
694};
695
696static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
697 { 0xfe410024, 0, 32,
698 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
699};
700
701static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
702 vectors_irq0123, NULL, sh7786_mask_registers,
703 sh7786_prio_registers, sh7786_sense_registers,
704 sh7786_ack_registers);
705
706static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
707 vectors_irq4567, NULL, sh7786_mask_registers,
708 sh7786_prio_registers, sh7786_sense_registers,
709 sh7786_ack_registers);
710
711
712
713static struct intc_vect vectors_irl0123[] __initdata = {
714 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
715 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
716 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
717 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
718 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
719 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
720 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
721 INTC_VECT(IRL0_HHHL, 0x3c0),
722};
723
724static struct intc_vect vectors_irl4567[] __initdata = {
725 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
726 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
727 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
728 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
729 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
730 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
731 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
732 INTC_VECT(IRL4_HHHL, 0xac0),
733};
734
735static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
736 NULL, sh7786_mask_registers, NULL, NULL);
737
738static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
739 NULL, sh7786_mask_registers, NULL, NULL);
740
741#define INTC_ICR0 0xfe410000
742#define INTC_INTMSK0 CnINTMSK0
743#define INTC_INTMSK1 CnINTMSK1
744#define INTC_INTMSK2 INTMSK2
745#define INTC_INTMSKCLR1 CnINTMSKCLR1
746#define INTC_INTMSKCLR2 INTMSKCLR2
747
748void __init plat_irq_setup(void)
749{
750
751 __raw_writel(0xff000000, INTC_INTMSK0);
752
753
754 __raw_writel(0xc0000000, INTC_INTMSK1);
755 __raw_writel(0xfffefffe, INTC_INTMSK2);
756
757
758 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
759
760 register_intc_controller(&sh7786_intc_desc);
761}
762
763void __init plat_irq_setup_pins(int mode)
764{
765 switch (mode) {
766 case IRQ_MODE_IRQ7654:
767
768 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
769 register_intc_controller(&intc_desc_irq4567);
770 break;
771 case IRQ_MODE_IRQ3210:
772
773 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
774 register_intc_controller(&intc_desc_irq0123);
775 break;
776 case IRQ_MODE_IRL7654:
777
778 __raw_writel(0x40000000, INTC_INTMSKCLR1);
779 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
780 break;
781 case IRQ_MODE_IRL3210:
782
783 __raw_writel(0x80000000, INTC_INTMSKCLR1);
784 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
785 break;
786 case IRQ_MODE_IRL7654_MASK:
787
788 __raw_writel(0x40000000, INTC_INTMSKCLR1);
789 register_intc_controller(&intc_desc_irl4567);
790 break;
791 case IRQ_MODE_IRL3210_MASK:
792
793 __raw_writel(0x80000000, INTC_INTMSKCLR1);
794 register_intc_controller(&intc_desc_irl0123);
795 break;
796 default:
797 BUG();
798 }
799}
800
801void __init plat_mem_setup(void)
802{
803}
804
805static int __init sh7786_devices_setup(void)
806{
807 int ret, irq;
808
809 sh7786_usb_setup();
810
811
812
813
814 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
815 if (irq > 0) {
816 scif1_demux_resources[1].start =
817 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
818 scif1_demux_resources[2].start =
819 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
820 scif1_demux_resources[3].start = irq;
821 scif1_demux_resources[4].start =
822 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
823
824 scif1_device.resource = scif1_demux_resources;
825 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
826 }
827
828 ret = platform_add_devices(sh7786_early_devices,
829 ARRAY_SIZE(sh7786_early_devices));
830 if (unlikely(ret != 0))
831 return ret;
832
833 return platform_add_devices(sh7786_devices,
834 ARRAY_SIZE(sh7786_devices));
835}
836arch_initcall(sh7786_devices_setup);
837
838void __init plat_early_device_setup(void)
839{
840 early_platform_add_devices(sh7786_early_devices,
841 ARRAY_SIZE(sh7786_early_devices));
842}
843
