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25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/slab.h>
28#include <linux/err.h>
29#include <linux/cacheinfo.h>
30#include <linux/cpuhotplug.h>
31
32#include <asm/intel-family.h>
33#include <asm/intel_rdt_sched.h>
34#include "intel_rdt.h"
35
36#define MAX_MBA_BW 100u
37#define MBA_IS_LINEAR 0x4
38
39
40DEFINE_MUTEX(rdtgroup_mutex);
41
42
43
44
45
46
47
48DEFINE_PER_CPU(struct intel_pqr_state, pqr_state);
49
50
51
52
53
54int max_name_width, max_data_width;
55
56
57
58
59
60bool rdt_alloc_capable;
61
62static void
63mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
64static void
65cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);
66
67#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
68
69struct rdt_resource rdt_resources_all[] = {
70 [RDT_RESOURCE_L3] =
71 {
72 .rid = RDT_RESOURCE_L3,
73 .name = "L3",
74 .domains = domain_init(RDT_RESOURCE_L3),
75 .msr_base = IA32_L3_CBM_BASE,
76 .msr_update = cat_wrmsr,
77 .cache_level = 3,
78 .cache = {
79 .min_cbm_bits = 1,
80 .cbm_idx_mult = 1,
81 .cbm_idx_offset = 0,
82 },
83 .parse_ctrlval = parse_cbm,
84 .format_str = "%d=%0*x",
85 .fflags = RFTYPE_RES_CACHE,
86 },
87 [RDT_RESOURCE_L3DATA] =
88 {
89 .rid = RDT_RESOURCE_L3DATA,
90 .name = "L3DATA",
91 .domains = domain_init(RDT_RESOURCE_L3DATA),
92 .msr_base = IA32_L3_CBM_BASE,
93 .msr_update = cat_wrmsr,
94 .cache_level = 3,
95 .cache = {
96 .min_cbm_bits = 1,
97 .cbm_idx_mult = 2,
98 .cbm_idx_offset = 0,
99 },
100 .parse_ctrlval = parse_cbm,
101 .format_str = "%d=%0*x",
102 .fflags = RFTYPE_RES_CACHE,
103 },
104 [RDT_RESOURCE_L3CODE] =
105 {
106 .rid = RDT_RESOURCE_L3CODE,
107 .name = "L3CODE",
108 .domains = domain_init(RDT_RESOURCE_L3CODE),
109 .msr_base = IA32_L3_CBM_BASE,
110 .msr_update = cat_wrmsr,
111 .cache_level = 3,
112 .cache = {
113 .min_cbm_bits = 1,
114 .cbm_idx_mult = 2,
115 .cbm_idx_offset = 1,
116 },
117 .parse_ctrlval = parse_cbm,
118 .format_str = "%d=%0*x",
119 .fflags = RFTYPE_RES_CACHE,
120 },
121 [RDT_RESOURCE_L2] =
122 {
123 .rid = RDT_RESOURCE_L2,
124 .name = "L2",
125 .domains = domain_init(RDT_RESOURCE_L2),
126 .msr_base = IA32_L2_CBM_BASE,
127 .msr_update = cat_wrmsr,
128 .cache_level = 2,
129 .cache = {
130 .min_cbm_bits = 1,
131 .cbm_idx_mult = 1,
132 .cbm_idx_offset = 0,
133 },
134 .parse_ctrlval = parse_cbm,
135 .format_str = "%d=%0*x",
136 .fflags = RFTYPE_RES_CACHE,
137 },
138 [RDT_RESOURCE_MBA] =
139 {
140 .rid = RDT_RESOURCE_MBA,
141 .name = "MB",
142 .domains = domain_init(RDT_RESOURCE_MBA),
143 .msr_base = IA32_MBA_THRTL_BASE,
144 .msr_update = mba_wrmsr,
145 .cache_level = 3,
146 .parse_ctrlval = parse_bw,
147 .format_str = "%d=%*d",
148 .fflags = RFTYPE_RES_MB,
149 },
150};
151
152static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid)
153{
154 return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;
155}
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174
175static inline void cache_alloc_hsw_probe(void)
176{
177 struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
178 u32 l, h, max_cbm = BIT_MASK(20) - 1;
179
180 if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
181 return;
182 rdmsr(IA32_L3_CBM_BASE, l, h);
183
184
185 if (l != max_cbm)
186 return;
187
188 r->num_closid = 4;
189 r->default_ctrl = max_cbm;
190 r->cache.cbm_len = 20;
191 r->cache.shareable_bits = 0xc0000;
192 r->cache.min_cbm_bits = 2;
193 r->alloc_capable = true;
194 r->alloc_enabled = true;
195
196 rdt_alloc_capable = true;
197}
198
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206
207
208
209static inline bool rdt_get_mb_table(struct rdt_resource *r)
210{
211
212
213
214 pr_info("MBA b/w map not implemented for cpu:%d, model:%d",
215 boot_cpu_data.x86, boot_cpu_data.x86_model);
216
217 return false;
218}
219
220static bool rdt_get_mem_config(struct rdt_resource *r)
221{
222 union cpuid_0x10_3_eax eax;
223 union cpuid_0x10_x_edx edx;
224 u32 ebx, ecx;
225
226 cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);
227 r->num_closid = edx.split.cos_max + 1;
228 r->membw.max_delay = eax.split.max_delay + 1;
229 r->default_ctrl = MAX_MBA_BW;
230 if (ecx & MBA_IS_LINEAR) {
231 r->membw.delay_linear = true;
232 r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay;
233 r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay;
234 } else {
235 if (!rdt_get_mb_table(r))
236 return false;
237 }
238 r->data_width = 3;
239
240 r->alloc_capable = true;
241 r->alloc_enabled = true;
242
243 return true;
244}
245
246static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r)
247{
248 union cpuid_0x10_1_eax eax;
249 union cpuid_0x10_x_edx edx;
250 u32 ebx, ecx;
251
252 cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
253 r->num_closid = edx.split.cos_max + 1;
254 r->cache.cbm_len = eax.split.cbm_len + 1;
255 r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;
256 r->cache.shareable_bits = ebx & r->default_ctrl;
257 r->data_width = (r->cache.cbm_len + 3) / 4;
258 r->alloc_capable = true;
259 r->alloc_enabled = true;
260}
261
262static void rdt_get_cdp_l3_config(int type)
263{
264 struct rdt_resource *r_l3 = &rdt_resources_all[RDT_RESOURCE_L3];
265 struct rdt_resource *r = &rdt_resources_all[type];
266
267 r->num_closid = r_l3->num_closid / 2;
268 r->cache.cbm_len = r_l3->cache.cbm_len;
269 r->default_ctrl = r_l3->default_ctrl;
270 r->data_width = (r->cache.cbm_len + 3) / 4;
271 r->alloc_capable = true;
272
273
274
275
276 r->alloc_enabled = false;
277}
278
279static int get_cache_id(int cpu, int level)
280{
281 struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
282 int i;
283
284 for (i = 0; i < ci->num_leaves; i++) {
285 if (ci->info_list[i].level == level)
286 return ci->info_list[i].id;
287 }
288
289 return -1;
290}
291
292
293
294
295
296
297static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r)
298{
299 if (r->membw.delay_linear)
300 return MAX_MBA_BW - bw;
301
302 pr_warn_once("Non Linear delay-bw map not supported but queried\n");
303 return r->default_ctrl;
304}
305
306static void
307mba_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
308{
309 unsigned int i;
310
311
312 for (i = m->low; i < m->high; i++)
313 wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));
314}
315
316static void
317cat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r)
318{
319 unsigned int i;
320
321 for (i = m->low; i < m->high; i++)
322 wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]);
323}
324
325struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r)
326{
327 struct rdt_domain *d;
328
329 list_for_each_entry(d, &r->domains, list) {
330
331 if (cpumask_test_cpu(cpu, &d->cpu_mask))
332 return d;
333 }
334
335 return NULL;
336}
337
338void rdt_ctrl_update(void *arg)
339{
340 struct msr_param *m = arg;
341 struct rdt_resource *r = m->res;
342 int cpu = smp_processor_id();
343 struct rdt_domain *d;
344
345 d = get_domain_from_cpu(cpu, r);
346 if (d) {
347 r->msr_update(d, m, r);
348 return;
349 }
350 pr_warn_once("cpu %d not found in any domain for resource %s\n",
351 cpu, r->name);
352}
353
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357
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359
360
361
362struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,
363 struct list_head **pos)
364{
365 struct rdt_domain *d;
366 struct list_head *l;
367
368 if (id < 0)
369 return ERR_PTR(id);
370
371 list_for_each(l, &r->domains) {
372 d = list_entry(l, struct rdt_domain, list);
373
374 if (id == d->id)
375 return d;
376
377 if (id < d->id)
378 break;
379 }
380
381 if (pos)
382 *pos = l;
383
384 return NULL;
385}
386
387static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d)
388{
389 struct msr_param m;
390 u32 *dc;
391 int i;
392
393 dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL);
394 if (!dc)
395 return -ENOMEM;
396
397 d->ctrl_val = dc;
398
399
400
401
402
403
404 for (i = 0; i < r->num_closid; i++, dc++)
405 *dc = r->default_ctrl;
406
407 m.low = 0;
408 m.high = r->num_closid;
409 r->msr_update(d, &m, r);
410 return 0;
411}
412
413static int domain_setup_mon_state(struct rdt_resource *r, struct rdt_domain *d)
414{
415 size_t tsize;
416
417 if (is_llc_occupancy_enabled()) {
418 d->rmid_busy_llc = kcalloc(BITS_TO_LONGS(r->num_rmid),
419 sizeof(unsigned long),
420 GFP_KERNEL);
421 if (!d->rmid_busy_llc)
422 return -ENOMEM;
423 INIT_DELAYED_WORK(&d->cqm_limbo, cqm_handle_limbo);
424 }
425 if (is_mbm_total_enabled()) {
426 tsize = sizeof(*d->mbm_total);
427 d->mbm_total = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
428 if (!d->mbm_total) {
429 kfree(d->rmid_busy_llc);
430 return -ENOMEM;
431 }
432 }
433 if (is_mbm_local_enabled()) {
434 tsize = sizeof(*d->mbm_local);
435 d->mbm_local = kcalloc(r->num_rmid, tsize, GFP_KERNEL);
436 if (!d->mbm_local) {
437 kfree(d->rmid_busy_llc);
438 kfree(d->mbm_total);
439 return -ENOMEM;
440 }
441 }
442
443 if (is_mbm_enabled()) {
444 INIT_DELAYED_WORK(&d->mbm_over, mbm_handle_overflow);
445 mbm_setup_overflow_handler(d, MBM_OVERFLOW_INTERVAL);
446 }
447
448 return 0;
449}
450
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462
463
464static void domain_add_cpu(int cpu, struct rdt_resource *r)
465{
466 int id = get_cache_id(cpu, r->cache_level);
467 struct list_head *add_pos = NULL;
468 struct rdt_domain *d;
469
470 d = rdt_find_domain(r, id, &add_pos);
471 if (IS_ERR(d)) {
472 pr_warn("Could't find cache id for cpu %d\n", cpu);
473 return;
474 }
475
476 if (d) {
477 cpumask_set_cpu(cpu, &d->cpu_mask);
478 return;
479 }
480
481 d = kzalloc_node(sizeof(*d), GFP_KERNEL, cpu_to_node(cpu));
482 if (!d)
483 return;
484
485 d->id = id;
486 cpumask_set_cpu(cpu, &d->cpu_mask);
487
488 if (r->alloc_capable && domain_setup_ctrlval(r, d)) {
489 kfree(d);
490 return;
491 }
492
493 if (r->mon_capable && domain_setup_mon_state(r, d)) {
494 kfree(d);
495 return;
496 }
497
498 list_add_tail(&d->list, add_pos);
499
500
501
502
503
504 if (static_branch_unlikely(&rdt_mon_enable_key))
505 mkdir_mondata_subdir_allrdtgrp(r, d);
506}
507
508static void domain_remove_cpu(int cpu, struct rdt_resource *r)
509{
510 int id = get_cache_id(cpu, r->cache_level);
511 struct rdt_domain *d;
512
513 d = rdt_find_domain(r, id, NULL);
514 if (IS_ERR_OR_NULL(d)) {
515 pr_warn("Could't find cache id for cpu %d\n", cpu);
516 return;
517 }
518
519 cpumask_clear_cpu(cpu, &d->cpu_mask);
520 if (cpumask_empty(&d->cpu_mask)) {
521
522
523
524
525 if (static_branch_unlikely(&rdt_mon_enable_key))
526 rmdir_mondata_subdir_allrdtgrp(r, d->id);
527 kfree(d->ctrl_val);
528 kfree(d->rmid_busy_llc);
529 kfree(d->mbm_total);
530 kfree(d->mbm_local);
531 list_del(&d->list);
532 if (is_mbm_enabled())
533 cancel_delayed_work(&d->mbm_over);
534 if (is_llc_occupancy_enabled() && has_busy_rmid(r, d)) {
535
536
537
538
539
540
541
542
543 __check_limbo(d, true);
544 cancel_delayed_work(&d->cqm_limbo);
545 }
546
547 kfree(d);
548 return;
549 }
550
551 if (r == &rdt_resources_all[RDT_RESOURCE_L3]) {
552 if (is_mbm_enabled() && cpu == d->mbm_work_cpu) {
553 cancel_delayed_work(&d->mbm_over);
554 mbm_setup_overflow_handler(d, 0);
555 }
556 if (is_llc_occupancy_enabled() && cpu == d->cqm_work_cpu &&
557 has_busy_rmid(r, d)) {
558 cancel_delayed_work(&d->cqm_limbo);
559 cqm_setup_limbo_handler(d, 0);
560 }
561 }
562}
563
564static void clear_closid_rmid(int cpu)
565{
566 struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
567
568 state->default_closid = 0;
569 state->default_rmid = 0;
570 state->cur_closid = 0;
571 state->cur_rmid = 0;
572 wrmsr(IA32_PQR_ASSOC, 0, 0);
573}
574
575static int intel_rdt_online_cpu(unsigned int cpu)
576{
577 struct rdt_resource *r;
578
579 mutex_lock(&rdtgroup_mutex);
580 for_each_capable_rdt_resource(r)
581 domain_add_cpu(cpu, r);
582
583 cpumask_set_cpu(cpu, &rdtgroup_default.cpu_mask);
584 clear_closid_rmid(cpu);
585 mutex_unlock(&rdtgroup_mutex);
586
587 return 0;
588}
589
590static void clear_childcpus(struct rdtgroup *r, unsigned int cpu)
591{
592 struct rdtgroup *cr;
593
594 list_for_each_entry(cr, &r->mon.crdtgrp_list, mon.crdtgrp_list) {
595 if (cpumask_test_and_clear_cpu(cpu, &cr->cpu_mask)) {
596 break;
597 }
598 }
599}
600
601static int intel_rdt_offline_cpu(unsigned int cpu)
602{
603 struct rdtgroup *rdtgrp;
604 struct rdt_resource *r;
605
606 mutex_lock(&rdtgroup_mutex);
607 for_each_capable_rdt_resource(r)
608 domain_remove_cpu(cpu, r);
609 list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) {
610 if (cpumask_test_and_clear_cpu(cpu, &rdtgrp->cpu_mask)) {
611 clear_childcpus(rdtgrp, cpu);
612 break;
613 }
614 }
615 clear_closid_rmid(cpu);
616 mutex_unlock(&rdtgroup_mutex);
617
618 return 0;
619}
620
621
622
623
624
625static __init void rdt_init_padding(void)
626{
627 struct rdt_resource *r;
628 int cl;
629
630 for_each_alloc_capable_rdt_resource(r) {
631 cl = strlen(r->name);
632 if (cl > max_name_width)
633 max_name_width = cl;
634
635 if (r->data_width > max_data_width)
636 max_data_width = r->data_width;
637 }
638}
639
640enum {
641 RDT_FLAG_CMT,
642 RDT_FLAG_MBM_TOTAL,
643 RDT_FLAG_MBM_LOCAL,
644 RDT_FLAG_L3_CAT,
645 RDT_FLAG_L3_CDP,
646 RDT_FLAG_L2_CAT,
647 RDT_FLAG_MBA,
648};
649
650#define RDT_OPT(idx, n, f) \
651[idx] = { \
652 .name = n, \
653 .flag = f \
654}
655
656struct rdt_options {
657 char *name;
658 int flag;
659 bool force_off, force_on;
660};
661
662static struct rdt_options rdt_options[] __initdata = {
663 RDT_OPT(RDT_FLAG_CMT, "cmt", X86_FEATURE_CQM_OCCUP_LLC),
664 RDT_OPT(RDT_FLAG_MBM_TOTAL, "mbmtotal", X86_FEATURE_CQM_MBM_TOTAL),
665 RDT_OPT(RDT_FLAG_MBM_LOCAL, "mbmlocal", X86_FEATURE_CQM_MBM_LOCAL),
666 RDT_OPT(RDT_FLAG_L3_CAT, "l3cat", X86_FEATURE_CAT_L3),
667 RDT_OPT(RDT_FLAG_L3_CDP, "l3cdp", X86_FEATURE_CDP_L3),
668 RDT_OPT(RDT_FLAG_L2_CAT, "l2cat", X86_FEATURE_CAT_L2),
669 RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA),
670};
671#define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options)
672
673static int __init set_rdt_options(char *str)
674{
675 struct rdt_options *o;
676 bool force_off;
677 char *tok;
678
679 if (*str == '=')
680 str++;
681 while ((tok = strsep(&str, ",")) != NULL) {
682 force_off = *tok == '!';
683 if (force_off)
684 tok++;
685 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
686 if (strcmp(tok, o->name) == 0) {
687 if (force_off)
688 o->force_off = true;
689 else
690 o->force_on = true;
691 break;
692 }
693 }
694 }
695 return 1;
696}
697__setup("rdt", set_rdt_options);
698
699static bool __init rdt_cpu_has(int flag)
700{
701 bool ret = boot_cpu_has(flag);
702 struct rdt_options *o;
703
704 if (!ret)
705 return ret;
706
707 for (o = rdt_options; o < &rdt_options[NUM_RDT_OPTIONS]; o++) {
708 if (flag == o->flag) {
709 if (o->force_off)
710 ret = false;
711 if (o->force_on)
712 ret = true;
713 break;
714 }
715 }
716 return ret;
717}
718
719static __init bool get_rdt_alloc_resources(void)
720{
721 bool ret = false;
722
723 if (rdt_alloc_capable)
724 return true;
725
726 if (!boot_cpu_has(X86_FEATURE_RDT_A))
727 return false;
728
729 if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {
730 rdt_get_cache_alloc_cfg(1, &rdt_resources_all[RDT_RESOURCE_L3]);
731 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) {
732 rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);
733 rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);
734 }
735 ret = true;
736 }
737 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
738
739 rdt_get_cache_alloc_cfg(2, &rdt_resources_all[RDT_RESOURCE_L2]);
740 ret = true;
741 }
742
743 if (rdt_cpu_has(X86_FEATURE_MBA)) {
744 if (rdt_get_mem_config(&rdt_resources_all[RDT_RESOURCE_MBA]))
745 ret = true;
746 }
747 return ret;
748}
749
750static __init bool get_rdt_mon_resources(void)
751{
752 if (rdt_cpu_has(X86_FEATURE_CQM_OCCUP_LLC))
753 rdt_mon_features |= (1 << QOS_L3_OCCUP_EVENT_ID);
754 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL))
755 rdt_mon_features |= (1 << QOS_L3_MBM_TOTAL_EVENT_ID);
756 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL))
757 rdt_mon_features |= (1 << QOS_L3_MBM_LOCAL_EVENT_ID);
758
759 if (!rdt_mon_features)
760 return false;
761
762 return !rdt_get_mon_l3_config(&rdt_resources_all[RDT_RESOURCE_L3]);
763}
764
765static __init void rdt_quirks(void)
766{
767 switch (boot_cpu_data.x86_model) {
768 case INTEL_FAM6_HASWELL_X:
769 if (!rdt_options[RDT_FLAG_L3_CAT].force_off)
770 cache_alloc_hsw_probe();
771 break;
772 case INTEL_FAM6_SKYLAKE_X:
773 if (boot_cpu_data.x86_mask <= 4)
774 set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
775 }
776}
777
778static __init bool get_rdt_resources(void)
779{
780 rdt_quirks();
781 rdt_alloc_capable = get_rdt_alloc_resources();
782 rdt_mon_capable = get_rdt_mon_resources();
783
784 return (rdt_mon_capable || rdt_alloc_capable);
785}
786
787static int __init intel_rdt_late_init(void)
788{
789 struct rdt_resource *r;
790 int state, ret;
791
792 if (!get_rdt_resources())
793 return -ENODEV;
794
795 rdt_init_padding();
796
797 state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
798 "x86/rdt/cat:online:",
799 intel_rdt_online_cpu, intel_rdt_offline_cpu);
800 if (state < 0)
801 return state;
802
803 ret = rdtgroup_init();
804 if (ret) {
805 cpuhp_remove_state(state);
806 return ret;
807 }
808
809 for_each_alloc_capable_rdt_resource(r)
810 pr_info("Intel RDT %s allocation detected\n", r->name);
811
812 for_each_mon_capable_rdt_resource(r)
813 pr_info("Intel RDT %s monitoring detected\n", r->name);
814
815 return 0;
816}
817
818late_initcall(intel_rdt_late_init);
819