linux/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
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   1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26#include <drm/drmP.h>
  27#include <drm/amdgpu_drm.h>
  28#include "amdgpu.h"
  29#include "amdgpu_atombios.h"
  30#include "amdgpu_i2c.h"
  31
  32#include "atom.h"
  33#include "atom-bits.h"
  34#include "atombios_encoders.h"
  35#include "bif/bif_4_1_d.h"
  36
  37static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev,
  38                                          ATOM_GPIO_I2C_ASSIGMENT *gpio,
  39                                          u8 index)
  40{
  41
  42}
  43
  44static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
  45{
  46        struct amdgpu_i2c_bus_rec i2c;
  47
  48        memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  49
  50        i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
  51        i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
  52        i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
  53        i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
  54        i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
  55        i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
  56        i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
  57        i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
  58        i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
  59        i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
  60        i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
  61        i2c.en_data_mask = (1 << gpio->ucDataEnShift);
  62        i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
  63        i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
  64        i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
  65        i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
  66
  67        if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
  68                i2c.hw_capable = true;
  69        else
  70                i2c.hw_capable = false;
  71
  72        if (gpio->sucI2cId.ucAccess == 0xa0)
  73                i2c.mm_i2c = true;
  74        else
  75                i2c.mm_i2c = false;
  76
  77        i2c.i2c_id = gpio->sucI2cId.ucAccess;
  78
  79        if (i2c.mask_clk_reg)
  80                i2c.valid = true;
  81        else
  82                i2c.valid = false;
  83
  84        return i2c;
  85}
  86
  87struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
  88                                                          uint8_t id)
  89{
  90        struct atom_context *ctx = adev->mode_info.atom_context;
  91        ATOM_GPIO_I2C_ASSIGMENT *gpio;
  92        struct amdgpu_i2c_bus_rec i2c;
  93        int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  94        struct _ATOM_GPIO_I2C_INFO *i2c_info;
  95        uint16_t data_offset, size;
  96        int i, num_indices;
  97
  98        memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
  99        i2c.valid = false;
 100
 101        if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 102                i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 103
 104                num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 105                        sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 106
 107                gpio = &i2c_info->asGPIO_Info[0];
 108                for (i = 0; i < num_indices; i++) {
 109
 110                        amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 111
 112                        if (gpio->sucI2cId.ucAccess == id) {
 113                                i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 114                                break;
 115                        }
 116                        gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 117                                ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 118                }
 119        }
 120
 121        return i2c;
 122}
 123
 124void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
 125{
 126        struct atom_context *ctx = adev->mode_info.atom_context;
 127        ATOM_GPIO_I2C_ASSIGMENT *gpio;
 128        struct amdgpu_i2c_bus_rec i2c;
 129        int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 130        struct _ATOM_GPIO_I2C_INFO *i2c_info;
 131        uint16_t data_offset, size;
 132        int i, num_indices;
 133        char stmp[32];
 134
 135        if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 136                i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 137
 138                num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 139                        sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 140
 141                gpio = &i2c_info->asGPIO_Info[0];
 142                for (i = 0; i < num_indices; i++) {
 143                        amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i);
 144
 145                        i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
 146
 147                        if (i2c.valid) {
 148                                sprintf(stmp, "0x%x", i2c.i2c_id);
 149                                adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp);
 150                        }
 151                        gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
 152                                ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
 153                }
 154        }
 155}
 156
 157struct amdgpu_gpio_rec
 158amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
 159                            u8 id)
 160{
 161        struct atom_context *ctx = adev->mode_info.atom_context;
 162        struct amdgpu_gpio_rec gpio;
 163        int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 164        struct _ATOM_GPIO_PIN_LUT *gpio_info;
 165        ATOM_GPIO_PIN_ASSIGNMENT *pin;
 166        u16 data_offset, size;
 167        int i, num_indices;
 168
 169        memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
 170        gpio.valid = false;
 171
 172        if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 173                gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 174
 175                num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 176                        sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 177
 178                pin = gpio_info->asGPIO_Pin;
 179                for (i = 0; i < num_indices; i++) {
 180                        if (id == pin->ucGPIO_ID) {
 181                                gpio.id = pin->ucGPIO_ID;
 182                                gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
 183                                gpio.shift = pin->ucGpioPinBitShift;
 184                                gpio.mask = (1 << pin->ucGpioPinBitShift);
 185                                gpio.valid = true;
 186                                break;
 187                        }
 188                        pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
 189                                ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
 190                }
 191        }
 192
 193        return gpio;
 194}
 195
 196static struct amdgpu_hpd
 197amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 198                                       struct amdgpu_gpio_rec *gpio)
 199{
 200        struct amdgpu_hpd hpd;
 201        u32 reg;
 202
 203        memset(&hpd, 0, sizeof(struct amdgpu_hpd));
 204
 205        reg = amdgpu_display_hpd_get_gpio_reg(adev);
 206
 207        hpd.gpio = *gpio;
 208        if (gpio->reg == reg) {
 209                switch(gpio->mask) {
 210                case (1 << 0):
 211                        hpd.hpd = AMDGPU_HPD_1;
 212                        break;
 213                case (1 << 8):
 214                        hpd.hpd = AMDGPU_HPD_2;
 215                        break;
 216                case (1 << 16):
 217                        hpd.hpd = AMDGPU_HPD_3;
 218                        break;
 219                case (1 << 24):
 220                        hpd.hpd = AMDGPU_HPD_4;
 221                        break;
 222                case (1 << 26):
 223                        hpd.hpd = AMDGPU_HPD_5;
 224                        break;
 225                case (1 << 28):
 226                        hpd.hpd = AMDGPU_HPD_6;
 227                        break;
 228                default:
 229                        hpd.hpd = AMDGPU_HPD_NONE;
 230                        break;
 231                }
 232        } else
 233                hpd.hpd = AMDGPU_HPD_NONE;
 234        return hpd;
 235}
 236
 237static const int object_connector_convert[] = {
 238        DRM_MODE_CONNECTOR_Unknown,
 239        DRM_MODE_CONNECTOR_DVII,
 240        DRM_MODE_CONNECTOR_DVII,
 241        DRM_MODE_CONNECTOR_DVID,
 242        DRM_MODE_CONNECTOR_DVID,
 243        DRM_MODE_CONNECTOR_VGA,
 244        DRM_MODE_CONNECTOR_Composite,
 245        DRM_MODE_CONNECTOR_SVIDEO,
 246        DRM_MODE_CONNECTOR_Unknown,
 247        DRM_MODE_CONNECTOR_Unknown,
 248        DRM_MODE_CONNECTOR_9PinDIN,
 249        DRM_MODE_CONNECTOR_Unknown,
 250        DRM_MODE_CONNECTOR_HDMIA,
 251        DRM_MODE_CONNECTOR_HDMIB,
 252        DRM_MODE_CONNECTOR_LVDS,
 253        DRM_MODE_CONNECTOR_9PinDIN,
 254        DRM_MODE_CONNECTOR_Unknown,
 255        DRM_MODE_CONNECTOR_Unknown,
 256        DRM_MODE_CONNECTOR_Unknown,
 257        DRM_MODE_CONNECTOR_DisplayPort,
 258        DRM_MODE_CONNECTOR_eDP,
 259        DRM_MODE_CONNECTOR_Unknown
 260};
 261
 262bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
 263{
 264        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 265        struct atom_context *ctx = mode_info->atom_context;
 266        int index = GetIndexIntoMasterTable(DATA, Object_Header);
 267        u16 size, data_offset;
 268        u8 frev, crev;
 269        ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 270        ATOM_OBJECT_HEADER *obj_header;
 271
 272        if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 273                return false;
 274
 275        if (crev < 2)
 276                return false;
 277
 278        obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 279        path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 280            (ctx->bios + data_offset +
 281             le16_to_cpu(obj_header->usDisplayPathTableOffset));
 282
 283        if (path_obj->ucNumOfDispPath)
 284                return true;
 285        else
 286                return false;
 287}
 288
 289bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
 290{
 291        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 292        struct atom_context *ctx = mode_info->atom_context;
 293        int index = GetIndexIntoMasterTable(DATA, Object_Header);
 294        u16 size, data_offset;
 295        u8 frev, crev;
 296        ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 297        ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 298        ATOM_OBJECT_TABLE *router_obj;
 299        ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 300        ATOM_OBJECT_HEADER *obj_header;
 301        int i, j, k, path_size, device_support;
 302        int connector_type;
 303        u16 conn_id, connector_object_id;
 304        struct amdgpu_i2c_bus_rec ddc_bus;
 305        struct amdgpu_router router;
 306        struct amdgpu_gpio_rec gpio;
 307        struct amdgpu_hpd hpd;
 308
 309        if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 310                return false;
 311
 312        if (crev < 2)
 313                return false;
 314
 315        obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 316        path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 317            (ctx->bios + data_offset +
 318             le16_to_cpu(obj_header->usDisplayPathTableOffset));
 319        con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 320            (ctx->bios + data_offset +
 321             le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 322        enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 323            (ctx->bios + data_offset +
 324             le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 325        router_obj = (ATOM_OBJECT_TABLE *)
 326                (ctx->bios + data_offset +
 327                 le16_to_cpu(obj_header->usRouterObjectTableOffset));
 328        device_support = le16_to_cpu(obj_header->usDeviceSupport);
 329
 330        path_size = 0;
 331        for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 332                uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 333                ATOM_DISPLAY_OBJECT_PATH *path;
 334                addr += path_size;
 335                path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 336                path_size += le16_to_cpu(path->usSize);
 337
 338                if (device_support & le16_to_cpu(path->usDeviceTag)) {
 339                        uint8_t con_obj_id, con_obj_num, con_obj_type;
 340
 341                        con_obj_id =
 342                            (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 343                            >> OBJECT_ID_SHIFT;
 344                        con_obj_num =
 345                            (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 346                            >> ENUM_ID_SHIFT;
 347                        con_obj_type =
 348                            (le16_to_cpu(path->usConnObjectId) &
 349                             OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 350
 351                        /* Skip TV/CV support */
 352                        if ((le16_to_cpu(path->usDeviceTag) ==
 353                             ATOM_DEVICE_TV1_SUPPORT) ||
 354                            (le16_to_cpu(path->usDeviceTag) ==
 355                             ATOM_DEVICE_CV_SUPPORT))
 356                                continue;
 357
 358                        if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
 359                                DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
 360                                          con_obj_id, le16_to_cpu(path->usDeviceTag));
 361                                continue;
 362                        }
 363
 364                        connector_type =
 365                                object_connector_convert[con_obj_id];
 366                        connector_object_id = con_obj_id;
 367
 368                        if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 369                                continue;
 370
 371                        router.ddc_valid = false;
 372                        router.cd_valid = false;
 373                        for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 374                                uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 375
 376                                grph_obj_id =
 377                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
 378                                     OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 379                                grph_obj_num =
 380                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
 381                                     ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 382                                grph_obj_type =
 383                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
 384                                     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 385
 386                                if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 387                                        for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 388                                                u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 389                                                if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 390                                                        ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 391                                                                (ctx->bios + data_offset +
 392                                                                 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 393                                                        ATOM_ENCODER_CAP_RECORD *cap_record;
 394                                                        u16 caps = 0;
 395
 396                                                        while (record->ucRecordSize > 0 &&
 397                                                               record->ucRecordType > 0 &&
 398                                                               record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 399                                                                switch (record->ucRecordType) {
 400                                                                case ATOM_ENCODER_CAP_RECORD_TYPE:
 401                                                                        cap_record =(ATOM_ENCODER_CAP_RECORD *)
 402                                                                                record;
 403                                                                        caps = le16_to_cpu(cap_record->usEncoderCap);
 404                                                                        break;
 405                                                                }
 406                                                                record = (ATOM_COMMON_RECORD_HEADER *)
 407                                                                        ((char *)record + record->ucRecordSize);
 408                                                        }
 409                                                        amdgpu_display_add_encoder(adev, encoder_obj,
 410                                                                                    le16_to_cpu(path->usDeviceTag),
 411                                                                                    caps);
 412                                                }
 413                                        }
 414                                } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 415                                        for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 416                                                u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 417                                                if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 418                                                        ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 419                                                                (ctx->bios + data_offset +
 420                                                                 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 421                                                        ATOM_I2C_RECORD *i2c_record;
 422                                                        ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 423                                                        ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 424                                                        ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 425                                                        ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 426                                                                (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 427                                                                (ctx->bios + data_offset +
 428                                                                 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 429                                                        u8 *num_dst_objs = (u8 *)
 430                                                                ((u8 *)router_src_dst_table + 1 +
 431                                                                 (router_src_dst_table->ucNumberOfSrc * 2));
 432                                                        u16 *dst_objs = (u16 *)(num_dst_objs + 1);
 433                                                        int enum_id;
 434
 435                                                        router.router_id = router_obj_id;
 436                                                        for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
 437                                                                if (le16_to_cpu(path->usConnObjectId) ==
 438                                                                    le16_to_cpu(dst_objs[enum_id]))
 439                                                                        break;
 440                                                        }
 441
 442                                                        while (record->ucRecordSize > 0 &&
 443                                                               record->ucRecordType > 0 &&
 444                                                               record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 445                                                                switch (record->ucRecordType) {
 446                                                                case ATOM_I2C_RECORD_TYPE:
 447                                                                        i2c_record =
 448                                                                                (ATOM_I2C_RECORD *)
 449                                                                                record;
 450                                                                        i2c_config =
 451                                                                                (ATOM_I2C_ID_CONFIG_ACCESS *)
 452                                                                                &i2c_record->sucI2cId;
 453                                                                        router.i2c_info =
 454                                                                                amdgpu_atombios_lookup_i2c_gpio(adev,
 455                                                                                                       i2c_config->
 456                                                                                                       ucAccess);
 457                                                                        router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 458                                                                        break;
 459                                                                case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 460                                                                        ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 461                                                                                record;
 462                                                                        router.ddc_valid = true;
 463                                                                        router.ddc_mux_type = ddc_path->ucMuxType;
 464                                                                        router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 465                                                                        router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 466                                                                        break;
 467                                                                case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 468                                                                        cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 469                                                                                record;
 470                                                                        router.cd_valid = true;
 471                                                                        router.cd_mux_type = cd_path->ucMuxType;
 472                                                                        router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 473                                                                        router.cd_mux_state = cd_path->ucMuxState[enum_id];
 474                                                                        break;
 475                                                                }
 476                                                                record = (ATOM_COMMON_RECORD_HEADER *)
 477                                                                        ((char *)record + record->ucRecordSize);
 478                                                        }
 479                                                }
 480                                        }
 481                                }
 482                        }
 483
 484                        /* look up gpio for ddc, hpd */
 485                        ddc_bus.valid = false;
 486                        hpd.hpd = AMDGPU_HPD_NONE;
 487                        if ((le16_to_cpu(path->usDeviceTag) &
 488                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 489                                for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 490                                        if (le16_to_cpu(path->usConnObjectId) ==
 491                                            le16_to_cpu(con_obj->asObjects[j].
 492                                                        usObjectID)) {
 493                                                ATOM_COMMON_RECORD_HEADER
 494                                                    *record =
 495                                                    (ATOM_COMMON_RECORD_HEADER
 496                                                     *)
 497                                                    (ctx->bios + data_offset +
 498                                                     le16_to_cpu(con_obj->
 499                                                                 asObjects[j].
 500                                                                 usRecordOffset));
 501                                                ATOM_I2C_RECORD *i2c_record;
 502                                                ATOM_HPD_INT_RECORD *hpd_record;
 503                                                ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 504
 505                                                while (record->ucRecordSize > 0 &&
 506                                                       record->ucRecordType > 0 &&
 507                                                       record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 508                                                        switch (record->ucRecordType) {
 509                                                        case ATOM_I2C_RECORD_TYPE:
 510                                                                i2c_record =
 511                                                                    (ATOM_I2C_RECORD *)
 512                                                                        record;
 513                                                                i2c_config =
 514                                                                        (ATOM_I2C_ID_CONFIG_ACCESS *)
 515                                                                        &i2c_record->sucI2cId;
 516                                                                ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
 517                                                                                                 i2c_config->
 518                                                                                                 ucAccess);
 519                                                                break;
 520                                                        case ATOM_HPD_INT_RECORD_TYPE:
 521                                                                hpd_record =
 522                                                                        (ATOM_HPD_INT_RECORD *)
 523                                                                        record;
 524                                                                gpio = amdgpu_atombios_lookup_gpio(adev,
 525                                                                                          hpd_record->ucHPDIntGPIOID);
 526                                                                hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
 527                                                                hpd.plugged_state = hpd_record->ucPlugged_PinState;
 528                                                                break;
 529                                                        }
 530                                                        record =
 531                                                            (ATOM_COMMON_RECORD_HEADER
 532                                                             *) ((char *)record
 533                                                                 +
 534                                                                 record->
 535                                                                 ucRecordSize);
 536                                                }
 537                                                break;
 538                                        }
 539                                }
 540                        }
 541
 542                        /* needed for aux chan transactions */
 543                        ddc_bus.hpd = hpd.hpd;
 544
 545                        conn_id = le16_to_cpu(path->usConnObjectId);
 546
 547                        amdgpu_display_add_connector(adev,
 548                                                      conn_id,
 549                                                      le16_to_cpu(path->usDeviceTag),
 550                                                      connector_type, &ddc_bus,
 551                                                      connector_object_id,
 552                                                      &hpd,
 553                                                      &router);
 554
 555                }
 556        }
 557
 558        amdgpu_link_encoder_connector(adev->ddev);
 559
 560        return true;
 561}
 562
 563union firmware_info {
 564        ATOM_FIRMWARE_INFO info;
 565        ATOM_FIRMWARE_INFO_V1_2 info_12;
 566        ATOM_FIRMWARE_INFO_V1_3 info_13;
 567        ATOM_FIRMWARE_INFO_V1_4 info_14;
 568        ATOM_FIRMWARE_INFO_V2_1 info_21;
 569        ATOM_FIRMWARE_INFO_V2_2 info_22;
 570};
 571
 572int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
 573{
 574        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 575        int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
 576        uint8_t frev, crev;
 577        uint16_t data_offset;
 578        int ret = -EINVAL;
 579
 580        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 581                                   &frev, &crev, &data_offset)) {
 582                int i;
 583                struct amdgpu_pll *ppll = &adev->clock.ppll[0];
 584                struct amdgpu_pll *spll = &adev->clock.spll;
 585                struct amdgpu_pll *mpll = &adev->clock.mpll;
 586                union firmware_info *firmware_info =
 587                        (union firmware_info *)(mode_info->atom_context->bios +
 588                                                data_offset);
 589                /* pixel clocks */
 590                ppll->reference_freq =
 591                    le16_to_cpu(firmware_info->info.usReferenceClock);
 592                ppll->reference_div = 0;
 593
 594                ppll->pll_out_min =
 595                        le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
 596                ppll->pll_out_max =
 597                    le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
 598
 599                ppll->lcd_pll_out_min =
 600                        le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
 601                if (ppll->lcd_pll_out_min == 0)
 602                        ppll->lcd_pll_out_min = ppll->pll_out_min;
 603                ppll->lcd_pll_out_max =
 604                        le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
 605                if (ppll->lcd_pll_out_max == 0)
 606                        ppll->lcd_pll_out_max = ppll->pll_out_max;
 607
 608                if (ppll->pll_out_min == 0)
 609                        ppll->pll_out_min = 64800;
 610
 611                ppll->pll_in_min =
 612                    le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
 613                ppll->pll_in_max =
 614                    le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
 615
 616                ppll->min_post_div = 2;
 617                ppll->max_post_div = 0x7f;
 618                ppll->min_frac_feedback_div = 0;
 619                ppll->max_frac_feedback_div = 9;
 620                ppll->min_ref_div = 2;
 621                ppll->max_ref_div = 0x3ff;
 622                ppll->min_feedback_div = 4;
 623                ppll->max_feedback_div = 0xfff;
 624                ppll->best_vco = 0;
 625
 626                for (i = 1; i < AMDGPU_MAX_PPLL; i++)
 627                        adev->clock.ppll[i] = *ppll;
 628
 629                /* system clock */
 630                spll->reference_freq =
 631                        le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
 632                spll->reference_div = 0;
 633
 634                spll->pll_out_min =
 635                    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
 636                spll->pll_out_max =
 637                    le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
 638
 639                /* ??? */
 640                if (spll->pll_out_min == 0)
 641                        spll->pll_out_min = 64800;
 642
 643                spll->pll_in_min =
 644                    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
 645                spll->pll_in_max =
 646                    le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
 647
 648                spll->min_post_div = 1;
 649                spll->max_post_div = 1;
 650                spll->min_ref_div = 2;
 651                spll->max_ref_div = 0xff;
 652                spll->min_feedback_div = 4;
 653                spll->max_feedback_div = 0xff;
 654                spll->best_vco = 0;
 655
 656                /* memory clock */
 657                mpll->reference_freq =
 658                        le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
 659                mpll->reference_div = 0;
 660
 661                mpll->pll_out_min =
 662                    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
 663                mpll->pll_out_max =
 664                    le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
 665
 666                /* ??? */
 667                if (mpll->pll_out_min == 0)
 668                        mpll->pll_out_min = 64800;
 669
 670                mpll->pll_in_min =
 671                    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
 672                mpll->pll_in_max =
 673                    le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
 674
 675                adev->clock.default_sclk =
 676                    le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
 677                adev->clock.default_mclk =
 678                    le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
 679
 680                mpll->min_post_div = 1;
 681                mpll->max_post_div = 1;
 682                mpll->min_ref_div = 2;
 683                mpll->max_ref_div = 0xff;
 684                mpll->min_feedback_div = 4;
 685                mpll->max_feedback_div = 0xff;
 686                mpll->best_vco = 0;
 687
 688                /* disp clock */
 689                adev->clock.default_dispclk =
 690                        le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
 691                /* set a reasonable default for DP */
 692                if (adev->clock.default_dispclk < 53900) {
 693                        DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
 694                                 adev->clock.default_dispclk / 100);
 695                        adev->clock.default_dispclk = 60000;
 696                } else if (adev->clock.default_dispclk <= 60000) {
 697                        DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n",
 698                                 adev->clock.default_dispclk / 100);
 699                        adev->clock.default_dispclk = 62500;
 700                }
 701                adev->clock.dp_extclk =
 702                        le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
 703                adev->clock.current_dispclk = adev->clock.default_dispclk;
 704
 705                adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
 706                if (adev->clock.max_pixel_clock == 0)
 707                        adev->clock.max_pixel_clock = 40000;
 708
 709                /* not technically a clock, but... */
 710                adev->mode_info.firmware_flags =
 711                        le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
 712
 713                ret = 0;
 714        }
 715
 716        adev->pm.current_sclk = adev->clock.default_sclk;
 717        adev->pm.current_mclk = adev->clock.default_mclk;
 718
 719        return ret;
 720}
 721
 722union gfx_info {
 723        ATOM_GFX_INFO_V2_1 info;
 724};
 725
 726int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
 727{
 728        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 729        int index = GetIndexIntoMasterTable(DATA, GFX_Info);
 730        uint8_t frev, crev;
 731        uint16_t data_offset;
 732        int ret = -EINVAL;
 733
 734        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 735                                   &frev, &crev, &data_offset)) {
 736                union gfx_info *gfx_info = (union gfx_info *)
 737                        (mode_info->atom_context->bios + data_offset);
 738
 739                adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
 740                adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
 741                adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
 742                adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
 743                adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
 744                adev->gfx.config.max_texture_channel_caches =
 745                        gfx_info->info.max_texture_channel_caches;
 746
 747                ret = 0;
 748        }
 749        return ret;
 750}
 751
 752union igp_info {
 753        struct _ATOM_INTEGRATED_SYSTEM_INFO info;
 754        struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
 755        struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
 756        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
 757        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
 758        struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
 759};
 760
 761/*
 762 * Return vram width from integrated system info table, if available,
 763 * or 0 if not.
 764 */
 765int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
 766{
 767        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 768        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 769        u16 data_offset, size;
 770        union igp_info *igp_info;
 771        u8 frev, crev;
 772
 773        /* get any igp specific overrides */
 774        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 775                                   &frev, &crev, &data_offset)) {
 776                igp_info = (union igp_info *)
 777                        (mode_info->atom_context->bios + data_offset);
 778                switch (crev) {
 779                case 8:
 780                case 9:
 781                        return igp_info->info_8.ucUMAChannelNumber * 64;
 782                default:
 783                        return 0;
 784                }
 785        }
 786
 787        return 0;
 788}
 789
 790static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
 791                                                 struct amdgpu_atom_ss *ss,
 792                                                 int id)
 793{
 794        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 795        int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 796        u16 data_offset, size;
 797        union igp_info *igp_info;
 798        u8 frev, crev;
 799        u16 percentage = 0, rate = 0;
 800
 801        /* get any igp specific overrides */
 802        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 803                                   &frev, &crev, &data_offset)) {
 804                igp_info = (union igp_info *)
 805                        (mode_info->atom_context->bios + data_offset);
 806                switch (crev) {
 807                case 6:
 808                        switch (id) {
 809                        case ASIC_INTERNAL_SS_ON_TMDS:
 810                                percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
 811                                rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
 812                                break;
 813                        case ASIC_INTERNAL_SS_ON_HDMI:
 814                                percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
 815                                rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
 816                                break;
 817                        case ASIC_INTERNAL_SS_ON_LVDS:
 818                                percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
 819                                rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
 820                                break;
 821                        }
 822                        break;
 823                case 7:
 824                        switch (id) {
 825                        case ASIC_INTERNAL_SS_ON_TMDS:
 826                                percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
 827                                rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
 828                                break;
 829                        case ASIC_INTERNAL_SS_ON_HDMI:
 830                                percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
 831                                rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
 832                                break;
 833                        case ASIC_INTERNAL_SS_ON_LVDS:
 834                                percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
 835                                rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
 836                                break;
 837                        }
 838                        break;
 839                case 8:
 840                        switch (id) {
 841                        case ASIC_INTERNAL_SS_ON_TMDS:
 842                                percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
 843                                rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
 844                                break;
 845                        case ASIC_INTERNAL_SS_ON_HDMI:
 846                                percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
 847                                rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
 848                                break;
 849                        case ASIC_INTERNAL_SS_ON_LVDS:
 850                                percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
 851                                rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
 852                                break;
 853                        }
 854                        break;
 855                case 9:
 856                        switch (id) {
 857                        case ASIC_INTERNAL_SS_ON_TMDS:
 858                                percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
 859                                rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
 860                                break;
 861                        case ASIC_INTERNAL_SS_ON_HDMI:
 862                                percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
 863                                rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
 864                                break;
 865                        case ASIC_INTERNAL_SS_ON_LVDS:
 866                                percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
 867                                rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
 868                                break;
 869                        }
 870                        break;
 871                default:
 872                        DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 873                        break;
 874                }
 875                if (percentage)
 876                        ss->percentage = percentage;
 877                if (rate)
 878                        ss->rate = rate;
 879        }
 880}
 881
 882union asic_ss_info {
 883        struct _ATOM_ASIC_INTERNAL_SS_INFO info;
 884        struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
 885        struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
 886};
 887
 888union asic_ss_assignment {
 889        struct _ATOM_ASIC_SS_ASSIGNMENT v1;
 890        struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
 891        struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
 892};
 893
 894bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
 895                                      struct amdgpu_atom_ss *ss,
 896                                      int id, u32 clock)
 897{
 898        struct amdgpu_mode_info *mode_info = &adev->mode_info;
 899        int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
 900        uint16_t data_offset, size;
 901        union asic_ss_info *ss_info;
 902        union asic_ss_assignment *ss_assign;
 903        uint8_t frev, crev;
 904        int i, num_indices;
 905
 906        if (id == ASIC_INTERNAL_MEMORY_SS) {
 907                if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
 908                        return false;
 909        }
 910        if (id == ASIC_INTERNAL_ENGINE_SS) {
 911                if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
 912                        return false;
 913        }
 914
 915        memset(ss, 0, sizeof(struct amdgpu_atom_ss));
 916        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 917                                   &frev, &crev, &data_offset)) {
 918
 919                ss_info =
 920                        (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
 921
 922                switch (frev) {
 923                case 1:
 924                        num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 925                                sizeof(ATOM_ASIC_SS_ASSIGNMENT);
 926
 927                        ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
 928                        for (i = 0; i < num_indices; i++) {
 929                                if ((ss_assign->v1.ucClockIndication == id) &&
 930                                    (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
 931                                        ss->percentage =
 932                                                le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
 933                                        ss->type = ss_assign->v1.ucSpreadSpectrumMode;
 934                                        ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
 935                                        ss->percentage_divider = 100;
 936                                        return true;
 937                                }
 938                                ss_assign = (union asic_ss_assignment *)
 939                                        ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
 940                        }
 941                        break;
 942                case 2:
 943                        num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 944                                sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
 945                        ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
 946                        for (i = 0; i < num_indices; i++) {
 947                                if ((ss_assign->v2.ucClockIndication == id) &&
 948                                    (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
 949                                        ss->percentage =
 950                                                le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
 951                                        ss->type = ss_assign->v2.ucSpreadSpectrumMode;
 952                                        ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
 953                                        ss->percentage_divider = 100;
 954                                        if ((crev == 2) &&
 955                                            ((id == ASIC_INTERNAL_ENGINE_SS) ||
 956                                             (id == ASIC_INTERNAL_MEMORY_SS)))
 957                                                ss->rate /= 100;
 958                                        return true;
 959                                }
 960                                ss_assign = (union asic_ss_assignment *)
 961                                        ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
 962                        }
 963                        break;
 964                case 3:
 965                        num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 966                                sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
 967                        ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
 968                        for (i = 0; i < num_indices; i++) {
 969                                if ((ss_assign->v3.ucClockIndication == id) &&
 970                                    (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
 971                                        ss->percentage =
 972                                                le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
 973                                        ss->type = ss_assign->v3.ucSpreadSpectrumMode;
 974                                        ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
 975                                        if (ss_assign->v3.ucSpreadSpectrumMode &
 976                                            SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
 977                                                ss->percentage_divider = 1000;
 978                                        else
 979                                                ss->percentage_divider = 100;
 980                                        if ((id == ASIC_INTERNAL_ENGINE_SS) ||
 981                                            (id == ASIC_INTERNAL_MEMORY_SS))
 982                                                ss->rate /= 100;
 983                                        if (adev->flags & AMD_IS_APU)
 984                                                amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
 985                                        return true;
 986                                }
 987                                ss_assign = (union asic_ss_assignment *)
 988                                        ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
 989                        }
 990                        break;
 991                default:
 992                        DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
 993                        break;
 994                }
 995
 996        }
 997        return false;
 998}
 999
1000union get_clock_dividers {
1001        struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
1002        struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
1003        struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
1004        struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
1005        struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
1006        struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1007        struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1008};
1009
1010int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1011                                       u8 clock_type,
1012                                       u32 clock,
1013                                       bool strobe_mode,
1014                                       struct atom_clock_dividers *dividers)
1015{
1016        union get_clock_dividers args;
1017        int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1018        u8 frev, crev;
1019
1020        memset(&args, 0, sizeof(args));
1021        memset(dividers, 0, sizeof(struct atom_clock_dividers));
1022
1023        if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1024                return -EINVAL;
1025
1026        switch (crev) {
1027        case 2:
1028        case 3:
1029        case 5:
1030                /* r6xx, r7xx, evergreen, ni, si.
1031                 * TODO: add support for asic_type <= CHIP_RV770*/
1032                if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1033                        args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1034
1035                        amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1036
1037                        dividers->post_div = args.v3.ucPostDiv;
1038                        dividers->enable_post_div = (args.v3.ucCntlFlag &
1039                                                     ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1040                        dividers->enable_dithen = (args.v3.ucCntlFlag &
1041                                                   ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1042                        dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1043                        dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1044                        dividers->ref_div = args.v3.ucRefDiv;
1045                        dividers->vco_mode = (args.v3.ucCntlFlag &
1046                                              ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1047                } else {
1048                        /* for SI we use ComputeMemoryClockParam for memory plls */
1049                        if (adev->asic_type >= CHIP_TAHITI)
1050                                return -EINVAL;
1051                        args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1052                        if (strobe_mode)
1053                                args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1054
1055                        amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1056
1057                        dividers->post_div = args.v5.ucPostDiv;
1058                        dividers->enable_post_div = (args.v5.ucCntlFlag &
1059                                                     ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1060                        dividers->enable_dithen = (args.v5.ucCntlFlag &
1061                                                   ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1062                        dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1063                        dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1064                        dividers->ref_div = args.v5.ucRefDiv;
1065                        dividers->vco_mode = (args.v5.ucCntlFlag &
1066                                              ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1067                }
1068                break;
1069        case 4:
1070                /* fusion */
1071                args.v4.ulClock = cpu_to_le32(clock);   /* 10 khz */
1072
1073                amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1074
1075                dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1076                dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1077                break;
1078        case 6:
1079                /* CI */
1080                /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1081                args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1082                args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);    /* 10 khz */
1083
1084                amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1085
1086                dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1087                dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1088                dividers->ref_div = args.v6_out.ucPllRefDiv;
1089                dividers->post_div = args.v6_out.ucPllPostDiv;
1090                dividers->flags = args.v6_out.ucPllCntlFlag;
1091                dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1092                dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1093                break;
1094        default:
1095                return -EINVAL;
1096        }
1097        return 0;
1098}
1099
1100int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1101                                            u32 clock,
1102                                            bool strobe_mode,
1103                                            struct atom_mpll_param *mpll_param)
1104{
1105        COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1106        int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1107        u8 frev, crev;
1108
1109        memset(&args, 0, sizeof(args));
1110        memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1111
1112        if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1113                return -EINVAL;
1114
1115        switch (frev) {
1116        case 2:
1117                switch (crev) {
1118                case 1:
1119                        /* SI */
1120                        args.ulClock = cpu_to_le32(clock);      /* 10 khz */
1121                        args.ucInputFlag = 0;
1122                        if (strobe_mode)
1123                                args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1124
1125                        amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1126
1127                        mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1128                        mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1129                        mpll_param->post_div = args.ucPostDiv;
1130                        mpll_param->dll_speed = args.ucDllSpeed;
1131                        mpll_param->bwcntl = args.ucBWCntl;
1132                        mpll_param->vco_mode =
1133                                (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1134                        mpll_param->yclk_sel =
1135                                (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1136                        mpll_param->qdr =
1137                                (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1138                        mpll_param->half_rate =
1139                                (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1140                        break;
1141                default:
1142                        return -EINVAL;
1143                }
1144                break;
1145        default:
1146                return -EINVAL;
1147        }
1148        return 0;
1149}
1150
1151void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1152                                             u32 eng_clock, u32 mem_clock)
1153{
1154        SET_ENGINE_CLOCK_PS_ALLOCATION args;
1155        int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1156        u32 tmp;
1157
1158        memset(&args, 0, sizeof(args));
1159
1160        tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1161        tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1162
1163        args.ulTargetEngineClock = cpu_to_le32(tmp);
1164        if (mem_clock)
1165                args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1166
1167        amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1168}
1169
1170void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1171                                          u16 *vddc, u16 *vddci, u16 *mvdd)
1172{
1173        struct amdgpu_mode_info *mode_info = &adev->mode_info;
1174        int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1175        u8 frev, crev;
1176        u16 data_offset;
1177        union firmware_info *firmware_info;
1178
1179        *vddc = 0;
1180        *vddci = 0;
1181        *mvdd = 0;
1182
1183        if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1184                                   &frev, &crev, &data_offset)) {
1185                firmware_info =
1186                        (union firmware_info *)(mode_info->atom_context->bios +
1187                                                data_offset);
1188                *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1189                if ((frev == 2) && (crev >= 2)) {
1190                        *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1191                        *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1192                }
1193        }
1194}
1195
1196union set_voltage {
1197        struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1198        struct _SET_VOLTAGE_PARAMETERS v1;
1199        struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1200        struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1201};
1202
1203int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1204                             u16 voltage_id, u16 *voltage)
1205{
1206        union set_voltage args;
1207        int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1208        u8 frev, crev;
1209
1210        if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1211                return -EINVAL;
1212
1213        switch (crev) {
1214        case 1:
1215                return -EINVAL;
1216        case 2:
1217                args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1218                args.v2.ucVoltageMode = 0;
1219                args.v2.usVoltageLevel = 0;
1220
1221                amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1222
1223                *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1224                break;
1225        case 3:
1226                args.v3.ucVoltageType = voltage_type;
1227                args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1228                args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1229
1230                amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1231
1232                *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1233                break;
1234        default:
1235                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1236                return -EINVAL;
1237        }
1238
1239        return 0;
1240}
1241
1242int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1243                                                      u16 *voltage,
1244                                                      u16 leakage_idx)
1245{
1246        return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1247}
1248
1249int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev,
1250                                              u16 *leakage_id)
1251{
1252        union set_voltage args;
1253        int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1254        u8 frev, crev;
1255
1256        if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1257                return -EINVAL;
1258
1259        switch (crev) {
1260        case 3:
1261        case 4:
1262                args.v3.ucVoltageType = 0;
1263                args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
1264                args.v3.usVoltageLevel = 0;
1265
1266                amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1267
1268                *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
1269                break;
1270        default:
1271                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1272                return -EINVAL;
1273        }
1274
1275        return 0;
1276}
1277
1278int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev,
1279                                                             u16 *vddc, u16 *vddci,
1280                                                             u16 virtual_voltage_id,
1281                                                             u16 vbios_voltage_id)
1282{
1283        int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
1284        u8 frev, crev;
1285        u16 data_offset, size;
1286        int i, j;
1287        ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
1288        u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
1289
1290        *vddc = 0;
1291        *vddci = 0;
1292
1293        if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1294                                    &frev, &crev, &data_offset))
1295                return -EINVAL;
1296
1297        profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
1298                (adev->mode_info.atom_context->bios + data_offset);
1299
1300        switch (frev) {
1301        case 1:
1302                return -EINVAL;
1303        case 2:
1304                switch (crev) {
1305                case 1:
1306                        if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
1307                                return -EINVAL;
1308                        leakage_bin = (u16 *)
1309                                (adev->mode_info.atom_context->bios + data_offset +
1310                                 le16_to_cpu(profile->usLeakageBinArrayOffset));
1311                        vddc_id_buf = (u16 *)
1312                                (adev->mode_info.atom_context->bios + data_offset +
1313                                 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
1314                        vddc_buf = (u16 *)
1315                                (adev->mode_info.atom_context->bios + data_offset +
1316                                 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
1317                        vddci_id_buf = (u16 *)
1318                                (adev->mode_info.atom_context->bios + data_offset +
1319                                 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
1320                        vddci_buf = (u16 *)
1321                                (adev->mode_info.atom_context->bios + data_offset +
1322                                 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
1323
1324                        if (profile->ucElbVDDC_Num > 0) {
1325                                for (i = 0; i < profile->ucElbVDDC_Num; i++) {
1326                                        if (vddc_id_buf[i] == virtual_voltage_id) {
1327                                                for (j = 0; j < profile->ucLeakageBinNum; j++) {
1328                                                        if (vbios_voltage_id <= leakage_bin[j]) {
1329                                                                *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
1330                                                                break;
1331                                                        }
1332                                                }
1333                                                break;
1334                                        }
1335                                }
1336                        }
1337                        if (profile->ucElbVDDCI_Num > 0) {
1338                                for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
1339                                        if (vddci_id_buf[i] == virtual_voltage_id) {
1340                                                for (j = 0; j < profile->ucLeakageBinNum; j++) {
1341                                                        if (vbios_voltage_id <= leakage_bin[j]) {
1342                                                                *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
1343                                                                break;
1344                                                        }
1345                                                }
1346                                                break;
1347                                        }
1348                                }
1349                        }
1350                        break;
1351                default:
1352                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1353                        return -EINVAL;
1354                }
1355                break;
1356        default:
1357                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1358                return -EINVAL;
1359        }
1360
1361        return 0;
1362}
1363
1364union get_voltage_info {
1365        struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
1366        struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
1367};
1368
1369int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev,
1370                                    u16 virtual_voltage_id,
1371                                    u16 *voltage)
1372{
1373        int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
1374        u32 entry_id;
1375        u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1376        union get_voltage_info args;
1377
1378        for (entry_id = 0; entry_id < count; entry_id++) {
1379                if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1380                    virtual_voltage_id)
1381                        break;
1382        }
1383
1384        if (entry_id >= count)
1385                return -EINVAL;
1386
1387        args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
1388        args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
1389        args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
1390        args.in.ulSCLKFreq =
1391                cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
1392
1393        amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
1394
1395        *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
1396
1397        return 0;
1398}
1399
1400union voltage_object_info {
1401        struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1402        struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1403        struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1404};
1405
1406union voltage_object {
1407        struct _ATOM_VOLTAGE_OBJECT v1;
1408        struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1409        union _ATOM_VOLTAGE_OBJECT_V3 v3;
1410};
1411
1412
1413static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1414                                                                        u8 voltage_type, u8 voltage_mode)
1415{
1416        u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1417        u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1418        u8 *start = (u8*)v3;
1419
1420        while (offset < size) {
1421                ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1422                if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1423                    (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1424                        return vo;
1425                offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1426        }
1427        return NULL;
1428}
1429
1430int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1431                              u8 voltage_type,
1432                              u8 *svd_gpio_id, u8 *svc_gpio_id)
1433{
1434        int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1435        u8 frev, crev;
1436        u16 data_offset, size;
1437        union voltage_object_info *voltage_info;
1438        union voltage_object *voltage_object = NULL;
1439
1440        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1441                                   &frev, &crev, &data_offset)) {
1442                voltage_info = (union voltage_object_info *)
1443                        (adev->mode_info.atom_context->bios + data_offset);
1444
1445                switch (frev) {
1446                case 3:
1447                        switch (crev) {
1448                        case 1:
1449                                voltage_object = (union voltage_object *)
1450                                        amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1451                                                                      voltage_type,
1452                                                                      VOLTAGE_OBJ_SVID2);
1453                                if (voltage_object) {
1454                                        *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1455                                        *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1456                                } else {
1457                                        return -EINVAL;
1458                                }
1459                                break;
1460                        default:
1461                                DRM_ERROR("unknown voltage object table\n");
1462                                return -EINVAL;
1463                        }
1464                        break;
1465                default:
1466                        DRM_ERROR("unknown voltage object table\n");
1467                        return -EINVAL;
1468                }
1469
1470        }
1471        return 0;
1472}
1473
1474bool
1475amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1476                                u8 voltage_type, u8 voltage_mode)
1477{
1478        int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1479        u8 frev, crev;
1480        u16 data_offset, size;
1481        union voltage_object_info *voltage_info;
1482
1483        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1484                                   &frev, &crev, &data_offset)) {
1485                voltage_info = (union voltage_object_info *)
1486                        (adev->mode_info.atom_context->bios + data_offset);
1487
1488                switch (frev) {
1489                case 3:
1490                        switch (crev) {
1491                        case 1:
1492                                if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1493                                                                  voltage_type, voltage_mode))
1494                                        return true;
1495                                break;
1496                        default:
1497                                DRM_ERROR("unknown voltage object table\n");
1498                                return false;
1499                        }
1500                        break;
1501                default:
1502                        DRM_ERROR("unknown voltage object table\n");
1503                        return false;
1504                }
1505
1506        }
1507        return false;
1508}
1509
1510int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1511                                      u8 voltage_type, u8 voltage_mode,
1512                                      struct atom_voltage_table *voltage_table)
1513{
1514        int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1515        u8 frev, crev;
1516        u16 data_offset, size;
1517        int i;
1518        union voltage_object_info *voltage_info;
1519        union voltage_object *voltage_object = NULL;
1520
1521        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1522                                   &frev, &crev, &data_offset)) {
1523                voltage_info = (union voltage_object_info *)
1524                        (adev->mode_info.atom_context->bios + data_offset);
1525
1526                switch (frev) {
1527                case 3:
1528                        switch (crev) {
1529                        case 1:
1530                                voltage_object = (union voltage_object *)
1531                                        amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1532                                                                      voltage_type, voltage_mode);
1533                                if (voltage_object) {
1534                                        ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1535                                                &voltage_object->v3.asGpioVoltageObj;
1536                                        VOLTAGE_LUT_ENTRY_V2 *lut;
1537                                        if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1538                                                return -EINVAL;
1539                                        lut = &gpio->asVolGpioLut[0];
1540                                        for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1541                                                voltage_table->entries[i].value =
1542                                                        le16_to_cpu(lut->usVoltageValue);
1543                                                voltage_table->entries[i].smio_low =
1544                                                        le32_to_cpu(lut->ulVoltageId);
1545                                                lut = (VOLTAGE_LUT_ENTRY_V2 *)
1546                                                        ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1547                                        }
1548                                        voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1549                                        voltage_table->count = gpio->ucGpioEntryNum;
1550                                        voltage_table->phase_delay = gpio->ucPhaseDelay;
1551                                        return 0;
1552                                }
1553                                break;
1554                        default:
1555                                DRM_ERROR("unknown voltage object table\n");
1556                                return -EINVAL;
1557                        }
1558                        break;
1559                default:
1560                        DRM_ERROR("unknown voltage object table\n");
1561                        return -EINVAL;
1562                }
1563        }
1564        return -EINVAL;
1565}
1566
1567union vram_info {
1568        struct _ATOM_VRAM_INFO_V3 v1_3;
1569        struct _ATOM_VRAM_INFO_V4 v1_4;
1570        struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1571};
1572
1573#define MEM_ID_MASK           0xff000000
1574#define MEM_ID_SHIFT          24
1575#define CLOCK_RANGE_MASK      0x00ffffff
1576#define CLOCK_RANGE_SHIFT     0
1577#define LOW_NIBBLE_MASK       0xf
1578#define DATA_EQU_PREV         0
1579#define DATA_FROM_TABLE       4
1580
1581int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1582                                      u8 module_index,
1583                                      struct atom_mc_reg_table *reg_table)
1584{
1585        int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1586        u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1587        u32 i = 0, j;
1588        u16 data_offset, size;
1589        union vram_info *vram_info;
1590
1591        memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1592
1593        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1594                                   &frev, &crev, &data_offset)) {
1595                vram_info = (union vram_info *)
1596                        (adev->mode_info.atom_context->bios + data_offset);
1597                switch (frev) {
1598                case 1:
1599                        DRM_ERROR("old table version %d, %d\n", frev, crev);
1600                        return -EINVAL;
1601                case 2:
1602                        switch (crev) {
1603                        case 1:
1604                                if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1605                                        ATOM_INIT_REG_BLOCK *reg_block =
1606                                                (ATOM_INIT_REG_BLOCK *)
1607                                                ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1608                                        ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1609                                                (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1610                                                ((u8 *)reg_block + (2 * sizeof(u16)) +
1611                                                 le16_to_cpu(reg_block->usRegIndexTblSize));
1612                                        ATOM_INIT_REG_INDEX_FORMAT *format = &reg_block->asRegIndexBuf[0];
1613                                        num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1614                                                           sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1615                                        if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1616                                                return -EINVAL;
1617                                        while (i < num_entries) {
1618                                                if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1619                                                        break;
1620                                                reg_table->mc_reg_address[i].s1 =
1621                                                        (u16)(le16_to_cpu(format->usRegIndex));
1622                                                reg_table->mc_reg_address[i].pre_reg_data =
1623                                                        (u8)(format->ucPreRegDataLength);
1624                                                i++;
1625                                                format = (ATOM_INIT_REG_INDEX_FORMAT *)
1626                                                        ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1627                                        }
1628                                        reg_table->last = i;
1629                                        while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1630                                               (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1631                                                t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1632                                                                >> MEM_ID_SHIFT);
1633                                                if (module_index == t_mem_id) {
1634                                                        reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1635                                                                (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1636                                                                      >> CLOCK_RANGE_SHIFT);
1637                                                        for (i = 0, j = 1; i < reg_table->last; i++) {
1638                                                                if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1639                                                                        reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1640                                                                                (u32)le32_to_cpu(*((u32 *)reg_data + j));
1641                                                                        j++;
1642                                                                } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1643                                                                        reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1644                                                                                reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1645                                                                }
1646                                                        }
1647                                                        num_ranges++;
1648                                                }
1649                                                reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1650                                                        ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1651                                        }
1652                                        if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1653                                                return -EINVAL;
1654                                        reg_table->num_entries = num_ranges;
1655                                } else
1656                                        return -EINVAL;
1657                                break;
1658                        default:
1659                                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1660                                return -EINVAL;
1661                        }
1662                        break;
1663                default:
1664                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1665                        return -EINVAL;
1666                }
1667                return 0;
1668        }
1669        return -EINVAL;
1670}
1671
1672bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1673{
1674        int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1675        u8 frev, crev;
1676        u16 data_offset, size;
1677
1678        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1679                                          &frev, &crev, &data_offset))
1680                return true;
1681
1682        return false;
1683}
1684
1685void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1686{
1687        uint32_t bios_6_scratch;
1688
1689        bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1690
1691        if (lock) {
1692                bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1693                bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1694        } else {
1695                bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1696                bios_6_scratch |= ATOM_S6_ACC_MODE;
1697        }
1698
1699        WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1700}
1701
1702void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1703{
1704        uint32_t bios_2_scratch, bios_6_scratch;
1705
1706        adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1707
1708        bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1709        bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1710
1711        /* let the bios control the backlight */
1712        bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1713
1714        /* tell the bios not to handle mode switching */
1715        bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1716
1717        /* clear the vbios dpms state */
1718        bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1719
1720        WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1721        WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1722}
1723
1724void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev)
1725{
1726        int i;
1727
1728        for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1729                adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i);
1730}
1731
1732void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev)
1733{
1734        int i;
1735
1736        /*
1737         * VBIOS will check ASIC_INIT_COMPLETE bit to decide if
1738         * execute ASIC_Init posting via driver
1739         */
1740        adev->bios_scratch[7] &= ~ATOM_S7_ASIC_INIT_COMPLETE_MASK;
1741
1742        for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
1743                WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);
1744}
1745
1746void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1747                                              bool hung)
1748{
1749        u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1750
1751        if (hung)
1752                tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1753        else
1754                tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1755
1756        WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1757}
1758
1759bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1760{
1761        u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1762
1763        if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1764                return false;
1765        else
1766                return true;
1767}
1768
1769/* Atom needs data in little endian format
1770 * so swap as appropriate when copying data to
1771 * or from atom. Note that atom operates on
1772 * dw units.
1773 */
1774void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1775{
1776#ifdef __BIG_ENDIAN
1777        u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
1778        u32 *dst32, *src32;
1779        int i;
1780
1781        memcpy(src_tmp, src, num_bytes);
1782        src32 = (u32 *)src_tmp;
1783        dst32 = (u32 *)dst_tmp;
1784        if (to_le) {
1785                for (i = 0; i < ((num_bytes + 3) / 4); i++)
1786                        dst32[i] = cpu_to_le32(src32[i]);
1787                memcpy(dst, dst_tmp, num_bytes);
1788        } else {
1789                u8 dws = num_bytes & ~3;
1790                for (i = 0; i < ((num_bytes + 3) / 4); i++)
1791                        dst32[i] = le32_to_cpu(src32[i]);
1792                memcpy(dst, dst_tmp, dws);
1793                if (num_bytes % 4) {
1794                        for (i = 0; i < (num_bytes % 4); i++)
1795                                dst[dws+i] = dst_tmp[dws+i];
1796                }
1797        }
1798#else
1799        memcpy(dst, src, num_bytes);
1800#endif
1801}
1802
1803int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1804{
1805        struct atom_context *ctx = adev->mode_info.atom_context;
1806        int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1807        uint16_t data_offset;
1808        int usage_bytes = 0;
1809        struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1810
1811        if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1812                firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1813
1814                DRM_DEBUG("atom firmware requested %08x %dkb\n",
1815                          le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1816                          le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1817
1818                usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1819        }
1820        ctx->scratch_size_bytes = 0;
1821        if (usage_bytes == 0)
1822                usage_bytes = 20 * 1024;
1823        /* allocate some scratch memory */
1824        ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1825        if (!ctx->scratch)
1826                return -ENOMEM;
1827        ctx->scratch_size_bytes = usage_bytes;
1828        return 0;
1829}
1830