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12#include <linux/module.h>
13#include <linux/spinlock.h>
14#include <linux/clk.h>
15#include <linux/component.h>
16#include <linux/list.h>
17#include <linux/of_graph.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/pm_runtime.h>
20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_fb_helper.h>
26#include <drm/drm_fb_cma_helper.h>
27#include <drm/drm_gem_cma_helper.h>
28#include <drm/drm_of.h>
29
30#include "hdlcd_drv.h"
31#include "hdlcd_regs.h"
32
33static int hdlcd_load(struct drm_device *drm, unsigned long flags)
34{
35 struct hdlcd_drm_private *hdlcd = drm->dev_private;
36 struct platform_device *pdev = to_platform_device(drm->dev);
37 struct resource *res;
38 u32 version;
39 int ret;
40
41 hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
42 if (IS_ERR(hdlcd->clk))
43 return PTR_ERR(hdlcd->clk);
44
45#ifdef CONFIG_DEBUG_FS
46 atomic_set(&hdlcd->buffer_underrun_count, 0);
47 atomic_set(&hdlcd->bus_error_count, 0);
48 atomic_set(&hdlcd->vsync_count, 0);
49 atomic_set(&hdlcd->dma_end_count, 0);
50#endif
51
52 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53 hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
54 if (IS_ERR(hdlcd->mmio)) {
55 DRM_ERROR("failed to map control registers area\n");
56 ret = PTR_ERR(hdlcd->mmio);
57 hdlcd->mmio = NULL;
58 return ret;
59 }
60
61 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
62 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
63 DRM_ERROR("unknown product id: 0x%x\n", version);
64 return -EINVAL;
65 }
66 DRM_INFO("found ARM HDLCD version r%dp%d\n",
67 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
68 version & HDLCD_VERSION_MINOR_MASK);
69
70
71 ret = of_reserved_mem_device_init(drm->dev);
72 if (ret && ret != -ENODEV)
73 return ret;
74
75 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
76 if (ret)
77 goto setup_fail;
78
79 ret = hdlcd_setup_crtc(drm);
80 if (ret < 0) {
81 DRM_ERROR("failed to create crtc\n");
82 goto setup_fail;
83 }
84
85 ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
86 if (ret < 0) {
87 DRM_ERROR("failed to install IRQ handler\n");
88 goto irq_fail;
89 }
90
91 return 0;
92
93irq_fail:
94 drm_crtc_cleanup(&hdlcd->crtc);
95setup_fail:
96 of_reserved_mem_device_release(drm->dev);
97
98 return ret;
99}
100
101static void hdlcd_fb_output_poll_changed(struct drm_device *drm)
102{
103 struct hdlcd_drm_private *hdlcd = drm->dev_private;
104
105 drm_fbdev_cma_hotplug_event(hdlcd->fbdev);
106}
107
108static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
109 .fb_create = drm_fb_cma_create,
110 .output_poll_changed = hdlcd_fb_output_poll_changed,
111 .atomic_check = drm_atomic_helper_check,
112 .atomic_commit = drm_atomic_helper_commit,
113};
114
115static void hdlcd_setup_mode_config(struct drm_device *drm)
116{
117 drm_mode_config_init(drm);
118 drm->mode_config.min_width = 0;
119 drm->mode_config.min_height = 0;
120 drm->mode_config.max_width = HDLCD_MAX_XRES;
121 drm->mode_config.max_height = HDLCD_MAX_YRES;
122 drm->mode_config.funcs = &hdlcd_mode_config_funcs;
123}
124
125static void hdlcd_lastclose(struct drm_device *drm)
126{
127 struct hdlcd_drm_private *hdlcd = drm->dev_private;
128
129 drm_fbdev_cma_restore_mode(hdlcd->fbdev);
130}
131
132static irqreturn_t hdlcd_irq(int irq, void *arg)
133{
134 struct drm_device *drm = arg;
135 struct hdlcd_drm_private *hdlcd = drm->dev_private;
136 unsigned long irq_status;
137
138 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
139
140#ifdef CONFIG_DEBUG_FS
141 if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
142 atomic_inc(&hdlcd->buffer_underrun_count);
143
144 if (irq_status & HDLCD_INTERRUPT_DMA_END)
145 atomic_inc(&hdlcd->dma_end_count);
146
147 if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
148 atomic_inc(&hdlcd->bus_error_count);
149
150 if (irq_status & HDLCD_INTERRUPT_VSYNC)
151 atomic_inc(&hdlcd->vsync_count);
152
153#endif
154 if (irq_status & HDLCD_INTERRUPT_VSYNC)
155 drm_crtc_handle_vblank(&hdlcd->crtc);
156
157
158 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
159
160 return IRQ_HANDLED;
161}
162
163static void hdlcd_irq_preinstall(struct drm_device *drm)
164{
165 struct hdlcd_drm_private *hdlcd = drm->dev_private;
166
167 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
168 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
169}
170
171static int hdlcd_irq_postinstall(struct drm_device *drm)
172{
173#ifdef CONFIG_DEBUG_FS
174 struct hdlcd_drm_private *hdlcd = drm->dev_private;
175 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
176
177
178 irq_mask |= HDLCD_DEBUG_INT_MASK;
179
180 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
181#endif
182 return 0;
183}
184
185static void hdlcd_irq_uninstall(struct drm_device *drm)
186{
187 struct hdlcd_drm_private *hdlcd = drm->dev_private;
188
189 unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
190
191#ifdef CONFIG_DEBUG_FS
192
193 irq_mask &= ~HDLCD_DEBUG_INT_MASK;
194#endif
195
196
197 irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
198
199 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
200}
201
202#ifdef CONFIG_DEBUG_FS
203static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
204{
205 struct drm_info_node *node = (struct drm_info_node *)m->private;
206 struct drm_device *drm = node->minor->dev;
207 struct hdlcd_drm_private *hdlcd = drm->dev_private;
208
209 seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
210 seq_printf(m, "dma_end : %d\n", atomic_read(&hdlcd->dma_end_count));
211 seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
212 seq_printf(m, "vsync : %d\n", atomic_read(&hdlcd->vsync_count));
213 return 0;
214}
215
216static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
217{
218 struct drm_info_node *node = (struct drm_info_node *)m->private;
219 struct drm_device *drm = node->minor->dev;
220 struct hdlcd_drm_private *hdlcd = drm->dev_private;
221 unsigned long clkrate = clk_get_rate(hdlcd->clk);
222 unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
223
224 seq_printf(m, "hw : %lu\n", clkrate);
225 seq_printf(m, "mode: %lu\n", mode_clock);
226 return 0;
227}
228
229static struct drm_info_list hdlcd_debugfs_list[] = {
230 { "interrupt_count", hdlcd_show_underrun_count, 0 },
231 { "clocks", hdlcd_show_pxlclock, 0 },
232 { "fb", drm_fb_cma_debugfs_show, 0 },
233};
234
235static int hdlcd_debugfs_init(struct drm_minor *minor)
236{
237 return drm_debugfs_create_files(hdlcd_debugfs_list,
238 ARRAY_SIZE(hdlcd_debugfs_list), minor->debugfs_root, minor);
239}
240#endif
241
242DEFINE_DRM_GEM_CMA_FOPS(fops);
243
244static struct drm_driver hdlcd_driver = {
245 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
246 DRIVER_MODESET | DRIVER_PRIME |
247 DRIVER_ATOMIC,
248 .lastclose = hdlcd_lastclose,
249 .irq_handler = hdlcd_irq,
250 .irq_preinstall = hdlcd_irq_preinstall,
251 .irq_postinstall = hdlcd_irq_postinstall,
252 .irq_uninstall = hdlcd_irq_uninstall,
253 .gem_free_object_unlocked = drm_gem_cma_free_object,
254 .gem_vm_ops = &drm_gem_cma_vm_ops,
255 .dumb_create = drm_gem_cma_dumb_create,
256 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
257 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
258 .gem_prime_export = drm_gem_prime_export,
259 .gem_prime_import = drm_gem_prime_import,
260 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
261 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
262 .gem_prime_vmap = drm_gem_cma_prime_vmap,
263 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
264 .gem_prime_mmap = drm_gem_cma_prime_mmap,
265#ifdef CONFIG_DEBUG_FS
266 .debugfs_init = hdlcd_debugfs_init,
267#endif
268 .fops = &fops,
269 .name = "hdlcd",
270 .desc = "ARM HDLCD Controller DRM",
271 .date = "20151021",
272 .major = 1,
273 .minor = 0,
274};
275
276static int hdlcd_drm_bind(struct device *dev)
277{
278 struct drm_device *drm;
279 struct hdlcd_drm_private *hdlcd;
280 int ret;
281
282 hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
283 if (!hdlcd)
284 return -ENOMEM;
285
286 drm = drm_dev_alloc(&hdlcd_driver, dev);
287 if (IS_ERR(drm))
288 return PTR_ERR(drm);
289
290 drm->dev_private = hdlcd;
291 dev_set_drvdata(dev, drm);
292
293 hdlcd_setup_mode_config(drm);
294 ret = hdlcd_load(drm, 0);
295 if (ret)
296 goto err_free;
297
298
299 hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
300
301 ret = component_bind_all(dev, drm);
302 if (ret) {
303 DRM_ERROR("Failed to bind all components\n");
304 goto err_unload;
305 }
306
307 ret = pm_runtime_set_active(dev);
308 if (ret)
309 goto err_pm_active;
310
311 pm_runtime_enable(dev);
312
313 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
314 if (ret < 0) {
315 DRM_ERROR("failed to initialise vblank\n");
316 goto err_vblank;
317 }
318
319 drm_mode_config_reset(drm);
320 drm_kms_helper_poll_init(drm);
321
322 hdlcd->fbdev = drm_fbdev_cma_init(drm, 32,
323 drm->mode_config.num_connector);
324
325 if (IS_ERR(hdlcd->fbdev)) {
326 ret = PTR_ERR(hdlcd->fbdev);
327 hdlcd->fbdev = NULL;
328 goto err_fbdev;
329 }
330
331 ret = drm_dev_register(drm, 0);
332 if (ret)
333 goto err_register;
334
335 return 0;
336
337err_register:
338 if (hdlcd->fbdev) {
339 drm_fbdev_cma_fini(hdlcd->fbdev);
340 hdlcd->fbdev = NULL;
341 }
342err_fbdev:
343 drm_kms_helper_poll_fini(drm);
344err_vblank:
345 pm_runtime_disable(drm->dev);
346err_pm_active:
347 component_unbind_all(dev, drm);
348err_unload:
349 of_node_put(hdlcd->crtc.port);
350 hdlcd->crtc.port = NULL;
351 drm_irq_uninstall(drm);
352 of_reserved_mem_device_release(drm->dev);
353err_free:
354 drm_mode_config_cleanup(drm);
355 dev_set_drvdata(dev, NULL);
356 drm_dev_unref(drm);
357
358 return ret;
359}
360
361static void hdlcd_drm_unbind(struct device *dev)
362{
363 struct drm_device *drm = dev_get_drvdata(dev);
364 struct hdlcd_drm_private *hdlcd = drm->dev_private;
365
366 drm_dev_unregister(drm);
367 if (hdlcd->fbdev) {
368 drm_fbdev_cma_fini(hdlcd->fbdev);
369 hdlcd->fbdev = NULL;
370 }
371 drm_kms_helper_poll_fini(drm);
372 component_unbind_all(dev, drm);
373 of_node_put(hdlcd->crtc.port);
374 hdlcd->crtc.port = NULL;
375 pm_runtime_get_sync(drm->dev);
376 drm_irq_uninstall(drm);
377 pm_runtime_put_sync(drm->dev);
378 pm_runtime_disable(drm->dev);
379 of_reserved_mem_device_release(drm->dev);
380 drm_mode_config_cleanup(drm);
381 drm_dev_unref(drm);
382 drm->dev_private = NULL;
383 dev_set_drvdata(dev, NULL);
384}
385
386static const struct component_master_ops hdlcd_master_ops = {
387 .bind = hdlcd_drm_bind,
388 .unbind = hdlcd_drm_unbind,
389};
390
391static int compare_dev(struct device *dev, void *data)
392{
393 return dev->of_node == data;
394}
395
396static int hdlcd_probe(struct platform_device *pdev)
397{
398 struct device_node *port;
399 struct component_match *match = NULL;
400
401
402 port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
403 if (!port)
404 return -ENODEV;
405
406 drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
407 of_node_put(port);
408
409 return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
410 match);
411}
412
413static int hdlcd_remove(struct platform_device *pdev)
414{
415 component_master_del(&pdev->dev, &hdlcd_master_ops);
416 return 0;
417}
418
419static const struct of_device_id hdlcd_of_match[] = {
420 { .compatible = "arm,hdlcd" },
421 {},
422};
423MODULE_DEVICE_TABLE(of, hdlcd_of_match);
424
425static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
426{
427 struct drm_device *drm = dev_get_drvdata(dev);
428 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
429
430 if (!hdlcd)
431 return 0;
432
433 drm_kms_helper_poll_disable(drm);
434
435 hdlcd->state = drm_atomic_helper_suspend(drm);
436 if (IS_ERR(hdlcd->state)) {
437 drm_kms_helper_poll_enable(drm);
438 return PTR_ERR(hdlcd->state);
439 }
440
441 return 0;
442}
443
444static int __maybe_unused hdlcd_pm_resume(struct device *dev)
445{
446 struct drm_device *drm = dev_get_drvdata(dev);
447 struct hdlcd_drm_private *hdlcd = drm ? drm->dev_private : NULL;
448
449 if (!hdlcd)
450 return 0;
451
452 drm_atomic_helper_resume(drm, hdlcd->state);
453 drm_kms_helper_poll_enable(drm);
454 pm_runtime_set_active(dev);
455
456 return 0;
457}
458
459static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
460
461static struct platform_driver hdlcd_platform_driver = {
462 .probe = hdlcd_probe,
463 .remove = hdlcd_remove,
464 .driver = {
465 .name = "hdlcd",
466 .pm = &hdlcd_pm_ops,
467 .of_match_table = hdlcd_of_match,
468 },
469};
470
471module_platform_driver(hdlcd_platform_driver);
472
473MODULE_AUTHOR("Liviu Dudau");
474MODULE_DESCRIPTION("ARM HDLCD DRM driver");
475MODULE_LICENSE("GPL v2");
476
