linux/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
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   1/*
   2 * Copyright (C) 2013 Red Hat
   3 * Author: Rob Clark <robdclark@gmail.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18
  19#include "msm_drv.h"
  20#include "msm_gem.h"
  21#include "msm_mmu.h"
  22#include "mdp4_kms.h"
  23
  24static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  25
  26static int mdp4_hw_init(struct msm_kms *kms)
  27{
  28        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  29        struct drm_device *dev = mdp4_kms->dev;
  30        uint32_t version, major, minor, dmap_cfg, vg_cfg;
  31        unsigned long clk;
  32        int ret = 0;
  33
  34        pm_runtime_get_sync(dev->dev);
  35
  36        mdp4_enable(mdp4_kms);
  37        version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  38        mdp4_disable(mdp4_kms);
  39
  40        major = FIELD(version, MDP4_VERSION_MAJOR);
  41        minor = FIELD(version, MDP4_VERSION_MINOR);
  42
  43        DBG("found MDP4 version v%d.%d", major, minor);
  44
  45        if (major != 4) {
  46                dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  47                                major, minor);
  48                ret = -ENXIO;
  49                goto out;
  50        }
  51
  52        mdp4_kms->rev = minor;
  53
  54        if (mdp4_kms->rev > 1) {
  55                mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  56                mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  57        }
  58
  59        mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  60
  61        /* max read pending cmd config, 3 pending requests: */
  62        mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  63
  64        clk = clk_get_rate(mdp4_kms->clk);
  65
  66        if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  67                dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  68                vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  69        } else {
  70                dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  71                vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  72        }
  73
  74        DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  75
  76        mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  77        mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  78
  79        mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
  80        mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
  81        mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
  82        mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
  83
  84        if (mdp4_kms->rev >= 2)
  85                mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
  86        mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
  87
  88        /* disable CSC matrix / YUV by default: */
  89        mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
  90        mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
  91        mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
  92        mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
  93        mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
  94        mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
  95
  96        if (mdp4_kms->rev > 1)
  97                mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
  98
  99        dev->mode_config.allow_fb_modifiers = true;
 100
 101out:
 102        pm_runtime_put_sync(dev->dev);
 103
 104        return ret;
 105}
 106
 107static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 108{
 109        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 110        int i;
 111        struct drm_crtc *crtc;
 112        struct drm_crtc_state *crtc_state;
 113
 114        mdp4_enable(mdp4_kms);
 115
 116        /* see 119ecb7fd */
 117        for_each_new_crtc_in_state(state, crtc, crtc_state, i)
 118                drm_crtc_vblank_get(crtc);
 119}
 120
 121static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 122{
 123        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 124        int i;
 125        struct drm_crtc *crtc;
 126        struct drm_crtc_state *crtc_state;
 127
 128        /* see 119ecb7fd */
 129        for_each_new_crtc_in_state(state, crtc, crtc_state, i)
 130                drm_crtc_vblank_put(crtc);
 131
 132        mdp4_disable(mdp4_kms);
 133}
 134
 135static void mdp4_wait_for_crtc_commit_done(struct msm_kms *kms,
 136                                                struct drm_crtc *crtc)
 137{
 138        mdp4_crtc_wait_for_commit_done(crtc);
 139}
 140
 141static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 142                struct drm_encoder *encoder)
 143{
 144        /* if we had >1 encoder, we'd need something more clever: */
 145        switch (encoder->encoder_type) {
 146        case DRM_MODE_ENCODER_TMDS:
 147                return mdp4_dtv_round_pixclk(encoder, rate);
 148        case DRM_MODE_ENCODER_LVDS:
 149        case DRM_MODE_ENCODER_DSI:
 150        default:
 151                return rate;
 152        }
 153}
 154
 155static const char * const iommu_ports[] = {
 156        "mdp_port0_cb0", "mdp_port1_cb0",
 157};
 158
 159static void mdp4_destroy(struct msm_kms *kms)
 160{
 161        struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 162        struct device *dev = mdp4_kms->dev->dev;
 163        struct msm_gem_address_space *aspace = kms->aspace;
 164
 165        if (mdp4_kms->blank_cursor_iova)
 166                msm_gem_put_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
 167        drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
 168
 169        if (aspace) {
 170                aspace->mmu->funcs->detach(aspace->mmu,
 171                                iommu_ports, ARRAY_SIZE(iommu_ports));
 172                msm_gem_address_space_put(aspace);
 173        }
 174
 175        if (mdp4_kms->rpm_enabled)
 176                pm_runtime_disable(dev);
 177
 178        kfree(mdp4_kms);
 179}
 180
 181static const struct mdp_kms_funcs kms_funcs = {
 182        .base = {
 183                .hw_init         = mdp4_hw_init,
 184                .irq_preinstall  = mdp4_irq_preinstall,
 185                .irq_postinstall = mdp4_irq_postinstall,
 186                .irq_uninstall   = mdp4_irq_uninstall,
 187                .irq             = mdp4_irq,
 188                .enable_vblank   = mdp4_enable_vblank,
 189                .disable_vblank  = mdp4_disable_vblank,
 190                .prepare_commit  = mdp4_prepare_commit,
 191                .complete_commit = mdp4_complete_commit,
 192                .wait_for_crtc_commit_done = mdp4_wait_for_crtc_commit_done,
 193                .get_format      = mdp_get_format,
 194                .round_pixclk    = mdp4_round_pixclk,
 195                .destroy         = mdp4_destroy,
 196        },
 197        .set_irqmask         = mdp4_set_irqmask,
 198};
 199
 200int mdp4_disable(struct mdp4_kms *mdp4_kms)
 201{
 202        DBG("");
 203
 204        clk_disable_unprepare(mdp4_kms->clk);
 205        if (mdp4_kms->pclk)
 206                clk_disable_unprepare(mdp4_kms->pclk);
 207        clk_disable_unprepare(mdp4_kms->lut_clk);
 208        if (mdp4_kms->axi_clk)
 209                clk_disable_unprepare(mdp4_kms->axi_clk);
 210
 211        return 0;
 212}
 213
 214int mdp4_enable(struct mdp4_kms *mdp4_kms)
 215{
 216        DBG("");
 217
 218        clk_prepare_enable(mdp4_kms->clk);
 219        if (mdp4_kms->pclk)
 220                clk_prepare_enable(mdp4_kms->pclk);
 221        clk_prepare_enable(mdp4_kms->lut_clk);
 222        if (mdp4_kms->axi_clk)
 223                clk_prepare_enable(mdp4_kms->axi_clk);
 224
 225        return 0;
 226}
 227
 228
 229static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
 230                                  int intf_type)
 231{
 232        struct drm_device *dev = mdp4_kms->dev;
 233        struct msm_drm_private *priv = dev->dev_private;
 234        struct drm_encoder *encoder;
 235        struct drm_connector *connector;
 236        struct device_node *panel_node;
 237        int dsi_id;
 238        int ret;
 239
 240        switch (intf_type) {
 241        case DRM_MODE_ENCODER_LVDS:
 242                /*
 243                 * bail out early if there is no panel node (no need to
 244                 * initialize LCDC encoder and LVDS connector)
 245                 */
 246                panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
 247                if (!panel_node)
 248                        return 0;
 249
 250                encoder = mdp4_lcdc_encoder_init(dev, panel_node);
 251                if (IS_ERR(encoder)) {
 252                        dev_err(dev->dev, "failed to construct LCDC encoder\n");
 253                        return PTR_ERR(encoder);
 254                }
 255
 256                /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
 257                encoder->possible_crtcs = 1 << DMA_P;
 258
 259                connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
 260                if (IS_ERR(connector)) {
 261                        dev_err(dev->dev, "failed to initialize LVDS connector\n");
 262                        return PTR_ERR(connector);
 263                }
 264
 265                priv->encoders[priv->num_encoders++] = encoder;
 266                priv->connectors[priv->num_connectors++] = connector;
 267
 268                break;
 269        case DRM_MODE_ENCODER_TMDS:
 270                encoder = mdp4_dtv_encoder_init(dev);
 271                if (IS_ERR(encoder)) {
 272                        dev_err(dev->dev, "failed to construct DTV encoder\n");
 273                        return PTR_ERR(encoder);
 274                }
 275
 276                /* DTV can be hooked to DMA_E: */
 277                encoder->possible_crtcs = 1 << 1;
 278
 279                if (priv->hdmi) {
 280                        /* Construct bridge/connector for HDMI: */
 281                        ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 282                        if (ret) {
 283                                dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
 284                                return ret;
 285                        }
 286                }
 287
 288                priv->encoders[priv->num_encoders++] = encoder;
 289
 290                break;
 291        case DRM_MODE_ENCODER_DSI:
 292                /* only DSI1 supported for now */
 293                dsi_id = 0;
 294
 295                if (!priv->dsi[dsi_id])
 296                        break;
 297
 298                encoder = mdp4_dsi_encoder_init(dev);
 299                if (IS_ERR(encoder)) {
 300                        ret = PTR_ERR(encoder);
 301                        dev_err(dev->dev,
 302                                "failed to construct DSI encoder: %d\n", ret);
 303                        return ret;
 304                }
 305
 306                /* TODO: Add DMA_S later? */
 307                encoder->possible_crtcs = 1 << DMA_P;
 308                priv->encoders[priv->num_encoders++] = encoder;
 309
 310                ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
 311                if (ret) {
 312                        dev_err(dev->dev, "failed to initialize DSI: %d\n",
 313                                ret);
 314                        return ret;
 315                }
 316
 317                break;
 318        default:
 319                dev_err(dev->dev, "Invalid or unsupported interface\n");
 320                return -EINVAL;
 321        }
 322
 323        return 0;
 324}
 325
 326static int modeset_init(struct mdp4_kms *mdp4_kms)
 327{
 328        struct drm_device *dev = mdp4_kms->dev;
 329        struct msm_drm_private *priv = dev->dev_private;
 330        struct drm_plane *plane;
 331        struct drm_crtc *crtc;
 332        int i, ret;
 333        static const enum mdp4_pipe rgb_planes[] = {
 334                RGB1, RGB2,
 335        };
 336        static const enum mdp4_pipe vg_planes[] = {
 337                VG1, VG2,
 338        };
 339        static const enum mdp4_dma mdp4_crtcs[] = {
 340                DMA_P, DMA_E,
 341        };
 342        static const char * const mdp4_crtc_names[] = {
 343                "DMA_P", "DMA_E",
 344        };
 345        static const int mdp4_intfs[] = {
 346                DRM_MODE_ENCODER_LVDS,
 347                DRM_MODE_ENCODER_DSI,
 348                DRM_MODE_ENCODER_TMDS,
 349        };
 350
 351        /* construct non-private planes: */
 352        for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
 353                plane = mdp4_plane_init(dev, vg_planes[i], false);
 354                if (IS_ERR(plane)) {
 355                        dev_err(dev->dev,
 356                                "failed to construct plane for VG%d\n", i + 1);
 357                        ret = PTR_ERR(plane);
 358                        goto fail;
 359                }
 360                priv->planes[priv->num_planes++] = plane;
 361        }
 362
 363        for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
 364                plane = mdp4_plane_init(dev, rgb_planes[i], true);
 365                if (IS_ERR(plane)) {
 366                        dev_err(dev->dev,
 367                                "failed to construct plane for RGB%d\n", i + 1);
 368                        ret = PTR_ERR(plane);
 369                        goto fail;
 370                }
 371
 372                crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
 373                                mdp4_crtcs[i]);
 374                if (IS_ERR(crtc)) {
 375                        dev_err(dev->dev, "failed to construct crtc for %s\n",
 376                                mdp4_crtc_names[i]);
 377                        ret = PTR_ERR(crtc);
 378                        goto fail;
 379                }
 380
 381                priv->crtcs[priv->num_crtcs++] = crtc;
 382        }
 383
 384        /*
 385         * we currently set up two relatively fixed paths:
 386         *
 387         * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
 388         *                      or
 389         * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
 390         *
 391         * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
 392         */
 393
 394        for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
 395                ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
 396                if (ret) {
 397                        dev_err(dev->dev, "failed to initialize intf: %d, %d\n",
 398                                i, ret);
 399                        goto fail;
 400                }
 401        }
 402
 403        return 0;
 404
 405fail:
 406        return ret;
 407}
 408
 409struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 410{
 411        struct platform_device *pdev = to_platform_device(dev->dev);
 412        struct mdp4_platform_config *config = mdp4_get_config(pdev);
 413        struct mdp4_kms *mdp4_kms;
 414        struct msm_kms *kms = NULL;
 415        struct msm_gem_address_space *aspace;
 416        int irq, ret;
 417
 418        mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 419        if (!mdp4_kms) {
 420                dev_err(dev->dev, "failed to allocate kms\n");
 421                ret = -ENOMEM;
 422                goto fail;
 423        }
 424
 425        mdp_kms_init(&mdp4_kms->base, &kms_funcs);
 426
 427        kms = &mdp4_kms->base.base;
 428
 429        mdp4_kms->dev = dev;
 430
 431        mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 432        if (IS_ERR(mdp4_kms->mmio)) {
 433                ret = PTR_ERR(mdp4_kms->mmio);
 434                goto fail;
 435        }
 436
 437        irq = platform_get_irq(pdev, 0);
 438        if (irq < 0) {
 439                ret = irq;
 440                dev_err(dev->dev, "failed to get irq: %d\n", ret);
 441                goto fail;
 442        }
 443
 444        kms->irq = irq;
 445
 446        /* NOTE: driver for this regulator still missing upstream.. use
 447         * _get_exclusive() and ignore the error if it does not exist
 448         * (and hope that the bootloader left it on for us)
 449         */
 450        mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
 451        if (IS_ERR(mdp4_kms->vdd))
 452                mdp4_kms->vdd = NULL;
 453
 454        if (mdp4_kms->vdd) {
 455                ret = regulator_enable(mdp4_kms->vdd);
 456                if (ret) {
 457                        dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 458                        goto fail;
 459                }
 460        }
 461
 462        mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 463        if (IS_ERR(mdp4_kms->clk)) {
 464                dev_err(dev->dev, "failed to get core_clk\n");
 465                ret = PTR_ERR(mdp4_kms->clk);
 466                goto fail;
 467        }
 468
 469        mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 470        if (IS_ERR(mdp4_kms->pclk))
 471                mdp4_kms->pclk = NULL;
 472
 473        // XXX if (rev >= MDP_REV_42) { ???
 474        mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 475        if (IS_ERR(mdp4_kms->lut_clk)) {
 476                dev_err(dev->dev, "failed to get lut_clk\n");
 477                ret = PTR_ERR(mdp4_kms->lut_clk);
 478                goto fail;
 479        }
 480
 481        mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
 482        if (IS_ERR(mdp4_kms->axi_clk)) {
 483                dev_err(dev->dev, "failed to get axi_clk\n");
 484                ret = PTR_ERR(mdp4_kms->axi_clk);
 485                goto fail;
 486        }
 487
 488        clk_set_rate(mdp4_kms->clk, config->max_clk);
 489        clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 490
 491        pm_runtime_enable(dev->dev);
 492        mdp4_kms->rpm_enabled = true;
 493
 494        /* make sure things are off before attaching iommu (bootloader could
 495         * have left things on, in which case we'll start getting faults if
 496         * we don't disable):
 497         */
 498        mdp4_enable(mdp4_kms);
 499        mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 500        mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 501        mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 502        mdp4_disable(mdp4_kms);
 503        mdelay(16);
 504
 505        if (config->iommu) {
 506                aspace = msm_gem_address_space_create(&pdev->dev,
 507                                config->iommu, "mdp4");
 508                if (IS_ERR(aspace)) {
 509                        ret = PTR_ERR(aspace);
 510                        goto fail;
 511                }
 512
 513                kms->aspace = aspace;
 514
 515                ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
 516                                ARRAY_SIZE(iommu_ports));
 517                if (ret)
 518                        goto fail;
 519        } else {
 520                dev_info(dev->dev, "no iommu, fallback to phys "
 521                                "contig buffers for scanout\n");
 522                aspace = NULL;
 523        }
 524
 525        ret = modeset_init(mdp4_kms);
 526        if (ret) {
 527                dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 528                goto fail;
 529        }
 530
 531        mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
 532        if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
 533                ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
 534                dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
 535                mdp4_kms->blank_cursor_bo = NULL;
 536                goto fail;
 537        }
 538
 539        ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
 540                        &mdp4_kms->blank_cursor_iova);
 541        if (ret) {
 542                dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
 543                goto fail;
 544        }
 545
 546        dev->mode_config.min_width = 0;
 547        dev->mode_config.min_height = 0;
 548        dev->mode_config.max_width = 2048;
 549        dev->mode_config.max_height = 2048;
 550
 551        return kms;
 552
 553fail:
 554        if (kms)
 555                mdp4_destroy(kms);
 556        return ERR_PTR(ret);
 557}
 558
 559static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 560{
 561        static struct mdp4_platform_config config = {};
 562
 563        /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
 564        config.max_clk = 266667000;
 565        config.iommu = iommu_domain_alloc(&platform_bus_type);
 566        if (config.iommu) {
 567                config.iommu->geometry.aperture_start = 0x1000;
 568                config.iommu->geometry.aperture_end = 0xffffffff;
 569        }
 570
 571        return &config;
 572}
 573