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10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/gpio.h>
13#include <linux/hdmi.h>
14#include <linux/pm_runtime.h>
15#include <linux/regulator/consumer.h>
16#include <linux/reset.h>
17
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_crtc.h>
20#include <drm/drm_crtc_helper.h>
21
22#include <sound/hda_verbs.h>
23
24#include "hdmi.h"
25#include "drm.h"
26#include "dc.h"
27#include "trace.h"
28
29#define HDMI_ELD_BUFFER_SIZE 96
30
31struct tmds_config {
32 unsigned int pclk;
33 u32 pll0;
34 u32 pll1;
35 u32 pe_current;
36 u32 drive_current;
37 u32 peak_current;
38};
39
40struct tegra_hdmi_config {
41 const struct tmds_config *tmds;
42 unsigned int num_tmds;
43
44 unsigned long fuse_override_offset;
45 u32 fuse_override_value;
46
47 bool has_sor_io_peak_current;
48 bool has_hda;
49 bool has_hbr;
50};
51
52struct tegra_hdmi {
53 struct host1x_client client;
54 struct tegra_output output;
55 struct device *dev;
56
57 struct regulator *hdmi;
58 struct regulator *pll;
59 struct regulator *vdd;
60
61 void __iomem *regs;
62 unsigned int irq;
63
64 struct clk *clk_parent;
65 struct clk *clk;
66 struct reset_control *rst;
67
68 const struct tegra_hdmi_config *config;
69
70 unsigned int audio_source;
71 unsigned int audio_sample_rate;
72 unsigned int audio_channels;
73
74 unsigned int pixel_clock;
75 bool stereo;
76 bool dvi;
77
78 struct drm_info_list *debugfs_files;
79 struct drm_minor *minor;
80 struct dentry *debugfs;
81};
82
83static inline struct tegra_hdmi *
84host1x_client_to_hdmi(struct host1x_client *client)
85{
86 return container_of(client, struct tegra_hdmi, client);
87}
88
89static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
90{
91 return container_of(output, struct tegra_hdmi, output);
92}
93
94#define HDMI_AUDIOCLK_FREQ 216000000
95#define HDMI_REKEY_DEFAULT 56
96
97enum {
98 AUTO = 0,
99 SPDIF,
100 HDA,
101};
102
103static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
104 unsigned int offset)
105{
106 u32 value = readl(hdmi->regs + (offset << 2));
107
108 trace_hdmi_readl(hdmi->dev, offset, value);
109
110 return value;
111}
112
113static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
114 unsigned int offset)
115{
116 trace_hdmi_writel(hdmi->dev, offset, value);
117 writel(value, hdmi->regs + (offset << 2));
118}
119
120struct tegra_hdmi_audio_config {
121 unsigned int pclk;
122 unsigned int n;
123 unsigned int cts;
124 unsigned int aval;
125};
126
127static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
128 { 25200000, 4096, 25200, 24000 },
129 { 27000000, 4096, 27000, 24000 },
130 { 74250000, 4096, 74250, 24000 },
131 { 148500000, 4096, 148500, 24000 },
132 { 0, 0, 0, 0 },
133};
134
135static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
136 { 25200000, 5880, 26250, 25000 },
137 { 27000000, 5880, 28125, 25000 },
138 { 74250000, 4704, 61875, 20000 },
139 { 148500000, 4704, 123750, 20000 },
140 { 0, 0, 0, 0 },
141};
142
143static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
144 { 25200000, 6144, 25200, 24000 },
145 { 27000000, 6144, 27000, 24000 },
146 { 74250000, 6144, 74250, 24000 },
147 { 148500000, 6144, 148500, 24000 },
148 { 0, 0, 0, 0 },
149};
150
151static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
152 { 25200000, 11760, 26250, 25000 },
153 { 27000000, 11760, 28125, 25000 },
154 { 74250000, 9408, 61875, 20000 },
155 { 148500000, 9408, 123750, 20000 },
156 { 0, 0, 0, 0 },
157};
158
159static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
160 { 25200000, 12288, 25200, 24000 },
161 { 27000000, 12288, 27000, 24000 },
162 { 74250000, 12288, 74250, 24000 },
163 { 148500000, 12288, 148500, 24000 },
164 { 0, 0, 0, 0 },
165};
166
167static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
168 { 25200000, 23520, 26250, 25000 },
169 { 27000000, 23520, 28125, 25000 },
170 { 74250000, 18816, 61875, 20000 },
171 { 148500000, 18816, 123750, 20000 },
172 { 0, 0, 0, 0 },
173};
174
175static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
176 { 25200000, 24576, 25200, 24000 },
177 { 27000000, 24576, 27000, 24000 },
178 { 74250000, 24576, 74250, 24000 },
179 { 148500000, 24576, 148500, 24000 },
180 { 0, 0, 0, 0 },
181};
182
183static const struct tmds_config tegra20_tmds_config[] = {
184 {
185 .pclk = 27000000,
186 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
188 SOR_PLL_TX_REG_LOAD(3),
189 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
190 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
191 PE_CURRENT1(PE_CURRENT_0_0_mA) |
192 PE_CURRENT2(PE_CURRENT_0_0_mA) |
193 PE_CURRENT3(PE_CURRENT_0_0_mA),
194 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
195 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
196 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
197 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
198 },
199 {
200 .pclk = UINT_MAX,
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
202 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
203 SOR_PLL_TX_REG_LOAD(3),
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
205 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
206 PE_CURRENT1(PE_CURRENT_6_0_mA) |
207 PE_CURRENT2(PE_CURRENT_6_0_mA) |
208 PE_CURRENT3(PE_CURRENT_6_0_mA),
209 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
210 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
211 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
212 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
213 },
214};
215
216static const struct tmds_config tegra30_tmds_config[] = {
217 {
218 .pclk = 27000000,
219 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
220 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
221 SOR_PLL_TX_REG_LOAD(0),
222 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
223 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
224 PE_CURRENT1(PE_CURRENT_0_0_mA) |
225 PE_CURRENT2(PE_CURRENT_0_0_mA) |
226 PE_CURRENT3(PE_CURRENT_0_0_mA),
227 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
228 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
229 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
230 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
231 }, {
232 .pclk = 74250000,
233 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
234 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
235 SOR_PLL_TX_REG_LOAD(0),
236 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
237 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
238 PE_CURRENT1(PE_CURRENT_5_0_mA) |
239 PE_CURRENT2(PE_CURRENT_5_0_mA) |
240 PE_CURRENT3(PE_CURRENT_5_0_mA),
241 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
242 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
243 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
244 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
245 }, {
246 .pclk = UINT_MAX,
247 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
248 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
249 SOR_PLL_TX_REG_LOAD(0),
250 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
251 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
252 PE_CURRENT1(PE_CURRENT_5_0_mA) |
253 PE_CURRENT2(PE_CURRENT_5_0_mA) |
254 PE_CURRENT3(PE_CURRENT_5_0_mA),
255 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
256 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
257 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
258 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
259 },
260};
261
262static const struct tmds_config tegra114_tmds_config[] = {
263 {
264 .pclk = 27000000,
265 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
266 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
267 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
268 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
269 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
270 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
271 PE_CURRENT3(PE_CURRENT_0_mA_T114),
272 .drive_current =
273 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
274 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
275 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
276 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
277 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
278 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
279 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
280 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
281 }, {
282 .pclk = 74250000,
283 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
284 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
285 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
286 SOR_PLL_TMDS_TERMADJ(0),
287 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
288 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
289 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
290 PE_CURRENT3(PE_CURRENT_15_mA_T114),
291 .drive_current =
292 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
293 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
294 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
295 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
296 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
297 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
298 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
299 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
300 }, {
301 .pclk = 148500000,
302 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
303 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
304 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
305 SOR_PLL_TMDS_TERMADJ(0),
306 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
307 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
308 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
309 PE_CURRENT3(PE_CURRENT_10_mA_T114),
310 .drive_current =
311 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
312 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
313 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
314 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
315 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
316 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
317 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
318 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
319 }, {
320 .pclk = UINT_MAX,
321 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
322 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
323 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
324 | SOR_PLL_TMDS_TERM_ENABLE,
325 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
326 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
327 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
328 PE_CURRENT3(PE_CURRENT_0_mA_T114),
329 .drive_current =
330 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
331 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
332 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
333 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
334 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
335 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
336 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
337 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
338 },
339};
340
341static const struct tmds_config tegra124_tmds_config[] = {
342 {
343 .pclk = 27000000,
344 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
345 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
346 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
347 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
348 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
349 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
350 PE_CURRENT3(PE_CURRENT_0_mA_T114),
351 .drive_current =
352 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
353 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
354 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
355 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
356 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
357 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
358 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
359 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
360 }, {
361 .pclk = 74250000,
362 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
363 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
364 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
365 SOR_PLL_TMDS_TERMADJ(0),
366 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
367 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
368 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
369 PE_CURRENT3(PE_CURRENT_15_mA_T114),
370 .drive_current =
371 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
372 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
373 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
374 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
375 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
376 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
377 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
378 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
379 }, {
380 .pclk = 148500000,
381 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
382 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
383 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
384 SOR_PLL_TMDS_TERMADJ(0),
385 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
386 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
387 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
388 PE_CURRENT3(PE_CURRENT_10_mA_T114),
389 .drive_current =
390 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
391 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
392 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
393 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
394 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
395 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
396 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
397 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
398 }, {
399 .pclk = UINT_MAX,
400 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
401 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
402 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
403 | SOR_PLL_TMDS_TERM_ENABLE,
404 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
405 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
406 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
407 PE_CURRENT3(PE_CURRENT_0_mA_T114),
408 .drive_current =
409 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
410 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
411 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
412 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
413 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
414 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
415 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
416 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
417 },
418};
419
420static const struct tegra_hdmi_audio_config *
421tegra_hdmi_get_audio_config(unsigned int sample_rate, unsigned int pclk)
422{
423 const struct tegra_hdmi_audio_config *table;
424
425 switch (sample_rate) {
426 case 32000:
427 table = tegra_hdmi_audio_32k;
428 break;
429
430 case 44100:
431 table = tegra_hdmi_audio_44_1k;
432 break;
433
434 case 48000:
435 table = tegra_hdmi_audio_48k;
436 break;
437
438 case 88200:
439 table = tegra_hdmi_audio_88_2k;
440 break;
441
442 case 96000:
443 table = tegra_hdmi_audio_96k;
444 break;
445
446 case 176400:
447 table = tegra_hdmi_audio_176_4k;
448 break;
449
450 case 192000:
451 table = tegra_hdmi_audio_192k;
452 break;
453
454 default:
455 return NULL;
456 }
457
458 while (table->pclk) {
459 if (table->pclk == pclk)
460 return table;
461
462 table++;
463 }
464
465 return NULL;
466}
467
468static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
469{
470 const unsigned int freqs[] = {
471 32000, 44100, 48000, 88200, 96000, 176400, 192000
472 };
473 unsigned int i;
474
475 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
476 unsigned int f = freqs[i];
477 unsigned int eight_half;
478 unsigned int delta;
479 u32 value;
480
481 if (f > 96000)
482 delta = 2;
483 else if (f > 48000)
484 delta = 6;
485 else
486 delta = 9;
487
488 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
489 value = AUDIO_FS_LOW(eight_half - delta) |
490 AUDIO_FS_HIGH(eight_half + delta);
491 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
492 }
493}
494
495static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
496{
497 static const struct {
498 unsigned int sample_rate;
499 unsigned int offset;
500 } regs[] = {
501 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
502 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
503 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
504 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
505 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
506 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
507 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
508 };
509 unsigned int i;
510
511 for (i = 0; i < ARRAY_SIZE(regs); i++) {
512 if (regs[i].sample_rate == hdmi->audio_sample_rate) {
513 tegra_hdmi_writel(hdmi, value, regs[i].offset);
514 break;
515 }
516 }
517}
518
519static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
520{
521 const struct tegra_hdmi_audio_config *config;
522 u32 source, value;
523
524 switch (hdmi->audio_source) {
525 case HDA:
526 if (hdmi->config->has_hda)
527 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
528 else
529 return -EINVAL;
530
531 break;
532
533 case SPDIF:
534 if (hdmi->config->has_hda)
535 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
536 else
537 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
538 break;
539
540 default:
541 if (hdmi->config->has_hda)
542 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
543 else
544 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
545 break;
546 }
547
548
549
550
551
552
553
554
555 if (hdmi->config->has_hda) {
556
557
558
559
560
561
562
563
564
565
566 if (hdmi->audio_channels == 2)
567 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
568 else
569 value = 0;
570
571 value |= source;
572
573 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
574 }
575
576
577
578
579
580 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
581 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
582
583 if (!hdmi->config->has_hda)
584 value |= source;
585
586 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
587
588
589
590
591 if (hdmi->config->has_hbr) {
592 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
593 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
594 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
595 }
596
597 config = tegra_hdmi_get_audio_config(hdmi->audio_sample_rate,
598 hdmi->pixel_clock);
599 if (!config) {
600 dev_err(hdmi->dev,
601 "cannot set audio to %u Hz at %u Hz pixel clock\n",
602 hdmi->audio_sample_rate, hdmi->pixel_clock);
603 return -EINVAL;
604 }
605
606 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
607
608 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
609 AUDIO_N_VALUE(config->n - 1);
610 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
611
612 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
613 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
614
615 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
616 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
617
618 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
619 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
620
621 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
622 value &= ~AUDIO_N_RESETF;
623 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
624
625 if (hdmi->config->has_hda)
626 tegra_hdmi_write_aval(hdmi, config->aval);
627
628 tegra_hdmi_setup_audio_fs_tables(hdmi);
629
630 return 0;
631}
632
633static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
634{
635 u32 value;
636
637 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
638 value &= ~GENERIC_CTRL_AUDIO;
639 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
640}
641
642static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
643{
644 u32 value;
645
646 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
647 value |= GENERIC_CTRL_AUDIO;
648 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
649}
650
651static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
652{
653 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
654 u32 value;
655
656 for (i = 0; i < length; i++)
657 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
658 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
659
660
661
662
663
664
665
666 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
667 tegra_hdmi_writel(hdmi, i << 8 | 0,
668 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
669
670 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
671 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
672}
673
674static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
675{
676 u32 value = 0;
677 size_t i;
678
679 for (i = size; i > 0; i--)
680 value = (value << 8) | ptr[i - 1];
681
682 return value;
683}
684
685static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
686 size_t size)
687{
688 const u8 *ptr = data;
689 unsigned long offset;
690 size_t i, j;
691 u32 value;
692
693 switch (ptr[0]) {
694 case HDMI_INFOFRAME_TYPE_AVI:
695 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
696 break;
697
698 case HDMI_INFOFRAME_TYPE_AUDIO:
699 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
700 break;
701
702 case HDMI_INFOFRAME_TYPE_VENDOR:
703 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
704 break;
705
706 default:
707 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
708 ptr[0]);
709 return;
710 }
711
712 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
713 INFOFRAME_HEADER_VERSION(ptr[1]) |
714 INFOFRAME_HEADER_LEN(ptr[2]);
715 tegra_hdmi_writel(hdmi, value, offset);
716 offset++;
717
718
719
720
721
722
723 for (i = 3, j = 0; i < size; i += 7, j += 8) {
724 size_t rem = size - i, num = min_t(size_t, rem, 4);
725
726 value = tegra_hdmi_subpack(&ptr[i], num);
727 tegra_hdmi_writel(hdmi, value, offset++);
728
729 num = min_t(size_t, rem - num, 3);
730
731 value = tegra_hdmi_subpack(&ptr[i + 4], num);
732 tegra_hdmi_writel(hdmi, value, offset++);
733 }
734}
735
736static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
737 struct drm_display_mode *mode)
738{
739 struct hdmi_avi_infoframe frame;
740 u8 buffer[17];
741 ssize_t err;
742
743 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
744 if (err < 0) {
745 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
746 return;
747 }
748
749 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
750 if (err < 0) {
751 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
752 return;
753 }
754
755 tegra_hdmi_write_infopack(hdmi, buffer, err);
756}
757
758static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
759{
760 u32 value;
761
762 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
763 value &= ~INFOFRAME_CTRL_ENABLE;
764 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
765}
766
767static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
768{
769 u32 value;
770
771 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
772 value |= INFOFRAME_CTRL_ENABLE;
773 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
774}
775
776static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
777{
778 struct hdmi_audio_infoframe frame;
779 u8 buffer[14];
780 ssize_t err;
781
782 err = hdmi_audio_infoframe_init(&frame);
783 if (err < 0) {
784 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
785 err);
786 return;
787 }
788
789 frame.channels = hdmi->audio_channels;
790
791 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
792 if (err < 0) {
793 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
794 err);
795 return;
796 }
797
798
799
800
801
802
803
804 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
805}
806
807static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
808{
809 u32 value;
810
811 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
812 value &= ~INFOFRAME_CTRL_ENABLE;
813 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
814}
815
816static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
817{
818 u32 value;
819
820 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
821 value |= INFOFRAME_CTRL_ENABLE;
822 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
823}
824
825static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
826{
827 struct hdmi_vendor_infoframe frame;
828 u8 buffer[10];
829 ssize_t err;
830
831 hdmi_vendor_infoframe_init(&frame);
832 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
833
834 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
835 if (err < 0) {
836 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
837 err);
838 return;
839 }
840
841 tegra_hdmi_write_infopack(hdmi, buffer, err);
842}
843
844static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
845{
846 u32 value;
847
848 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
849 value &= ~GENERIC_CTRL_ENABLE;
850 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
851}
852
853static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
854{
855 u32 value;
856
857 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
858 value |= GENERIC_CTRL_ENABLE;
859 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
860}
861
862static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
863 const struct tmds_config *tmds)
864{
865 u32 value;
866
867 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
868 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
869 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
870
871 tegra_hdmi_writel(hdmi, tmds->drive_current,
872 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
873
874 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
875 value |= hdmi->config->fuse_override_value;
876 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
877
878 if (hdmi->config->has_sor_io_peak_current)
879 tegra_hdmi_writel(hdmi, tmds->peak_current,
880 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
881}
882
883static bool tegra_output_is_hdmi(struct tegra_output *output)
884{
885 struct edid *edid;
886
887 if (!output->connector.edid_blob_ptr)
888 return false;
889
890 edid = (struct edid *)output->connector.edid_blob_ptr->data;
891
892 return drm_detect_hdmi_monitor(edid);
893}
894
895static enum drm_connector_status
896tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
897{
898 struct tegra_output *output = connector_to_output(connector);
899 struct tegra_hdmi *hdmi = to_hdmi(output);
900 enum drm_connector_status status;
901
902 status = tegra_output_connector_detect(connector, force);
903 if (status == connector_status_connected)
904 return status;
905
906 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
907 return status;
908}
909
910static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
911 .reset = drm_atomic_helper_connector_reset,
912 .detect = tegra_hdmi_connector_detect,
913 .fill_modes = drm_helper_probe_single_connector_modes,
914 .destroy = tegra_output_connector_destroy,
915 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
916 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
917};
918
919static enum drm_mode_status
920tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
921 struct drm_display_mode *mode)
922{
923 struct tegra_output *output = connector_to_output(connector);
924 struct tegra_hdmi *hdmi = to_hdmi(output);
925 unsigned long pclk = mode->clock * 1000;
926 enum drm_mode_status status = MODE_OK;
927 struct clk *parent;
928 long err;
929
930 parent = clk_get_parent(hdmi->clk_parent);
931
932 err = clk_round_rate(parent, pclk * 4);
933 if (err <= 0)
934 status = MODE_NOCLOCK;
935
936 return status;
937}
938
939static const struct drm_connector_helper_funcs
940tegra_hdmi_connector_helper_funcs = {
941 .get_modes = tegra_output_connector_get_modes,
942 .mode_valid = tegra_hdmi_connector_mode_valid,
943};
944
945static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
946 .destroy = tegra_output_encoder_destroy,
947};
948
949static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
950{
951 struct tegra_output *output = encoder_to_output(encoder);
952 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
953 struct tegra_hdmi *hdmi = to_hdmi(output);
954 u32 value;
955
956
957
958
959
960 if (dc) {
961 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
962 value &= ~HDMI_ENABLE;
963 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
964
965 tegra_dc_commit(dc);
966 }
967
968 if (!hdmi->dvi) {
969 if (hdmi->stereo)
970 tegra_hdmi_disable_stereo_infoframe(hdmi);
971
972 tegra_hdmi_disable_audio_infoframe(hdmi);
973 tegra_hdmi_disable_avi_infoframe(hdmi);
974 tegra_hdmi_disable_audio(hdmi);
975 }
976
977 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
978 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
979
980 pm_runtime_put(hdmi->dev);
981}
982
983static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
984{
985 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
986 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
987 struct tegra_output *output = encoder_to_output(encoder);
988 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
989 struct tegra_hdmi *hdmi = to_hdmi(output);
990 unsigned int pulse_start, div82;
991 int retries = 1000;
992 u32 value;
993 int err;
994
995 pm_runtime_get_sync(hdmi->dev);
996
997
998
999
1000
1001
1002 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1003 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1004
1005 hdmi->pixel_clock = mode->clock * 1000;
1006 h_sync_width = mode->hsync_end - mode->hsync_start;
1007 h_back_porch = mode->htotal - mode->hsync_end;
1008 h_front_porch = mode->hsync_start - mode->hdisplay;
1009
1010 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1011 if (err < 0) {
1012 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1013 err);
1014 }
1015
1016 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1017
1018
1019 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1020 value &= ~SOR_PLL_PDBG;
1021 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1022
1023 usleep_range(10, 20);
1024
1025 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1026 value &= ~SOR_PLL_PWR;
1027 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1028
1029 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1030 DC_DISP_DISP_TIMING_OPTIONS);
1031 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1032 DC_DISP_DISP_COLOR_CONTROL);
1033
1034
1035 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1036
1037 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1038
1039 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1040 PULSE_LAST_END_A;
1041 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1042
1043 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1044 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1045
1046 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1047 VSYNC_WINDOW_ENABLE;
1048 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1049
1050 if (dc->pipe)
1051 value = HDMI_SRC_DISPLAYB;
1052 else
1053 value = HDMI_SRC_DISPLAYA;
1054
1055 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1056 (mode->vdisplay == 576)))
1057 tegra_hdmi_writel(hdmi,
1058 value | ARM_VIDEO_RANGE_FULL,
1059 HDMI_NV_PDISP_INPUT_CONTROL);
1060 else
1061 tegra_hdmi_writel(hdmi,
1062 value | ARM_VIDEO_RANGE_LIMITED,
1063 HDMI_NV_PDISP_INPUT_CONTROL);
1064
1065 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1066 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1067 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1068
1069 hdmi->dvi = !tegra_output_is_hdmi(output);
1070 if (!hdmi->dvi) {
1071 err = tegra_hdmi_setup_audio(hdmi);
1072 if (err < 0)
1073 hdmi->dvi = true;
1074 }
1075
1076 if (hdmi->config->has_hda)
1077 tegra_hdmi_write_eld(hdmi);
1078
1079 rekey = HDMI_REKEY_DEFAULT;
1080 value = HDMI_CTRL_REKEY(rekey);
1081 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1082 h_front_porch - rekey - 18) / 32);
1083
1084 if (!hdmi->dvi)
1085 value |= HDMI_CTRL_ENABLE;
1086
1087 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1088
1089 if (!hdmi->dvi) {
1090 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1091 tegra_hdmi_setup_audio_infoframe(hdmi);
1092
1093 if (hdmi->stereo)
1094 tegra_hdmi_setup_stereo_infoframe(hdmi);
1095 }
1096
1097
1098 for (i = 0; i < hdmi->config->num_tmds; i++) {
1099 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1100 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1101 break;
1102 }
1103 }
1104
1105 tegra_hdmi_writel(hdmi,
1106 SOR_SEQ_PU_PC(0) |
1107 SOR_SEQ_PU_PC_ALT(0) |
1108 SOR_SEQ_PD_PC(8) |
1109 SOR_SEQ_PD_PC_ALT(8),
1110 HDMI_NV_PDISP_SOR_SEQ_CTL);
1111
1112 value = SOR_SEQ_INST_WAIT_TIME(1) |
1113 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1114 SOR_SEQ_INST_HALT |
1115 SOR_SEQ_INST_PIN_A_LOW |
1116 SOR_SEQ_INST_PIN_B_LOW |
1117 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1118
1119 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1120 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1121
1122 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1123 value &= ~SOR_CSTM_ROTCLK(~0);
1124 value |= SOR_CSTM_ROTCLK(2);
1125 value |= SOR_CSTM_PLLDIV;
1126 value &= ~SOR_CSTM_LVDS_ENABLE;
1127 value &= ~SOR_CSTM_MODE_MASK;
1128 value |= SOR_CSTM_MODE_TMDS;
1129 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1130
1131
1132 tegra_hdmi_writel(hdmi,
1133 SOR_PWR_NORMAL_STATE_PU |
1134 SOR_PWR_NORMAL_START_NORMAL |
1135 SOR_PWR_SAFE_STATE_PD |
1136 SOR_PWR_SETTING_NEW_TRIGGER,
1137 HDMI_NV_PDISP_SOR_PWR);
1138 tegra_hdmi_writel(hdmi,
1139 SOR_PWR_NORMAL_STATE_PU |
1140 SOR_PWR_NORMAL_START_NORMAL |
1141 SOR_PWR_SAFE_STATE_PD |
1142 SOR_PWR_SETTING_NEW_DONE,
1143 HDMI_NV_PDISP_SOR_PWR);
1144
1145 do {
1146 BUG_ON(--retries < 0);
1147 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1148 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1149
1150 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1151 SOR_STATE_ASY_OWNER_HEAD0 |
1152 SOR_STATE_ASY_SUBOWNER_BOTH |
1153 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1154 SOR_STATE_ASY_DEPOL_POS;
1155
1156
1157 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1158 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1159
1160 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1161 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1162
1163 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1164 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1165
1166 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1167 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1168
1169 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1170
1171 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1172 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1173
1174 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1175 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1176 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1177 HDMI_NV_PDISP_SOR_STATE1);
1178 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1179
1180 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1181 value |= HDMI_ENABLE;
1182 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1183
1184 tegra_dc_commit(dc);
1185
1186 if (!hdmi->dvi) {
1187 tegra_hdmi_enable_avi_infoframe(hdmi);
1188 tegra_hdmi_enable_audio_infoframe(hdmi);
1189 tegra_hdmi_enable_audio(hdmi);
1190
1191 if (hdmi->stereo)
1192 tegra_hdmi_enable_stereo_infoframe(hdmi);
1193 }
1194
1195
1196}
1197
1198static int
1199tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1200 struct drm_crtc_state *crtc_state,
1201 struct drm_connector_state *conn_state)
1202{
1203 struct tegra_output *output = encoder_to_output(encoder);
1204 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1205 unsigned long pclk = crtc_state->mode.clock * 1000;
1206 struct tegra_hdmi *hdmi = to_hdmi(output);
1207 int err;
1208
1209 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1210 pclk, 0);
1211 if (err < 0) {
1212 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1213 return err;
1214 }
1215
1216 return err;
1217}
1218
1219static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1220 .disable = tegra_hdmi_encoder_disable,
1221 .enable = tegra_hdmi_encoder_enable,
1222 .atomic_check = tegra_hdmi_encoder_atomic_check,
1223};
1224
1225static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1226{
1227 struct drm_info_node *node = s->private;
1228 struct tegra_hdmi *hdmi = node->info_ent->data;
1229 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1230 struct drm_device *drm = node->minor->dev;
1231 int err = 0;
1232
1233 drm_modeset_lock_all(drm);
1234
1235 if (!crtc || !crtc->state->active) {
1236 err = -EBUSY;
1237 goto unlock;
1238 }
1239
1240#define DUMP_REG(name) \
1241 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1242 tegra_hdmi_readl(hdmi, name))
1243
1244 DUMP_REG(HDMI_CTXSW);
1245 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1246 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1247 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1248 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1249 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1250 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1251 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1252 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1253 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1254 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1255 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1256 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1257 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1258 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1259 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1260 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1261 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1262 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1263 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1264 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1265 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1266 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1267 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1268 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1269 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1270 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1271 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1272 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1273 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1274 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1275 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1276 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1277 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1278 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1279 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1280 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1281 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1282 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1283 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1284 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1285 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1286 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1287 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1288 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1289 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1290 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1291 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1292 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1293 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1294 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1295 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1296 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1297 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1298 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1299 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1300 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1301 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1302 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1303 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1304 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1305 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1306 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1307 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1308 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1309 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1310 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1311 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1312 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1313 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1314 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1315 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1316 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1317 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1318 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1319 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1320 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1321 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1322 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1323 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1324 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1325 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1326 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1327 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1328 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1329 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1330 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1331 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1332 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1333 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1334 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1335 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1336 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1337 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1338 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1339 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1340 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1341 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1342 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1343 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1344 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1345 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1346 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1347 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1348 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1349 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1350 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1351 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1352 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1353 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1354 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1355 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1356 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1357 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1358 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1359 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1360 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1361 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1362 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1363 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1364 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1365 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1366 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1367 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1368 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1369 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1370 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1371 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1372 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1373 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1374 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1375 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1376 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1377 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1378 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1379 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1380 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1381 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1382 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1383 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1384 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1385 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1386 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1387 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1388 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1389 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1390 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1391 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1392 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1393 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1394 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1395 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1396 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1397 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1398 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1399 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
1400 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1401 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1);
1402 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1403 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1404 DUMP_REG(HDMI_NV_PDISP_INT_STATUS);
1405 DUMP_REG(HDMI_NV_PDISP_INT_MASK);
1406 DUMP_REG(HDMI_NV_PDISP_INT_ENABLE);
1407 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1408
1409#undef DUMP_REG
1410
1411unlock:
1412 drm_modeset_unlock_all(drm);
1413 return err;
1414}
1415
1416static struct drm_info_list debugfs_files[] = {
1417 { "regs", tegra_hdmi_show_regs, 0, NULL },
1418};
1419
1420static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1421 struct drm_minor *minor)
1422{
1423 unsigned int i;
1424 int err;
1425
1426 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1427 if (!hdmi->debugfs)
1428 return -ENOMEM;
1429
1430 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1431 GFP_KERNEL);
1432 if (!hdmi->debugfs_files) {
1433 err = -ENOMEM;
1434 goto remove;
1435 }
1436
1437 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1438 hdmi->debugfs_files[i].data = hdmi;
1439
1440 err = drm_debugfs_create_files(hdmi->debugfs_files,
1441 ARRAY_SIZE(debugfs_files),
1442 hdmi->debugfs, minor);
1443 if (err < 0)
1444 goto free;
1445
1446 hdmi->minor = minor;
1447
1448 return 0;
1449
1450free:
1451 kfree(hdmi->debugfs_files);
1452 hdmi->debugfs_files = NULL;
1453remove:
1454 debugfs_remove(hdmi->debugfs);
1455 hdmi->debugfs = NULL;
1456
1457 return err;
1458}
1459
1460static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1461{
1462 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1463 hdmi->minor);
1464 hdmi->minor = NULL;
1465
1466 kfree(hdmi->debugfs_files);
1467 hdmi->debugfs_files = NULL;
1468
1469 debugfs_remove(hdmi->debugfs);
1470 hdmi->debugfs = NULL;
1471}
1472
1473static int tegra_hdmi_init(struct host1x_client *client)
1474{
1475 struct drm_device *drm = dev_get_drvdata(client->parent);
1476 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1477 int err;
1478
1479 hdmi->output.dev = client->dev;
1480
1481 drm_connector_init(drm, &hdmi->output.connector,
1482 &tegra_hdmi_connector_funcs,
1483 DRM_MODE_CONNECTOR_HDMIA);
1484 drm_connector_helper_add(&hdmi->output.connector,
1485 &tegra_hdmi_connector_helper_funcs);
1486 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1487
1488 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1489 DRM_MODE_ENCODER_TMDS, NULL);
1490 drm_encoder_helper_add(&hdmi->output.encoder,
1491 &tegra_hdmi_encoder_helper_funcs);
1492
1493 drm_mode_connector_attach_encoder(&hdmi->output.connector,
1494 &hdmi->output.encoder);
1495 drm_connector_register(&hdmi->output.connector);
1496
1497 err = tegra_output_init(drm, &hdmi->output);
1498 if (err < 0) {
1499 dev_err(client->dev, "failed to initialize output: %d\n", err);
1500 return err;
1501 }
1502
1503 hdmi->output.encoder.possible_crtcs = 0x3;
1504
1505 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1506 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1507 if (err < 0)
1508 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1509 }
1510
1511 err = regulator_enable(hdmi->hdmi);
1512 if (err < 0) {
1513 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1514 err);
1515 return err;
1516 }
1517
1518 err = regulator_enable(hdmi->pll);
1519 if (err < 0) {
1520 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1521 return err;
1522 }
1523
1524 err = regulator_enable(hdmi->vdd);
1525 if (err < 0) {
1526 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1527 return err;
1528 }
1529
1530 return 0;
1531}
1532
1533static int tegra_hdmi_exit(struct host1x_client *client)
1534{
1535 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1536
1537 tegra_output_exit(&hdmi->output);
1538
1539 regulator_disable(hdmi->vdd);
1540 regulator_disable(hdmi->pll);
1541 regulator_disable(hdmi->hdmi);
1542
1543 if (IS_ENABLED(CONFIG_DEBUG_FS))
1544 tegra_hdmi_debugfs_exit(hdmi);
1545
1546 return 0;
1547}
1548
1549static const struct host1x_client_ops hdmi_client_ops = {
1550 .init = tegra_hdmi_init,
1551 .exit = tegra_hdmi_exit,
1552};
1553
1554static const struct tegra_hdmi_config tegra20_hdmi_config = {
1555 .tmds = tegra20_tmds_config,
1556 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1557 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1558 .fuse_override_value = 1 << 31,
1559 .has_sor_io_peak_current = false,
1560 .has_hda = false,
1561 .has_hbr = false,
1562};
1563
1564static const struct tegra_hdmi_config tegra30_hdmi_config = {
1565 .tmds = tegra30_tmds_config,
1566 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1567 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1568 .fuse_override_value = 1 << 31,
1569 .has_sor_io_peak_current = false,
1570 .has_hda = true,
1571 .has_hbr = false,
1572};
1573
1574static const struct tegra_hdmi_config tegra114_hdmi_config = {
1575 .tmds = tegra114_tmds_config,
1576 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1577 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1578 .fuse_override_value = 1 << 31,
1579 .has_sor_io_peak_current = true,
1580 .has_hda = true,
1581 .has_hbr = true,
1582};
1583
1584static const struct tegra_hdmi_config tegra124_hdmi_config = {
1585 .tmds = tegra124_tmds_config,
1586 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1587 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1588 .fuse_override_value = 1 << 31,
1589 .has_sor_io_peak_current = true,
1590 .has_hda = true,
1591 .has_hbr = true,
1592};
1593
1594static const struct of_device_id tegra_hdmi_of_match[] = {
1595 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1596 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1597 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1598 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1599 { },
1600};
1601MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1602
1603static void hda_format_parse(unsigned int format, unsigned int *rate,
1604 unsigned int *channels)
1605{
1606 unsigned int mul, div;
1607
1608 if (format & AC_FMT_BASE_44K)
1609 *rate = 44100;
1610 else
1611 *rate = 48000;
1612
1613 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT;
1614 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT;
1615
1616 *rate = *rate * (mul + 1) / (div + 1);
1617
1618 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT;
1619}
1620
1621static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1622{
1623 struct tegra_hdmi *hdmi = data;
1624 u32 value;
1625 int err;
1626
1627 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1628 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1629
1630 if (value & INT_CODEC_SCRATCH0) {
1631 unsigned int format;
1632 u32 value;
1633
1634 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1635
1636 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1637 unsigned int sample_rate, channels;
1638
1639 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1640
1641 hda_format_parse(format, &sample_rate, &channels);
1642
1643 hdmi->audio_sample_rate = sample_rate;
1644 hdmi->audio_channels = channels;
1645
1646 err = tegra_hdmi_setup_audio(hdmi);
1647 if (err < 0) {
1648 tegra_hdmi_disable_audio_infoframe(hdmi);
1649 tegra_hdmi_disable_audio(hdmi);
1650 } else {
1651 tegra_hdmi_setup_audio_infoframe(hdmi);
1652 tegra_hdmi_enable_audio_infoframe(hdmi);
1653 tegra_hdmi_enable_audio(hdmi);
1654 }
1655 } else {
1656 tegra_hdmi_disable_audio_infoframe(hdmi);
1657 tegra_hdmi_disable_audio(hdmi);
1658 }
1659 }
1660
1661 return IRQ_HANDLED;
1662}
1663
1664static int tegra_hdmi_probe(struct platform_device *pdev)
1665{
1666 const struct of_device_id *match;
1667 struct tegra_hdmi *hdmi;
1668 struct resource *regs;
1669 int err;
1670
1671 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1672 if (!match)
1673 return -ENODEV;
1674
1675 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1676 if (!hdmi)
1677 return -ENOMEM;
1678
1679 hdmi->config = match->data;
1680 hdmi->dev = &pdev->dev;
1681
1682 hdmi->audio_source = AUTO;
1683 hdmi->audio_sample_rate = 48000;
1684 hdmi->audio_channels = 2;
1685 hdmi->stereo = false;
1686 hdmi->dvi = false;
1687
1688 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1689 if (IS_ERR(hdmi->clk)) {
1690 dev_err(&pdev->dev, "failed to get clock\n");
1691 return PTR_ERR(hdmi->clk);
1692 }
1693
1694 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1695 if (IS_ERR(hdmi->rst)) {
1696 dev_err(&pdev->dev, "failed to get reset\n");
1697 return PTR_ERR(hdmi->rst);
1698 }
1699
1700 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1701 if (IS_ERR(hdmi->clk_parent))
1702 return PTR_ERR(hdmi->clk_parent);
1703
1704 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1705 if (err < 0) {
1706 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1707 return err;
1708 }
1709
1710 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1711 if (IS_ERR(hdmi->hdmi)) {
1712 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1713 return PTR_ERR(hdmi->hdmi);
1714 }
1715
1716 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1717 if (IS_ERR(hdmi->pll)) {
1718 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1719 return PTR_ERR(hdmi->pll);
1720 }
1721
1722 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1723 if (IS_ERR(hdmi->vdd)) {
1724 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1725 return PTR_ERR(hdmi->vdd);
1726 }
1727
1728 hdmi->output.dev = &pdev->dev;
1729
1730 err = tegra_output_probe(&hdmi->output);
1731 if (err < 0)
1732 return err;
1733
1734 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1736 if (IS_ERR(hdmi->regs))
1737 return PTR_ERR(hdmi->regs);
1738
1739 err = platform_get_irq(pdev, 0);
1740 if (err < 0)
1741 return err;
1742
1743 hdmi->irq = err;
1744
1745 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1746 dev_name(hdmi->dev), hdmi);
1747 if (err < 0) {
1748 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1749 hdmi->irq, err);
1750 return err;
1751 }
1752
1753 platform_set_drvdata(pdev, hdmi);
1754 pm_runtime_enable(&pdev->dev);
1755
1756 INIT_LIST_HEAD(&hdmi->client.list);
1757 hdmi->client.ops = &hdmi_client_ops;
1758 hdmi->client.dev = &pdev->dev;
1759
1760 err = host1x_client_register(&hdmi->client);
1761 if (err < 0) {
1762 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1763 err);
1764 return err;
1765 }
1766
1767 return 0;
1768}
1769
1770static int tegra_hdmi_remove(struct platform_device *pdev)
1771{
1772 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1773 int err;
1774
1775 pm_runtime_disable(&pdev->dev);
1776
1777 err = host1x_client_unregister(&hdmi->client);
1778 if (err < 0) {
1779 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1780 err);
1781 return err;
1782 }
1783
1784 tegra_output_remove(&hdmi->output);
1785
1786 return 0;
1787}
1788
1789#ifdef CONFIG_PM
1790static int tegra_hdmi_suspend(struct device *dev)
1791{
1792 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1793 int err;
1794
1795 err = reset_control_assert(hdmi->rst);
1796 if (err < 0) {
1797 dev_err(dev, "failed to assert reset: %d\n", err);
1798 return err;
1799 }
1800
1801 usleep_range(1000, 2000);
1802
1803 clk_disable_unprepare(hdmi->clk);
1804
1805 return 0;
1806}
1807
1808static int tegra_hdmi_resume(struct device *dev)
1809{
1810 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1811 int err;
1812
1813 err = clk_prepare_enable(hdmi->clk);
1814 if (err < 0) {
1815 dev_err(dev, "failed to enable clock: %d\n", err);
1816 return err;
1817 }
1818
1819 usleep_range(1000, 2000);
1820
1821 err = reset_control_deassert(hdmi->rst);
1822 if (err < 0) {
1823 dev_err(dev, "failed to deassert reset: %d\n", err);
1824 clk_disable_unprepare(hdmi->clk);
1825 return err;
1826 }
1827
1828 return 0;
1829}
1830#endif
1831
1832static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1833 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1834};
1835
1836struct platform_driver tegra_hdmi_driver = {
1837 .driver = {
1838 .name = "tegra-hdmi",
1839 .of_match_table = tegra_hdmi_of_match,
1840 .pm = &tegra_hdmi_pm_ops,
1841 },
1842 .probe = tegra_hdmi_probe,
1843 .remove = tegra_hdmi_remove,
1844};
1845
