1/* 2 * drivers/media/i2c/tvp514x_regs.h 3 * 4 * Copyright (C) 2008 Texas Instruments Inc 5 * Author: Vaibhav Hiremath <hvaibhav@ti.com> 6 * 7 * Contributors: 8 * Sivaraj R <sivaraj@ti.com> 9 * Brijesh R Jadav <brijesh.j@ti.com> 10 * Hardik Shah <hardik.shah@ti.com> 11 * Manjunath Hadli <mrh@ti.com> 12 * Karicheri Muralidharan <m-karicheri2@ti.com> 13 * 14 * This package is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 */ 24 25#ifndef _TVP514X_REGS_H 26#define _TVP514X_REGS_H 27 28/* 29 * TVP5146/47 registers 30 */ 31#define REG_INPUT_SEL (0x00) 32#define REG_AFE_GAIN_CTRL (0x01) 33#define REG_VIDEO_STD (0x02) 34#define REG_OPERATION_MODE (0x03) 35#define REG_AUTOSWITCH_MASK (0x04) 36 37#define REG_COLOR_KILLER (0x05) 38#define REG_LUMA_CONTROL1 (0x06) 39#define REG_LUMA_CONTROL2 (0x07) 40#define REG_LUMA_CONTROL3 (0x08) 41 42#define REG_BRIGHTNESS (0x09) 43#define REG_CONTRAST (0x0A) 44#define REG_SATURATION (0x0B) 45#define REG_HUE (0x0C) 46 47#define REG_CHROMA_CONTROL1 (0x0D) 48#define REG_CHROMA_CONTROL2 (0x0E) 49 50/* 0x0F Reserved */ 51 52#define REG_COMP_PR_SATURATION (0x10) 53#define REG_COMP_Y_CONTRAST (0x11) 54#define REG_COMP_PB_SATURATION (0x12) 55 56/* 0x13 Reserved */ 57 58#define REG_COMP_Y_BRIGHTNESS (0x14) 59 60/* 0x15 Reserved */ 61 62#define REG_AVID_START_PIXEL_LSB (0x16) 63#define REG_AVID_START_PIXEL_MSB (0x17) 64#define REG_AVID_STOP_PIXEL_LSB (0x18) 65#define REG_AVID_STOP_PIXEL_MSB (0x19) 66 67#define REG_HSYNC_START_PIXEL_LSB (0x1A) 68#define REG_HSYNC_START_PIXEL_MSB (0x1B) 69#define REG_HSYNC_STOP_PIXEL_LSB (0x1C) 70#define REG_HSYNC_STOP_PIXEL_MSB (0x1D) 71 72#define REG_VSYNC_START_LINE_LSB (0x1E) 73#define REG_VSYNC_START_LINE_MSB (0x1F) 74#define REG_VSYNC_STOP_LINE_LSB (0x20) 75#define REG_VSYNC_STOP_LINE_MSB (0x21) 76 77#define REG_VBLK_START_LINE_LSB (0x22) 78#define REG_VBLK_START_LINE_MSB (0x23) 79#define REG_VBLK_STOP_LINE_LSB (0x24) 80#define REG_VBLK_STOP_LINE_MSB (0x25) 81 82/* 0x26 - 0x27 Reserved */ 83 84#define REG_FAST_SWTICH_CONTROL (0x28) 85 86/* 0x29 Reserved */ 87 88#define REG_FAST_SWTICH_SCART_DELAY (0x2A) 89 90/* 0x2B Reserved */ 91 92#define REG_SCART_DELAY (0x2C) 93#define REG_CTI_DELAY (0x2D) 94#define REG_CTI_CONTROL (0x2E) 95 96/* 0x2F - 0x31 Reserved */ 97 98#define REG_SYNC_CONTROL (0x32) 99#define REG_OUTPUT_FORMATTER1 (0x33) 100#define REG_OUTPUT_FORMATTER2 (0x34) 101#define REG_OUTPUT_FORMATTER3 (0x35) 102#define REG_OUTPUT_FORMATTER4 (0x36) 103#define REG_OUTPUT_FORMATTER5 (0x37) 104#define REG_OUTPUT_FORMATTER6 (0x38) 105#define REG_CLEAR_LOST_LOCK (0x39) 106 107#define REG_STATUS1 (0x3A) 108#define REG_STATUS2 (0x3B) 109 110#define REG_AGC_GAIN_STATUS_LSB (0x3C) 111#define REG_AGC_GAIN_STATUS_MSB (0x3D) 112 113/* 0x3E Reserved */ 114 115#define REG_VIDEO_STD_STATUS (0x3F) 116#define REG_GPIO_INPUT1 (0x40) 117#define REG_GPIO_INPUT2 (0x41) 118 119/* 0x42 - 0x45 Reserved */ 120 121#define REG_AFE_COARSE_GAIN_CH1 (0x46) 122#define REG_AFE_COARSE_GAIN_CH2 (0x47) 123#define REG_AFE_COARSE_GAIN_CH3 (0x48) 124#define REG_AFE_COARSE_GAIN_CH4 (0x49) 125 126#define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A) 127#define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B) 128#define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C) 129#define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D) 130#define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E) 131#define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F) 132#define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50) 133#define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51) 134 135/* 0x52 - 0x68 Reserved */ 136 137#define REG_FBIT_VBIT_CONTROL1 (0x69) 138 139/* 0x6A - 0x6B Reserved */ 140 141#define REG_BACKEND_AGC_CONTROL (0x6C) 142 143/* 0x6D - 0x6E Reserved */ 144 145#define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F) 146#define REG_ROM_VERSION (0x70) 147 148/* 0x71 - 0x73 Reserved */ 149 150#define REG_AGC_WHITE_PEAK_PROCESSING (0x74) 151#define REG_FBIT_VBIT_CONTROL2 (0x75) 152#define REG_VCR_TRICK_MODE_CONTROL (0x76) 153#define REG_HORIZONTAL_SHAKE_INCREMENT (0x77) 154#define REG_AGC_INCREMENT_SPEED (0x78) 155#define REG_AGC_INCREMENT_DELAY (0x79) 156 157/* 0x7A - 0x7F Reserved */ 158 159#define REG_CHIP_ID_MSB (0x80) 160#define REG_CHIP_ID_LSB (0x81) 161 162/* 0x82 Reserved */ 163 164#define REG_CPLL_SPEED_CONTROL (0x83) 165 166/* 0x84 - 0x96 Reserved */ 167 168#define REG_STATUS_REQUEST (0x97) 169 170/* 0x98 - 0x99 Reserved */ 171 172#define REG_VERTICAL_LINE_COUNT_LSB (0x9A) 173#define REG_VERTICAL_LINE_COUNT_MSB (0x9B) 174 175/* 0x9C - 0x9D Reserved */ 176 177#define REG_AGC_DECREMENT_DELAY (0x9E) 178 179/* 0x9F - 0xB0 Reserved */ 180 181#define REG_VDP_TTX_FILTER_1_MASK1 (0xB1) 182#define REG_VDP_TTX_FILTER_1_MASK2 (0xB2) 183#define REG_VDP_TTX_FILTER_1_MASK3 (0xB3) 184#define REG_VDP_TTX_FILTER_1_MASK4 (0xB4) 185#define REG_VDP_TTX_FILTER_1_MASK5 (0xB5) 186#define REG_VDP_TTX_FILTER_2_MASK1 (0xB6) 187#define REG_VDP_TTX_FILTER_2_MASK2 (0xB7) 188#define REG_VDP_TTX_FILTER_2_MASK3 (0xB8) 189#define REG_VDP_TTX_FILTER_2_MASK4 (0xB9) 190#define REG_VDP_TTX_FILTER_2_MASK5 (0xBA) 191#define REG_VDP_TTX_FILTER_CONTROL (0xBB) 192#define REG_VDP_FIFO_WORD_COUNT (0xBC) 193#define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD) 194 195/* 0xBE Reserved */ 196 197#define REG_VDP_FIFO_RESET (0xBF) 198#define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0) 199#define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1) 200#define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2) 201#define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3) 202 203/* 0xC4 - 0xD5 Reserved */ 204 205#define REG_VDP_LINE_START (0xD6) 206#define REG_VDP_LINE_STOP (0xD7) 207#define REG_VDP_GLOBAL_LINE_MODE (0xD8) 208#define REG_VDP_FULL_FIELD_ENABLE (0xD9) 209#define REG_VDP_FULL_FIELD_MODE (0xDA) 210 211/* 0xDB - 0xDF Reserved */ 212 213#define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0) 214#define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1) 215#define REG_FIFO_READ_DATA (0xE2) 216 217/* 0xE3 - 0xE7 Reserved */ 218 219#define REG_VBUS_ADDRESS_ACCESS1 (0xE8) 220#define REG_VBUS_ADDRESS_ACCESS2 (0xE9) 221#define REG_VBUS_ADDRESS_ACCESS3 (0xEA) 222 223/* 0xEB - 0xEF Reserved */ 224 225#define REG_INTERRUPT_RAW_STATUS0 (0xF0) 226#define REG_INTERRUPT_RAW_STATUS1 (0xF1) 227#define REG_INTERRUPT_STATUS0 (0xF2) 228#define REG_INTERRUPT_STATUS1 (0xF3) 229#define REG_INTERRUPT_MASK0 (0xF4) 230#define REG_INTERRUPT_MASK1 (0xF5) 231#define REG_INTERRUPT_CLEAR0 (0xF6) 232#define REG_INTERRUPT_CLEAR1 (0xF7) 233 234/* 0xF8 - 0xFF Reserved */ 235 236/* 237 * Mask and bit definitions of TVP5146/47 registers 238 */ 239/* The ID values we are looking for */ 240#define TVP514X_CHIP_ID_MSB (0x51) 241#define TVP5146_CHIP_ID_LSB (0x46) 242#define TVP5147_CHIP_ID_LSB (0x47) 243 244#define VIDEO_STD_MASK (0x07) 245#define VIDEO_STD_AUTO_SWITCH_BIT (0x00) 246#define VIDEO_STD_NTSC_MJ_BIT (0x01) 247#define VIDEO_STD_PAL_BDGHIN_BIT (0x02) 248#define VIDEO_STD_PAL_M_BIT (0x03) 249#define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04) 250#define VIDEO_STD_NTSC_4_43_BIT (0x05) 251#define VIDEO_STD_SECAM_BIT (0x06) 252#define VIDEO_STD_PAL_60_BIT (0x07) 253 254/* 255 * Status bit 256 */ 257#define STATUS_TV_VCR_BIT (1<<0) 258#define STATUS_HORZ_SYNC_LOCK_BIT (1<<1) 259#define STATUS_VIRT_SYNC_LOCK_BIT (1<<2) 260#define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3) 261#define STATUS_LOST_LOCK_DETECT_BIT (1<<4) 262#define STATUS_FEILD_RATE_BIT (1<<5) 263#define STATUS_LINE_ALTERNATING_BIT (1<<6) 264#define STATUS_PEAK_WHITE_DETECT_BIT (1<<7) 265 266/* Tokens for register write */ 267#define TOK_WRITE (0) /* token for write operation */ 268#define TOK_TERM (1) /* terminating token */ 269#define TOK_DELAY (2) /* delay token for reg list */ 270#define TOK_SKIP (3) /* token to skip a register */ 271/** 272 * struct tvp514x_reg - Structure for TVP5146/47 register initialization values 273 * @token - Token: TOK_WRITE, TOK_TERM etc.. 274 * @reg - Register offset 275 * @val - Register Value for TOK_WRITE or delay in ms for TOK_DELAY 276 */ 277struct tvp514x_reg { 278 u8 token; 279 u8 reg; 280 u32 val; 281}; 282 283#endif /* ifndef _TVP514X_REGS_H */ 284