linux/drivers/media/platform/rcar_drif.c
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   1/*
   2 * R-Car Gen3 Digital Radio Interface (DRIF) driver
   3 *
   4 * Copyright (C) 2017 Renesas Electronics Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 */
  16
  17/*
  18 * The R-Car DRIF is a receive only MSIOF like controller with an
  19 * external master device driving the SCK. It receives data into a FIFO,
  20 * then this driver uses the SYS-DMAC engine to move the data from
  21 * the device to memory.
  22 *
  23 * Each DRIF channel DRIFx (as per datasheet) contains two internal
  24 * channels DRIFx0 & DRIFx1 within itself with each having its own resources
  25 * like module clk, register set, irq and dma. These internal channels share
  26 * common CLK & SYNC from master. The two data pins D0 & D1 shall be
  27 * considered to represent the two internal channels. This internal split
  28 * is not visible to the master device.
  29 *
  30 * Depending on the master device, a DRIF channel can use
  31 *  (1) both internal channels (D0 & D1) to receive data in parallel (or)
  32 *  (2) one internal channel (D0 or D1) to receive data
  33 *
  34 * The primary design goal of this controller is to act as a Digital Radio
  35 * Interface that receives digital samples from a tuner device. Hence the
  36 * driver exposes the device as a V4L2 SDR device. In order to qualify as
  37 * a V4L2 SDR device, it should possess a tuner interface as mandated by the
  38 * framework. This driver expects a tuner driver (sub-device) to bind
  39 * asynchronously with this device and the combined drivers shall expose
  40 * a V4L2 compliant SDR device. The DRIF driver is independent of the
  41 * tuner vendor.
  42 *
  43 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.
  44 * This driver is tested for I2S mode only because of the availability of
  45 * suitable master devices. Hence, not all configurable options of DRIF h/w
  46 * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults
  47 * are used. These can be exposed later if needed after testing.
  48 */
  49#include <linux/bitops.h>
  50#include <linux/clk.h>
  51#include <linux/dma-mapping.h>
  52#include <linux/dmaengine.h>
  53#include <linux/ioctl.h>
  54#include <linux/iopoll.h>
  55#include <linux/module.h>
  56#include <linux/of_graph.h>
  57#include <linux/of_device.h>
  58#include <linux/platform_device.h>
  59#include <linux/sched.h>
  60#include <media/v4l2-async.h>
  61#include <media/v4l2-ctrls.h>
  62#include <media/v4l2-device.h>
  63#include <media/v4l2-event.h>
  64#include <media/v4l2-fh.h>
  65#include <media/v4l2-ioctl.h>
  66#include <media/videobuf2-v4l2.h>
  67#include <media/videobuf2-vmalloc.h>
  68
  69/* DRIF register offsets */
  70#define RCAR_DRIF_SITMDR1                       0x00
  71#define RCAR_DRIF_SITMDR2                       0x04
  72#define RCAR_DRIF_SITMDR3                       0x08
  73#define RCAR_DRIF_SIRMDR1                       0x10
  74#define RCAR_DRIF_SIRMDR2                       0x14
  75#define RCAR_DRIF_SIRMDR3                       0x18
  76#define RCAR_DRIF_SICTR                         0x28
  77#define RCAR_DRIF_SIFCTR                        0x30
  78#define RCAR_DRIF_SISTR                         0x40
  79#define RCAR_DRIF_SIIER                         0x44
  80#define RCAR_DRIF_SIRFDR                        0x60
  81
  82#define RCAR_DRIF_RFOVF                 BIT(3)  /* Receive FIFO overflow */
  83#define RCAR_DRIF_RFUDF                 BIT(4)  /* Receive FIFO underflow */
  84#define RCAR_DRIF_RFSERR                BIT(5)  /* Receive frame sync error */
  85#define RCAR_DRIF_REOF                  BIT(7)  /* Frame reception end */
  86#define RCAR_DRIF_RDREQ                 BIT(12) /* Receive data xfer req */
  87#define RCAR_DRIF_RFFUL                 BIT(13) /* Receive FIFO full */
  88
  89/* SIRMDR1 */
  90#define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME          (0 << 28)
  91#define RCAR_DRIF_SIRMDR1_SYNCMD_LR             (3 << 28)
  92
  93#define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH       (0 << 25)
  94#define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW        (1 << 25)
  95
  96#define RCAR_DRIF_SIRMDR1_MSB_FIRST             (0 << 24)
  97#define RCAR_DRIF_SIRMDR1_LSB_FIRST             (1 << 24)
  98
  99#define RCAR_DRIF_SIRMDR1_DTDL_0                (0 << 20)
 100#define RCAR_DRIF_SIRMDR1_DTDL_1                (1 << 20)
 101#define RCAR_DRIF_SIRMDR1_DTDL_2                (2 << 20)
 102#define RCAR_DRIF_SIRMDR1_DTDL_0PT5             (5 << 20)
 103#define RCAR_DRIF_SIRMDR1_DTDL_1PT5             (6 << 20)
 104
 105#define RCAR_DRIF_SIRMDR1_SYNCDL_0              (0 << 20)
 106#define RCAR_DRIF_SIRMDR1_SYNCDL_1              (1 << 20)
 107#define RCAR_DRIF_SIRMDR1_SYNCDL_2              (2 << 20)
 108#define RCAR_DRIF_SIRMDR1_SYNCDL_3              (3 << 20)
 109#define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5           (5 << 20)
 110#define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5           (6 << 20)
 111
 112#define RCAR_DRIF_MDR_GRPCNT(n)                 (((n) - 1) << 30)
 113#define RCAR_DRIF_MDR_BITLEN(n)                 (((n) - 1) << 24)
 114#define RCAR_DRIF_MDR_WDCNT(n)                  (((n) - 1) << 16)
 115
 116/* Hidden Transmit register that controls CLK & SYNC */
 117#define RCAR_DRIF_SITMDR1_PCON                  BIT(30)
 118
 119#define RCAR_DRIF_SICTR_RX_RISING_EDGE          BIT(26)
 120#define RCAR_DRIF_SICTR_RX_EN                   BIT(8)
 121#define RCAR_DRIF_SICTR_RESET                   BIT(0)
 122
 123/* Constants */
 124#define RCAR_DRIF_NUM_HWBUFS                    32
 125#define RCAR_DRIF_MAX_DEVS                      4
 126#define RCAR_DRIF_DEFAULT_NUM_HWBUFS            16
 127#define RCAR_DRIF_DEFAULT_HWBUF_SIZE            (4 * PAGE_SIZE)
 128#define RCAR_DRIF_MAX_CHANNEL                   2
 129#define RCAR_SDR_BUFFER_SIZE                    SZ_64K
 130
 131/* Internal buffer status flags */
 132#define RCAR_DRIF_BUF_DONE                      BIT(0)  /* DMA completed */
 133#define RCAR_DRIF_BUF_OVERFLOW                  BIT(1)  /* Overflow detected */
 134
 135#define to_rcar_drif_buf_pair(sdr, ch_num, idx)                 \
 136        (&((sdr)->ch[!(ch_num)]->buf[(idx)]))
 137
 138#define for_each_rcar_drif_channel(ch, ch_mask)                 \
 139        for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
 140
 141/* Debug */
 142#define rdrif_dbg(sdr, fmt, arg...)                             \
 143        dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg)
 144
 145#define rdrif_err(sdr, fmt, arg...)                             \
 146        dev_err(sdr->v4l2_dev.dev, fmt, ## arg)
 147
 148/* Stream formats */
 149struct rcar_drif_format {
 150        u32     pixelformat;
 151        u32     buffersize;
 152        u32     bitlen;
 153        u32     wdcnt;
 154        u32     num_ch;
 155};
 156
 157/* Format descriptions for capture */
 158static const struct rcar_drif_format formats[] = {
 159        {
 160                .pixelformat    = V4L2_SDR_FMT_PCU16BE,
 161                .buffersize     = RCAR_SDR_BUFFER_SIZE,
 162                .bitlen         = 16,
 163                .wdcnt          = 1,
 164                .num_ch         = 2,
 165        },
 166        {
 167                .pixelformat    = V4L2_SDR_FMT_PCU18BE,
 168                .buffersize     = RCAR_SDR_BUFFER_SIZE,
 169                .bitlen         = 18,
 170                .wdcnt          = 1,
 171                .num_ch         = 2,
 172        },
 173        {
 174                .pixelformat    = V4L2_SDR_FMT_PCU20BE,
 175                .buffersize     = RCAR_SDR_BUFFER_SIZE,
 176                .bitlen         = 20,
 177                .wdcnt          = 1,
 178                .num_ch         = 2,
 179        },
 180};
 181
 182/* Buffer for a received frame from one or both internal channels */
 183struct rcar_drif_frame_buf {
 184        /* Common v4l buffer stuff -- must be first */
 185        struct vb2_v4l2_buffer vb;
 186        struct list_head list;
 187};
 188
 189/* OF graph endpoint's V4L2 async data */
 190struct rcar_drif_graph_ep {
 191        struct v4l2_subdev *subdev;     /* Async matched subdev */
 192        struct v4l2_async_subdev asd;   /* Async sub-device descriptor */
 193};
 194
 195/* DMA buffer */
 196struct rcar_drif_hwbuf {
 197        void *addr;                     /* CPU-side address */
 198        unsigned int status;            /* Buffer status flags */
 199};
 200
 201/* Internal channel */
 202struct rcar_drif {
 203        struct rcar_drif_sdr *sdr;      /* Group device */
 204        struct platform_device *pdev;   /* Channel's pdev */
 205        void __iomem *base;             /* Base register address */
 206        resource_size_t start;          /* I/O resource offset */
 207        struct dma_chan *dmach;         /* Reserved DMA channel */
 208        struct clk *clk;                /* Module clock */
 209        struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */
 210        dma_addr_t dma_handle;          /* Handle for all bufs */
 211        unsigned int num;               /* Channel number */
 212        bool acting_sdr;                /* Channel acting as SDR device */
 213};
 214
 215/* DRIF V4L2 SDR */
 216struct rcar_drif_sdr {
 217        struct device *dev;             /* Platform device */
 218        struct video_device *vdev;      /* V4L2 SDR device */
 219        struct v4l2_device v4l2_dev;    /* V4L2 device */
 220
 221        /* Videobuf2 queue and queued buffers list */
 222        struct vb2_queue vb_queue;
 223        struct list_head queued_bufs;
 224        spinlock_t queued_bufs_lock;    /* Protects queued_bufs */
 225        spinlock_t dma_lock;            /* To serialize DMA cb of channels */
 226
 227        struct mutex v4l2_mutex;        /* To serialize ioctls */
 228        struct mutex vb_queue_mutex;    /* To serialize streaming ioctls */
 229        struct v4l2_ctrl_handler ctrl_hdl;      /* SDR control handler */
 230        struct v4l2_async_notifier notifier;    /* For subdev (tuner) */
 231        struct rcar_drif_graph_ep ep;   /* Endpoint V4L2 async data */
 232
 233        /* Current V4L2 SDR format ptr */
 234        const struct rcar_drif_format *fmt;
 235
 236        /* Device tree SYNC properties */
 237        u32 mdr1;
 238
 239        /* Internals */
 240        struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
 241        unsigned long hw_ch_mask;       /* Enabled channels per DT */
 242        unsigned long cur_ch_mask;      /* Used channels for an SDR FMT */
 243        u32 num_hw_ch;                  /* Num of DT enabled channels */
 244        u32 num_cur_ch;                 /* Num of used channels */
 245        u32 hwbuf_size;                 /* Each DMA buffer size */
 246        u32 produced;                   /* Buffers produced by sdr dev */
 247};
 248
 249/* Register access functions */
 250static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
 251{
 252        writel(data, ch->base + offset);
 253}
 254
 255static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
 256{
 257        return readl(ch->base + offset);
 258}
 259
 260/* Release DMA channels */
 261static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr)
 262{
 263        unsigned int i;
 264
 265        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
 266                if (sdr->ch[i]->dmach) {
 267                        dma_release_channel(sdr->ch[i]->dmach);
 268                        sdr->ch[i]->dmach = NULL;
 269                }
 270}
 271
 272/* Allocate DMA channels */
 273static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr)
 274{
 275        struct dma_slave_config dma_cfg;
 276        unsigned int i;
 277        int ret = -ENODEV;
 278
 279        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 280                struct rcar_drif *ch = sdr->ch[i];
 281
 282                ch->dmach = dma_request_slave_channel(&ch->pdev->dev, "rx");
 283                if (!ch->dmach) {
 284                        rdrif_err(sdr, "ch%u: dma channel req failed\n", i);
 285                        goto dmach_error;
 286                }
 287
 288                /* Configure slave */
 289                memset(&dma_cfg, 0, sizeof(dma_cfg));
 290                dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
 291                dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 292                ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
 293                if (ret) {
 294                        rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
 295                        goto dmach_error;
 296                }
 297        }
 298        return 0;
 299
 300dmach_error:
 301        rcar_drif_release_dmachannels(sdr);
 302        return ret;
 303}
 304
 305/* Release queued vb2 buffers */
 306static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr,
 307                                          enum vb2_buffer_state state)
 308{
 309        struct rcar_drif_frame_buf *fbuf, *tmp;
 310        unsigned long flags;
 311
 312        spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
 313        list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) {
 314                list_del(&fbuf->list);
 315                vb2_buffer_done(&fbuf->vb.vb2_buf, state);
 316        }
 317        spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
 318}
 319
 320/* Set MDR defaults */
 321static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr)
 322{
 323        unsigned int i;
 324
 325        /* Set defaults for enabled internal channels */
 326        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 327                /* Refer MSIOF section in manual for this register setting */
 328                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
 329                                RCAR_DRIF_SITMDR1_PCON);
 330
 331                /* Setup MDR1 value */
 332                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
 333
 334                rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
 335                          i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
 336        }
 337}
 338
 339/* Set DRIF receive format */
 340static int rcar_drif_set_format(struct rcar_drif_sdr *sdr)
 341{
 342        unsigned int i;
 343
 344        rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n",
 345                  sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch);
 346
 347        /* Sanity check */
 348        if (sdr->fmt->num_ch > sdr->num_cur_ch) {
 349                rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n",
 350                          sdr->fmt->num_ch, sdr->num_cur_ch);
 351                return -EINVAL;
 352        }
 353
 354        /* Setup group, bitlen & wdcnt */
 355        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 356                u32 mdr;
 357
 358                /* Two groups */
 359                mdr = RCAR_DRIF_MDR_GRPCNT(2) |
 360                        RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
 361                        RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
 362                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
 363
 364                mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
 365                        RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
 366                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
 367
 368                rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
 369                          i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
 370                          rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
 371        }
 372        return 0;
 373}
 374
 375/* Release DMA buffers */
 376static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr)
 377{
 378        unsigned int i;
 379
 380        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 381                struct rcar_drif *ch = sdr->ch[i];
 382
 383                /* First entry contains the dma buf ptr */
 384                if (ch->buf[0].addr) {
 385                        dma_free_coherent(&ch->pdev->dev,
 386                                sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
 387                                ch->buf[0].addr, ch->dma_handle);
 388                        ch->buf[0].addr = NULL;
 389                }
 390        }
 391}
 392
 393/* Request DMA buffers */
 394static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr)
 395{
 396        int ret = -ENOMEM;
 397        unsigned int i, j;
 398        void *addr;
 399
 400        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 401                struct rcar_drif *ch = sdr->ch[i];
 402
 403                /* Allocate DMA buffers */
 404                addr = dma_alloc_coherent(&ch->pdev->dev,
 405                                sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
 406                                &ch->dma_handle, GFP_KERNEL);
 407                if (!addr) {
 408                        rdrif_err(sdr,
 409                        "ch%u: dma alloc failed. num hwbufs %u size %u\n",
 410                        i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
 411                        goto error;
 412                }
 413
 414                /* Split the chunk and populate bufctxt */
 415                for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) {
 416                        ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
 417                        ch->buf[j].status = 0;
 418                }
 419        }
 420        return 0;
 421error:
 422        return ret;
 423}
 424
 425/* Setup vb_queue minimum buffer requirements */
 426static int rcar_drif_queue_setup(struct vb2_queue *vq,
 427                        unsigned int *num_buffers, unsigned int *num_planes,
 428                        unsigned int sizes[], struct device *alloc_devs[])
 429{
 430        struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
 431
 432        /* Need at least 16 buffers */
 433        if (vq->num_buffers + *num_buffers < 16)
 434                *num_buffers = 16 - vq->num_buffers;
 435
 436        *num_planes = 1;
 437        sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize);
 438        rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]);
 439
 440        return 0;
 441}
 442
 443/* Enqueue buffer */
 444static void rcar_drif_buf_queue(struct vb2_buffer *vb)
 445{
 446        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 447        struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue);
 448        struct rcar_drif_frame_buf *fbuf =
 449                        container_of(vbuf, struct rcar_drif_frame_buf, vb);
 450        unsigned long flags;
 451
 452        rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index);
 453        spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
 454        list_add_tail(&fbuf->list, &sdr->queued_bufs);
 455        spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
 456}
 457
 458/* Get a frame buf from list */
 459static struct rcar_drif_frame_buf *
 460rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr)
 461{
 462        struct rcar_drif_frame_buf *fbuf;
 463        unsigned long flags;
 464
 465        spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
 466        fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct
 467                                        rcar_drif_frame_buf, list);
 468        if (!fbuf) {
 469                /*
 470                 * App is late in enqueing buffers. Samples lost & there will
 471                 * be a gap in sequence number when app recovers
 472                 */
 473                rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced);
 474                spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
 475                return NULL;
 476        }
 477        list_del(&fbuf->list);
 478        spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
 479
 480        return fbuf;
 481}
 482
 483/* Helpers to set/clear buf pair status */
 484static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf)
 485{
 486        return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE);
 487}
 488
 489static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf)
 490{
 491        return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW);
 492}
 493
 494static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf,
 495                                        unsigned int bit)
 496{
 497        unsigned int i;
 498
 499        for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
 500                buf[i]->status &= ~bit;
 501}
 502
 503/* Channel DMA complete */
 504static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
 505{
 506        u32 str;
 507
 508        ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
 509
 510        /* Check for DRIF errors */
 511        str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
 512        if (unlikely(str & RCAR_DRIF_RFOVF)) {
 513                /* Writing the same clears it */
 514                rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
 515
 516                /* Overflow: some samples are lost */
 517                ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
 518        }
 519}
 520
 521/* DMA callback for each stage */
 522static void rcar_drif_dma_complete(void *dma_async_param)
 523{
 524        struct rcar_drif *ch = dma_async_param;
 525        struct rcar_drif_sdr *sdr = ch->sdr;
 526        struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL];
 527        struct rcar_drif_frame_buf *fbuf;
 528        bool overflow = false;
 529        u32 idx, produced;
 530        unsigned int i;
 531
 532        spin_lock(&sdr->dma_lock);
 533
 534        /* DMA can be terminated while the callback was waiting on lock */
 535        if (!vb2_is_streaming(&sdr->vb_queue)) {
 536                spin_unlock(&sdr->dma_lock);
 537                return;
 538        }
 539
 540        idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS;
 541        rcar_drif_channel_complete(ch, idx);
 542
 543        if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) {
 544                buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
 545                                &ch->buf[idx];
 546                buf[1] = ch->num ? &ch->buf[idx] :
 547                                to_rcar_drif_buf_pair(sdr, ch->num, idx);
 548
 549                /* Check if both DMA buffers are done */
 550                if (!rcar_drif_bufs_done(buf)) {
 551                        spin_unlock(&sdr->dma_lock);
 552                        return;
 553                }
 554
 555                /* Clear buf done status */
 556                rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE);
 557
 558                if (rcar_drif_bufs_overflow(buf)) {
 559                        overflow = true;
 560                        /* Clear the flag in status */
 561                        rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW);
 562                }
 563        } else {
 564                buf[0] = &ch->buf[idx];
 565                if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) {
 566                        overflow = true;
 567                        /* Clear the flag in status */
 568                        buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW;
 569                }
 570        }
 571
 572        /* Buffer produced for consumption */
 573        produced = sdr->produced++;
 574        spin_unlock(&sdr->dma_lock);
 575
 576        rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
 577
 578        /* Get fbuf */
 579        fbuf = rcar_drif_get_fbuf(sdr);
 580        if (!fbuf)
 581                return;
 582
 583        for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
 584                memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) +
 585                       i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size);
 586
 587        fbuf->vb.field = V4L2_FIELD_NONE;
 588        fbuf->vb.sequence = produced;
 589        fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
 590        vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize);
 591
 592        /* Set error state on overflow */
 593        vb2_buffer_done(&fbuf->vb.vb2_buf,
 594                        overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
 595}
 596
 597static int rcar_drif_qbuf(struct rcar_drif *ch)
 598{
 599        struct rcar_drif_sdr *sdr = ch->sdr;
 600        dma_addr_t addr = ch->dma_handle;
 601        struct dma_async_tx_descriptor *rxd;
 602        dma_cookie_t cookie;
 603        int ret = -EIO;
 604
 605        /* Setup cyclic DMA with given buffers */
 606        rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
 607                                        sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
 608                                        sdr->hwbuf_size, DMA_DEV_TO_MEM,
 609                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 610        if (!rxd) {
 611                rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
 612                return ret;
 613        }
 614
 615        /* Submit descriptor */
 616        rxd->callback = rcar_drif_dma_complete;
 617        rxd->callback_param = ch;
 618        cookie = dmaengine_submit(rxd);
 619        if (dma_submit_error(cookie)) {
 620                rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
 621                return ret;
 622        }
 623
 624        dma_async_issue_pending(ch->dmach);
 625        return 0;
 626}
 627
 628/* Enable reception */
 629static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr)
 630{
 631        unsigned int i;
 632        u32 ctr;
 633        int ret;
 634
 635        /*
 636         * When both internal channels are enabled, they can be synchronized
 637         * only by the master
 638         */
 639
 640        /* Enable receive */
 641        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 642                ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
 643                ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE |
 644                         RCAR_DRIF_SICTR_RX_EN);
 645                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
 646        }
 647
 648        /* Check receive enabled */
 649        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 650                ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
 651                                ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000);
 652                if (ret) {
 653                        rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
 654                                  rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
 655                        break;
 656                }
 657        }
 658        return ret;
 659}
 660
 661/* Disable reception */
 662static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr)
 663{
 664        unsigned int i;
 665        u32 ctr;
 666        int ret;
 667
 668        /* Disable receive */
 669        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 670                ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
 671                ctr &= ~RCAR_DRIF_SICTR_RX_EN;
 672                rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
 673        }
 674
 675        /* Check receive disabled */
 676        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 677                ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
 678                                ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000);
 679                if (ret)
 680                        dev_warn(&sdr->vdev->dev,
 681                        "ch%u: failed to disable rx. ctr 0x%08x\n",
 682                        i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
 683        }
 684}
 685
 686/* Stop channel */
 687static void rcar_drif_stop_channel(struct rcar_drif *ch)
 688{
 689        /* Disable DMA receive interrupt */
 690        rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
 691
 692        /* Terminate all DMA transfers */
 693        dmaengine_terminate_sync(ch->dmach);
 694}
 695
 696/* Stop receive operation */
 697static void rcar_drif_stop(struct rcar_drif_sdr *sdr)
 698{
 699        unsigned int i;
 700
 701        /* Disable Rx */
 702        rcar_drif_disable_rx(sdr);
 703
 704        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
 705                rcar_drif_stop_channel(sdr->ch[i]);
 706}
 707
 708/* Start channel */
 709static int rcar_drif_start_channel(struct rcar_drif *ch)
 710{
 711        struct rcar_drif_sdr *sdr = ch->sdr;
 712        u32 ctr, str;
 713        int ret;
 714
 715        /* Reset receive */
 716        rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
 717        ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
 718                                 !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000);
 719        if (ret) {
 720                rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
 721                          ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
 722                return ret;
 723        }
 724
 725        /* Queue buffers for DMA */
 726        ret = rcar_drif_qbuf(ch);
 727        if (ret)
 728                return ret;
 729
 730        /* Clear status register flags */
 731        str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR |
 732                RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF;
 733        rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
 734
 735        /* Enable DMA receive interrupt */
 736        rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
 737
 738        return ret;
 739}
 740
 741/* Start receive operation */
 742static int rcar_drif_start(struct rcar_drif_sdr *sdr)
 743{
 744        unsigned long enabled = 0;
 745        unsigned int i;
 746        int ret;
 747
 748        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 749                ret = rcar_drif_start_channel(sdr->ch[i]);
 750                if (ret)
 751                        goto start_error;
 752                enabled |= BIT(i);
 753        }
 754
 755        ret = rcar_drif_enable_rx(sdr);
 756        if (ret)
 757                goto enable_error;
 758
 759        sdr->produced = 0;
 760        return ret;
 761
 762enable_error:
 763        rcar_drif_disable_rx(sdr);
 764start_error:
 765        for_each_rcar_drif_channel(i, &enabled)
 766                rcar_drif_stop_channel(sdr->ch[i]);
 767
 768        return ret;
 769}
 770
 771/* Start streaming */
 772static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count)
 773{
 774        struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
 775        unsigned long enabled = 0;
 776        unsigned int i;
 777        int ret;
 778
 779        mutex_lock(&sdr->v4l2_mutex);
 780
 781        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
 782                ret = clk_prepare_enable(sdr->ch[i]->clk);
 783                if (ret)
 784                        goto error;
 785                enabled |= BIT(i);
 786        }
 787
 788        /* Set default MDRx settings */
 789        rcar_drif_set_mdr1(sdr);
 790
 791        /* Set new format */
 792        ret = rcar_drif_set_format(sdr);
 793        if (ret)
 794                goto error;
 795
 796        if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL)
 797                sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL;
 798        else
 799                sdr->hwbuf_size = sdr->fmt->buffersize;
 800
 801        rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n",
 802                RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
 803
 804        /* Alloc DMA channel */
 805        ret = rcar_drif_alloc_dmachannels(sdr);
 806        if (ret)
 807                goto error;
 808
 809        /* Request buffers */
 810        ret = rcar_drif_request_buf(sdr);
 811        if (ret)
 812                goto error;
 813
 814        /* Start Rx */
 815        ret = rcar_drif_start(sdr);
 816        if (ret)
 817                goto error;
 818
 819        mutex_unlock(&sdr->v4l2_mutex);
 820
 821        return ret;
 822
 823error:
 824        rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED);
 825        rcar_drif_release_buf(sdr);
 826        rcar_drif_release_dmachannels(sdr);
 827        for_each_rcar_drif_channel(i, &enabled)
 828                clk_disable_unprepare(sdr->ch[i]->clk);
 829
 830        mutex_unlock(&sdr->v4l2_mutex);
 831
 832        return ret;
 833}
 834
 835/* Stop streaming */
 836static void rcar_drif_stop_streaming(struct vb2_queue *vq)
 837{
 838        struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
 839        unsigned int i;
 840
 841        mutex_lock(&sdr->v4l2_mutex);
 842
 843        /* Stop hardware streaming */
 844        rcar_drif_stop(sdr);
 845
 846        /* Return all queued buffers to vb2 */
 847        rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR);
 848
 849        /* Release buf */
 850        rcar_drif_release_buf(sdr);
 851
 852        /* Release DMA channel resources */
 853        rcar_drif_release_dmachannels(sdr);
 854
 855        for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
 856                clk_disable_unprepare(sdr->ch[i]->clk);
 857
 858        mutex_unlock(&sdr->v4l2_mutex);
 859}
 860
 861/* Vb2 ops */
 862static const struct vb2_ops rcar_drif_vb2_ops = {
 863        .queue_setup            = rcar_drif_queue_setup,
 864        .buf_queue              = rcar_drif_buf_queue,
 865        .start_streaming        = rcar_drif_start_streaming,
 866        .stop_streaming         = rcar_drif_stop_streaming,
 867        .wait_prepare           = vb2_ops_wait_prepare,
 868        .wait_finish            = vb2_ops_wait_finish,
 869};
 870
 871static int rcar_drif_querycap(struct file *file, void *fh,
 872                              struct v4l2_capability *cap)
 873{
 874        struct rcar_drif_sdr *sdr = video_drvdata(file);
 875
 876        strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
 877        strlcpy(cap->card, sdr->vdev->name, sizeof(cap->card));
 878        snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
 879                 sdr->vdev->name);
 880
 881        return 0;
 882}
 883
 884static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr)
 885{
 886        unsigned int i;
 887
 888        for (i = 0; i < ARRAY_SIZE(formats); i++) {
 889                /* Matching fmt based on required channels is set as default */
 890                if (sdr->num_hw_ch == formats[i].num_ch) {
 891                        sdr->fmt = &formats[i];
 892                        sdr->cur_ch_mask = sdr->hw_ch_mask;
 893                        sdr->num_cur_ch = sdr->num_hw_ch;
 894                        dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n",
 895                                i, sdr->cur_ch_mask, sdr->num_cur_ch);
 896                        return 0;
 897                }
 898        }
 899        return -EINVAL;
 900}
 901
 902static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv,
 903                                      struct v4l2_fmtdesc *f)
 904{
 905        if (f->index >= ARRAY_SIZE(formats))
 906                return -EINVAL;
 907
 908        f->pixelformat = formats[f->index].pixelformat;
 909
 910        return 0;
 911}
 912
 913static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv,
 914                                   struct v4l2_format *f)
 915{
 916        struct rcar_drif_sdr *sdr = video_drvdata(file);
 917
 918        f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
 919        f->fmt.sdr.buffersize = sdr->fmt->buffersize;
 920
 921        return 0;
 922}
 923
 924static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv,
 925                                   struct v4l2_format *f)
 926{
 927        struct rcar_drif_sdr *sdr = video_drvdata(file);
 928        struct vb2_queue *q = &sdr->vb_queue;
 929        unsigned int i;
 930
 931        if (vb2_is_busy(q))
 932                return -EBUSY;
 933
 934        for (i = 0; i < ARRAY_SIZE(formats); i++) {
 935                if (formats[i].pixelformat == f->fmt.sdr.pixelformat)
 936                        break;
 937        }
 938
 939        if (i == ARRAY_SIZE(formats))
 940                i = 0;          /* Set the 1st format as default on no match */
 941
 942        sdr->fmt = &formats[i];
 943        f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
 944        f->fmt.sdr.buffersize = formats[i].buffersize;
 945        memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
 946
 947        /*
 948         * If a format demands one channel only out of two
 949         * enabled channels, pick the 0th channel.
 950         */
 951        if (formats[i].num_ch < sdr->num_hw_ch) {
 952                sdr->cur_ch_mask = BIT(0);
 953                sdr->num_cur_ch = formats[i].num_ch;
 954        } else {
 955                sdr->cur_ch_mask = sdr->hw_ch_mask;
 956                sdr->num_cur_ch = sdr->num_hw_ch;
 957        }
 958
 959        rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n",
 960                  i, sdr->cur_ch_mask, sdr->num_cur_ch);
 961
 962        return 0;
 963}
 964
 965static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv,
 966                                     struct v4l2_format *f)
 967{
 968        unsigned int i;
 969
 970        for (i = 0; i < ARRAY_SIZE(formats); i++) {
 971                if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
 972                        f->fmt.sdr.buffersize = formats[i].buffersize;
 973                        return 0;
 974                }
 975        }
 976
 977        f->fmt.sdr.pixelformat = formats[0].pixelformat;
 978        f->fmt.sdr.buffersize = formats[0].buffersize;
 979        memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
 980
 981        return 0;
 982}
 983
 984/* Tuner subdev ioctls */
 985static int rcar_drif_enum_freq_bands(struct file *file, void *priv,
 986                                     struct v4l2_frequency_band *band)
 987{
 988        struct rcar_drif_sdr *sdr = video_drvdata(file);
 989
 990        return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band);
 991}
 992
 993static int rcar_drif_g_frequency(struct file *file, void *priv,
 994                                 struct v4l2_frequency *f)
 995{
 996        struct rcar_drif_sdr *sdr = video_drvdata(file);
 997
 998        return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f);
 999}
1000
1001static int rcar_drif_s_frequency(struct file *file, void *priv,
1002                                 const struct v4l2_frequency *f)
1003{
1004        struct rcar_drif_sdr *sdr = video_drvdata(file);
1005
1006        return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f);
1007}
1008
1009static int rcar_drif_g_tuner(struct file *file, void *priv,
1010                             struct v4l2_tuner *vt)
1011{
1012        struct rcar_drif_sdr *sdr = video_drvdata(file);
1013
1014        return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt);
1015}
1016
1017static int rcar_drif_s_tuner(struct file *file, void *priv,
1018                             const struct v4l2_tuner *vt)
1019{
1020        struct rcar_drif_sdr *sdr = video_drvdata(file);
1021
1022        return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt);
1023}
1024
1025static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = {
1026        .vidioc_querycap          = rcar_drif_querycap,
1027
1028        .vidioc_enum_fmt_sdr_cap  = rcar_drif_enum_fmt_sdr_cap,
1029        .vidioc_g_fmt_sdr_cap     = rcar_drif_g_fmt_sdr_cap,
1030        .vidioc_s_fmt_sdr_cap     = rcar_drif_s_fmt_sdr_cap,
1031        .vidioc_try_fmt_sdr_cap   = rcar_drif_try_fmt_sdr_cap,
1032
1033        .vidioc_reqbufs           = vb2_ioctl_reqbufs,
1034        .vidioc_create_bufs       = vb2_ioctl_create_bufs,
1035        .vidioc_prepare_buf       = vb2_ioctl_prepare_buf,
1036        .vidioc_querybuf          = vb2_ioctl_querybuf,
1037        .vidioc_qbuf              = vb2_ioctl_qbuf,
1038        .vidioc_dqbuf             = vb2_ioctl_dqbuf,
1039
1040        .vidioc_streamon          = vb2_ioctl_streamon,
1041        .vidioc_streamoff         = vb2_ioctl_streamoff,
1042
1043        .vidioc_s_frequency       = rcar_drif_s_frequency,
1044        .vidioc_g_frequency       = rcar_drif_g_frequency,
1045        .vidioc_s_tuner           = rcar_drif_s_tuner,
1046        .vidioc_g_tuner           = rcar_drif_g_tuner,
1047        .vidioc_enum_freq_bands   = rcar_drif_enum_freq_bands,
1048        .vidioc_subscribe_event   = v4l2_ctrl_subscribe_event,
1049        .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1050        .vidioc_log_status        = v4l2_ctrl_log_status,
1051};
1052
1053static const struct v4l2_file_operations rcar_drif_fops = {
1054        .owner                    = THIS_MODULE,
1055        .open                     = v4l2_fh_open,
1056        .release                  = vb2_fop_release,
1057        .read                     = vb2_fop_read,
1058        .poll                     = vb2_fop_poll,
1059        .mmap                     = vb2_fop_mmap,
1060        .unlocked_ioctl           = video_ioctl2,
1061};
1062
1063static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr)
1064{
1065        int ret;
1066
1067        /* Init video_device structure */
1068        sdr->vdev = video_device_alloc();
1069        if (!sdr->vdev)
1070                return -ENOMEM;
1071
1072        snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF");
1073        sdr->vdev->fops = &rcar_drif_fops;
1074        sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops;
1075        sdr->vdev->release = video_device_release;
1076        sdr->vdev->lock = &sdr->v4l2_mutex;
1077        sdr->vdev->queue = &sdr->vb_queue;
1078        sdr->vdev->queue->lock = &sdr->vb_queue_mutex;
1079        sdr->vdev->ctrl_handler = &sdr->ctrl_hdl;
1080        sdr->vdev->v4l2_dev = &sdr->v4l2_dev;
1081        sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER |
1082                V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1083        video_set_drvdata(sdr->vdev, sdr);
1084
1085        /* Register V4L2 SDR device */
1086        ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1);
1087        if (ret) {
1088                video_device_release(sdr->vdev);
1089                sdr->vdev = NULL;
1090                dev_err(sdr->dev, "failed video_register_device (%d)\n", ret);
1091        }
1092
1093        return ret;
1094}
1095
1096static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr)
1097{
1098        video_unregister_device(sdr->vdev);
1099        sdr->vdev = NULL;
1100}
1101
1102/* Sub-device bound callback */
1103static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier,
1104                                   struct v4l2_subdev *subdev,
1105                                   struct v4l2_async_subdev *asd)
1106{
1107        struct rcar_drif_sdr *sdr =
1108                container_of(notifier, struct rcar_drif_sdr, notifier);
1109
1110        if (sdr->ep.asd.match.fwnode.fwnode !=
1111            of_fwnode_handle(subdev->dev->of_node)) {
1112                rdrif_err(sdr, "subdev %s cannot bind\n", subdev->name);
1113                return -EINVAL;
1114        }
1115
1116        v4l2_set_subdev_hostdata(subdev, sdr);
1117        sdr->ep.subdev = subdev;
1118        rdrif_dbg(sdr, "bound asd %s\n", subdev->name);
1119
1120        return 0;
1121}
1122
1123/* Sub-device unbind callback */
1124static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier,
1125                                   struct v4l2_subdev *subdev,
1126                                   struct v4l2_async_subdev *asd)
1127{
1128        struct rcar_drif_sdr *sdr =
1129                container_of(notifier, struct rcar_drif_sdr, notifier);
1130
1131        if (sdr->ep.subdev != subdev) {
1132                rdrif_err(sdr, "subdev %s is not bound\n", subdev->name);
1133                return;
1134        }
1135
1136        /* Free ctrl handler if initialized */
1137        v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1138        sdr->v4l2_dev.ctrl_handler = NULL;
1139        sdr->ep.subdev = NULL;
1140
1141        rcar_drif_sdr_unregister(sdr);
1142        rdrif_dbg(sdr, "unbind asd %s\n", subdev->name);
1143}
1144
1145/* Sub-device registered notification callback */
1146static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
1147{
1148        struct rcar_drif_sdr *sdr =
1149                container_of(notifier, struct rcar_drif_sdr, notifier);
1150        int ret;
1151
1152        /*
1153         * The subdev tested at this point uses 4 controls. Using 10 as a worst
1154         * case scenario hint. When less controls are needed there will be some
1155         * unused memory and when more controls are needed the framework uses
1156         * hash to manage controls within this number.
1157         */
1158        ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10);
1159        if (ret)
1160                return -ENOMEM;
1161
1162        sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl;
1163        ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev);
1164        if (ret) {
1165                rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret);
1166                goto error;
1167        }
1168
1169        ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl,
1170                                    sdr->ep.subdev->ctrl_handler, NULL);
1171        if (ret) {
1172                rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret);
1173                goto error;
1174        }
1175
1176        ret = rcar_drif_sdr_register(sdr);
1177        if (ret)
1178                goto error;
1179
1180        return ret;
1181
1182error:
1183        v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1184
1185        return ret;
1186}
1187
1188/* Read endpoint properties */
1189static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
1190                                        struct fwnode_handle *fwnode)
1191{
1192        u32 val;
1193
1194        /* Set the I2S defaults for SIRMDR1*/
1195        sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST |
1196                RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0;
1197
1198        /* Parse sync polarity from endpoint */
1199        if (!fwnode_property_read_u32(fwnode, "sync-active", &val))
1200                sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH :
1201                        RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW;
1202        else
1203                sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */
1204
1205        dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1);
1206}
1207
1208/* Parse sub-devs (tuner) to find a matching device */
1209static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr)
1210{
1211        struct v4l2_async_notifier *notifier = &sdr->notifier;
1212        struct fwnode_handle *fwnode, *ep;
1213
1214        notifier->subdevs = devm_kzalloc(sdr->dev, sizeof(*notifier->subdevs),
1215                                         GFP_KERNEL);
1216        if (!notifier->subdevs)
1217                return -ENOMEM;
1218
1219        ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node),
1220                                            NULL);
1221        if (!ep)
1222                return 0;
1223
1224        notifier->subdevs[notifier->num_subdevs] = &sdr->ep.asd;
1225        fwnode = fwnode_graph_get_remote_port_parent(ep);
1226        if (!fwnode) {
1227                dev_warn(sdr->dev, "bad remote port parent\n");
1228                fwnode_handle_put(ep);
1229                return -EINVAL;
1230        }
1231
1232        sdr->ep.asd.match.fwnode.fwnode = fwnode;
1233        sdr->ep.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1234        notifier->num_subdevs++;
1235
1236        /* Get the endpoint properties */
1237        rcar_drif_get_ep_properties(sdr, ep);
1238
1239        fwnode_handle_put(fwnode);
1240        fwnode_handle_put(ep);
1241
1242        return 0;
1243}
1244
1245/* Check if the given device is the primary bond */
1246static bool rcar_drif_primary_bond(struct platform_device *pdev)
1247{
1248        return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond");
1249}
1250
1251/* Check if both devices of the bond are enabled */
1252static struct device_node *rcar_drif_bond_enabled(struct platform_device *p)
1253{
1254        struct device_node *np;
1255
1256        np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0);
1257        if (np && of_device_is_available(np))
1258                return np;
1259
1260        return NULL;
1261}
1262
1263/* Check if the bonded device is probed */
1264static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr,
1265                                    struct device_node *np)
1266{
1267        struct platform_device *pdev;
1268        struct rcar_drif *ch;
1269        int ret = 0;
1270
1271        pdev = of_find_device_by_node(np);
1272        if (!pdev) {
1273                dev_err(sdr->dev, "failed to get bonded device from node\n");
1274                return -ENODEV;
1275        }
1276
1277        device_lock(&pdev->dev);
1278        ch = platform_get_drvdata(pdev);
1279        if (ch) {
1280                /* Update sdr data in the bonded device */
1281                ch->sdr = sdr;
1282
1283                /* Update sdr with bonded device data */
1284                sdr->ch[ch->num] = ch;
1285                sdr->hw_ch_mask |= BIT(ch->num);
1286        } else {
1287                /* Defer */
1288                dev_info(sdr->dev, "defer probe\n");
1289                ret = -EPROBE_DEFER;
1290        }
1291        device_unlock(&pdev->dev);
1292
1293        put_device(&pdev->dev);
1294
1295        return ret;
1296}
1297
1298/* V4L2 SDR device probe */
1299static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
1300{
1301        int ret;
1302
1303        /* Validate any supported format for enabled channels */
1304        ret = rcar_drif_set_default_format(sdr);
1305        if (ret) {
1306                dev_err(sdr->dev, "failed to set default format\n");
1307                return ret;
1308        }
1309
1310        /* Set defaults */
1311        sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE;
1312
1313        mutex_init(&sdr->v4l2_mutex);
1314        mutex_init(&sdr->vb_queue_mutex);
1315        spin_lock_init(&sdr->queued_bufs_lock);
1316        spin_lock_init(&sdr->dma_lock);
1317        INIT_LIST_HEAD(&sdr->queued_bufs);
1318
1319        /* Init videobuf2 queue structure */
1320        sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
1321        sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1322        sdr->vb_queue.drv_priv = sdr;
1323        sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf);
1324        sdr->vb_queue.ops = &rcar_drif_vb2_ops;
1325        sdr->vb_queue.mem_ops = &vb2_vmalloc_memops;
1326        sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1327
1328        /* Init videobuf2 queue */
1329        ret = vb2_queue_init(&sdr->vb_queue);
1330        if (ret) {
1331                dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret);
1332                return ret;
1333        }
1334
1335        /* Register the v4l2_device */
1336        ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev);
1337        if (ret) {
1338                dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret);
1339                return ret;
1340        }
1341
1342        /*
1343         * Parse subdevs after v4l2_device_register because if the subdev
1344         * is already probed, bound and complete will be called immediately
1345         */
1346        ret = rcar_drif_parse_subdevs(sdr);
1347        if (ret)
1348                goto error;
1349
1350        sdr->notifier.bound = rcar_drif_notify_bound;
1351        sdr->notifier.unbind = rcar_drif_notify_unbind;
1352        sdr->notifier.complete = rcar_drif_notify_complete;
1353
1354        /* Register notifier */
1355        ret = v4l2_async_notifier_register(&sdr->v4l2_dev, &sdr->notifier);
1356        if (ret < 0) {
1357                dev_err(sdr->dev, "failed: notifier register ret %d\n", ret);
1358                goto error;
1359        }
1360
1361        return ret;
1362
1363error:
1364        v4l2_device_unregister(&sdr->v4l2_dev);
1365
1366        return ret;
1367}
1368
1369/* V4L2 SDR device remove */
1370static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr)
1371{
1372        v4l2_async_notifier_unregister(&sdr->notifier);
1373        v4l2_device_unregister(&sdr->v4l2_dev);
1374}
1375
1376/* DRIF channel probe */
1377static int rcar_drif_probe(struct platform_device *pdev)
1378{
1379        struct rcar_drif_sdr *sdr;
1380        struct device_node *np;
1381        struct rcar_drif *ch;
1382        struct resource *res;
1383        int ret;
1384
1385        /* Reserve memory for enabled channel */
1386        ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1387        if (!ch)
1388                return -ENOMEM;
1389
1390        ch->pdev = pdev;
1391
1392        /* Module clock */
1393        ch->clk = devm_clk_get(&pdev->dev, "fck");
1394        if (IS_ERR(ch->clk)) {
1395                ret = PTR_ERR(ch->clk);
1396                dev_err(&pdev->dev, "clk get failed (%d)\n", ret);
1397                return ret;
1398        }
1399
1400        /* Register map */
1401        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1402        ch->base = devm_ioremap_resource(&pdev->dev, res);
1403        if (IS_ERR(ch->base)) {
1404                ret = PTR_ERR(ch->base);
1405                dev_err(&pdev->dev, "ioremap failed (%d)\n", ret);
1406                return ret;
1407        }
1408        ch->start = res->start;
1409        platform_set_drvdata(pdev, ch);
1410
1411        /* Check if both channels of the bond are enabled */
1412        np = rcar_drif_bond_enabled(pdev);
1413        if (np) {
1414                /* Check if current channel acting as primary-bond */
1415                if (!rcar_drif_primary_bond(pdev)) {
1416                        ch->num = 1;    /* Primary bond is channel 0 always */
1417                        of_node_put(np);
1418                        return 0;
1419                }
1420        }
1421
1422        /* Reserve memory for SDR structure */
1423        sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL);
1424        if (!sdr) {
1425                of_node_put(np);
1426                return -ENOMEM;
1427        }
1428        ch->sdr = sdr;
1429        sdr->dev = &pdev->dev;
1430
1431        /* Establish links between SDR and channel(s) */
1432        sdr->ch[ch->num] = ch;
1433        sdr->hw_ch_mask = BIT(ch->num);
1434        if (np) {
1435                /* Check if bonded device is ready */
1436                ret = rcar_drif_bond_available(sdr, np);
1437                of_node_put(np);
1438                if (ret)
1439                        return ret;
1440        }
1441        sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask);
1442
1443        return rcar_drif_sdr_probe(sdr);
1444}
1445
1446/* DRIF channel remove */
1447static int rcar_drif_remove(struct platform_device *pdev)
1448{
1449        struct rcar_drif *ch = platform_get_drvdata(pdev);
1450        struct rcar_drif_sdr *sdr = ch->sdr;
1451
1452        /* Channel 0 will be the SDR instance */
1453        if (ch->num)
1454                return 0;
1455
1456        /* SDR instance */
1457        rcar_drif_sdr_remove(sdr);
1458
1459        return 0;
1460}
1461
1462/* FIXME: Implement suspend/resume support */
1463static int __maybe_unused rcar_drif_suspend(struct device *dev)
1464{
1465        return 0;
1466}
1467
1468static int __maybe_unused rcar_drif_resume(struct device *dev)
1469{
1470        return 0;
1471}
1472
1473static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend,
1474                         rcar_drif_resume);
1475
1476static const struct of_device_id rcar_drif_of_table[] = {
1477        { .compatible = "renesas,rcar-gen3-drif" },
1478        { }
1479};
1480MODULE_DEVICE_TABLE(of, rcar_drif_of_table);
1481
1482#define RCAR_DRIF_DRV_NAME "rcar_drif"
1483static struct platform_driver rcar_drif_driver = {
1484        .driver = {
1485                .name = RCAR_DRIF_DRV_NAME,
1486                .of_match_table = of_match_ptr(rcar_drif_of_table),
1487                .pm = &rcar_drif_pm_ops,
1488                },
1489        .probe = rcar_drif_probe,
1490        .remove = rcar_drif_remove,
1491};
1492
1493module_platform_driver(rcar_drif_driver);
1494
1495MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver");
1496MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME);
1497MODULE_LICENSE("GPL v2");
1498MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1499