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49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/types.h>
56#include <linux/pci.h>
57#include <linux/kdev_t.h>
58#include <linux/blkdev.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h>
61#include <linux/dma-mapping.h>
62#include <linux/kthread.h>
63#include <scsi/scsi_host.h>
64
65#include "mptbase.h"
66#include "lsi/mpi_log_fc.h"
67
68
69#define my_NAME "Fusion MPT base driver"
70#define my_VERSION MPT_LINUX_VERSION_COMMON
71#define MYNAM "mptbase"
72
73MODULE_AUTHOR(MODULEAUTHOR);
74MODULE_DESCRIPTION(my_NAME);
75MODULE_LICENSE("GPL");
76MODULE_VERSION(my_VERSION);
77
78
79
80
81
82static int mpt_msi_enable_spi;
83module_param(mpt_msi_enable_spi, int, 0);
84MODULE_PARM_DESC(mpt_msi_enable_spi,
85 " Enable MSI Support for SPI controllers (default=0)");
86
87static int mpt_msi_enable_fc;
88module_param(mpt_msi_enable_fc, int, 0);
89MODULE_PARM_DESC(mpt_msi_enable_fc,
90 " Enable MSI Support for FC controllers (default=0)");
91
92static int mpt_msi_enable_sas;
93module_param(mpt_msi_enable_sas, int, 0);
94MODULE_PARM_DESC(mpt_msi_enable_sas,
95 " Enable MSI Support for SAS controllers (default=0)");
96
97static int mpt_channel_mapping;
98module_param(mpt_channel_mapping, int, 0);
99MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
100
101static int mpt_debug_level;
102static int mpt_set_debug_level(const char *val, struct kernel_param *kp);
103module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
104 &mpt_debug_level, 0600);
105MODULE_PARM_DESC(mpt_debug_level,
106 " debug level - refer to mptdebug.h - (default=0)");
107
108int mpt_fwfault_debug;
109EXPORT_SYMBOL(mpt_fwfault_debug);
110module_param(mpt_fwfault_debug, int, 0600);
111MODULE_PARM_DESC(mpt_fwfault_debug,
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
113
114static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
115 [MPT_MAX_CALLBACKNAME_LEN+1];
116
117#ifdef MFCNT
118static int mfcounter = 0;
119#define PRINT_MF_COUNT 20000
120#endif
121
122
123
124
125
126
127#define WHOINIT_UNKNOWN 0xAA
128
129
130
131
132
133
134LIST_HEAD(ioc_list);
135
136static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
137
138static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
139
140static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
141
142static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
143static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
144
145#ifdef CONFIG_PROC_FS
146static struct proc_dir_entry *mpt_proc_root_dir;
147#endif
148
149
150
151
152static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
153static u8 last_drv_idx;
154
155
156
157
158
159static irqreturn_t mpt_interrupt(int irq, void *bus_id);
160static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
161 MPT_FRAME_HDR *reply);
162static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
163 u32 *req, int replyBytes, u16 *u16reply, int maxwait,
164 int sleepFlag);
165static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
166static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
167static void mpt_adapter_disable(MPT_ADAPTER *ioc);
168static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
169
170static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
171static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
172static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
173static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
174static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
175static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
176static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
177static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
178static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
179static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
180static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
181static int PrimeIocFifos(MPT_ADAPTER *ioc);
182static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
183static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
184static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
185static int GetLanConfigPages(MPT_ADAPTER *ioc);
186static int GetIoUnitPage2(MPT_ADAPTER *ioc);
187int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
188static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
189static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
190static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
191static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
192static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
193static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
194 int sleepFlag);
195static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
196static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
197static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
198
199#ifdef CONFIG_PROC_FS
200static const struct file_operations mpt_summary_proc_fops;
201static const struct file_operations mpt_version_proc_fops;
202static const struct file_operations mpt_iocinfo_proc_fops;
203#endif
204static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
205
206static int ProcessEventNotification(MPT_ADAPTER *ioc,
207 EventNotificationReply_t *evReply, int *evHandlers);
208static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
209static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
210static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
211static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
212static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
213static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
214
215
216static int __init fusion_init (void);
217static void __exit fusion_exit (void);
218
219#define CHIPREG_READ32(addr) readl_relaxed(addr)
220#define CHIPREG_READ32_dmasync(addr) readl(addr)
221#define CHIPREG_WRITE32(addr,val) writel(val, addr)
222#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
223#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
224
225static void
226pci_disable_io_access(struct pci_dev *pdev)
227{
228 u16 command_reg;
229
230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
231 command_reg &= ~1;
232 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
233}
234
235static void
236pci_enable_io_access(struct pci_dev *pdev)
237{
238 u16 command_reg;
239
240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
241 command_reg |= 1;
242 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
243}
244
245static int mpt_set_debug_level(const char *val, struct kernel_param *kp)
246{
247 int ret = param_set_int(val, kp);
248 MPT_ADAPTER *ioc;
249
250 if (ret)
251 return ret;
252
253 list_for_each_entry(ioc, &ioc_list, list)
254 ioc->debug_level = mpt_debug_level;
255 return 0;
256}
257
258
259
260
261
262
263
264static u8
265mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
266{
267 u8 cb_idx;
268
269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
270 if (MptDriverClass[cb_idx] == dclass)
271 return cb_idx;
272 return 0;
273}
274
275
276
277
278
279
280
281static int
282mpt_is_discovery_complete(MPT_ADAPTER *ioc)
283{
284 ConfigExtendedPageHeader_t hdr;
285 CONFIGPARMS cfg;
286 SasIOUnitPage0_t *buffer;
287 dma_addr_t dma_handle;
288 int rc = 0;
289
290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
291 memset(&cfg, 0, sizeof(CONFIGPARMS));
292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
295 cfg.cfghdr.ehdr = &hdr;
296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
297
298 if ((mpt_config(ioc, &cfg)))
299 goto out;
300 if (!hdr.ExtPageLength)
301 goto out;
302
303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
304 &dma_handle);
305 if (!buffer)
306 goto out;
307
308 cfg.physAddr = dma_handle;
309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
310
311 if ((mpt_config(ioc, &cfg)))
312 goto out_free_consistent;
313
314 if (!(buffer->PhyData[0].PortFlags &
315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
316 rc = 1;
317
318 out_free_consistent:
319 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
320 buffer, dma_handle);
321 out:
322 return rc;
323}
324
325
326
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328
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330
331
332
333static int mpt_remove_dead_ioc_func(void *arg)
334{
335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
336 struct pci_dev *pdev;
337
338 if ((ioc == NULL))
339 return -1;
340
341 pdev = ioc->pcidev;
342 if ((pdev == NULL))
343 return -1;
344
345 pci_stop_and_remove_bus_device_locked(pdev);
346 return 0;
347}
348
349
350
351
352
353
354
355
356static void
357mpt_fault_reset_work(struct work_struct *work)
358{
359 MPT_ADAPTER *ioc =
360 container_of(work, MPT_ADAPTER, fault_reset_work.work);
361 u32 ioc_raw_state;
362 int rc;
363 unsigned long flags;
364 MPT_SCSI_HOST *hd;
365 struct task_struct *p;
366
367 if (ioc->ioc_reset_in_progress || !ioc->active)
368 goto out;
369
370
371 ioc_raw_state = mpt_GetIocState(ioc, 0);
372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
374 ioc->name, __func__);
375
376
377
378
379
380
381
382
383 hd = shost_priv(ioc->sh);
384 ioc->schedule_dead_ioc_flush_running_cmds(hd);
385
386
387 p = kthread_run(mpt_remove_dead_ioc_func, ioc,
388 "mpt_dead_ioc_%d", ioc->id);
389 if (IS_ERR(p)) {
390 printk(MYIOC_s_ERR_FMT
391 "%s: Running mpt_dead_ioc thread failed !\n",
392 ioc->name, __func__);
393 } else {
394 printk(MYIOC_s_WARN_FMT
395 "%s: Running mpt_dead_ioc thread success !\n",
396 ioc->name, __func__);
397 }
398 return;
399 }
400
401 if ((ioc_raw_state & MPI_IOC_STATE_MASK)
402 == MPI_IOC_STATE_FAULT) {
403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
406 ioc->name, __func__);
407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
409 __func__, (rc == 0) ? "success" : "failed");
410 ioc_raw_state = mpt_GetIocState(ioc, 0);
411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
413 "reset (%04xh)\n", ioc->name, ioc_raw_state &
414 MPI_DOORBELL_DATA_MASK);
415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
416 if ((mpt_is_discovery_complete(ioc))) {
417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
418 "discovery_quiesce_io flag\n", ioc->name));
419 ioc->sas_discovery_quiesce_io = 0;
420 }
421 }
422
423 out:
424
425
426
427 if (ioc->alt_ioc)
428 ioc = ioc->alt_ioc;
429
430
431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
432 if (ioc->reset_work_q)
433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
434 msecs_to_jiffies(MPT_POLLING_INTERVAL));
435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
436}
437
438
439
440
441
442static void
443mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
444{
445 MPT_FRAME_HDR *mf = NULL;
446 MPT_FRAME_HDR *mr = NULL;
447 u16 req_idx = 0;
448 u8 cb_idx;
449
450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
451 ioc->name, pa));
452
453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
455 req_idx = pa & 0x0000FFFF;
456 cb_idx = (pa & 0x00FF0000) >> 16;
457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
458 break;
459 case MPI_CONTEXT_REPLY_TYPE_LAN:
460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
461
462
463
464
465
466
467
468
469
470 if ((pa & 0x58000000) == 0x58000000) {
471 req_idx = pa & 0x0000FFFF;
472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
473 mpt_free_msg_frame(ioc, mf);
474 mb();
475 return;
476 break;
477 }
478 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
479 break;
480 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
481 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
482 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
483 break;
484 default:
485 cb_idx = 0;
486 BUG();
487 }
488
489
490 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
491 MptCallbacks[cb_idx] == NULL) {
492 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
493 __func__, ioc->name, cb_idx);
494 goto out;
495 }
496
497 if (MptCallbacks[cb_idx](ioc, mf, mr))
498 mpt_free_msg_frame(ioc, mf);
499 out:
500 mb();
501}
502
503static void
504mpt_reply(MPT_ADAPTER *ioc, u32 pa)
505{
506 MPT_FRAME_HDR *mf;
507 MPT_FRAME_HDR *mr;
508 u16 req_idx;
509 u8 cb_idx;
510 int freeme;
511
512 u32 reply_dma_low;
513 u16 ioc_stat;
514
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524
525 reply_dma_low = (pa <<= 1);
526 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
527 (reply_dma_low - ioc->reply_frames_low_dma));
528
529 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
530 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
531 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
532
533 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
534 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
535 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
536
537
538
539 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
540 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
541 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
542 if (ioc->bus_type == FC)
543 mpt_fc_log_info(ioc, log_info);
544 else if (ioc->bus_type == SPI)
545 mpt_spi_log_info(ioc, log_info);
546 else if (ioc->bus_type == SAS)
547 mpt_sas_log_info(ioc, log_info, cb_idx);
548 }
549
550 if (ioc_stat & MPI_IOCSTATUS_MASK)
551 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
552
553
554 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
555 MptCallbacks[cb_idx] == NULL) {
556 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
557 __func__, ioc->name, cb_idx);
558 freeme = 0;
559 goto out;
560 }
561
562 freeme = MptCallbacks[cb_idx](ioc, mf, mr);
563
564 out:
565
566 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
567
568 if (freeme)
569 mpt_free_msg_frame(ioc, mf);
570 mb();
571}
572
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589
590static irqreturn_t
591mpt_interrupt(int irq, void *bus_id)
592{
593 MPT_ADAPTER *ioc = bus_id;
594 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
595
596 if (pa == 0xFFFFFFFF)
597 return IRQ_NONE;
598
599
600
601
602 do {
603 if (pa & MPI_ADDRESS_REPLY_A_BIT)
604 mpt_reply(ioc, pa);
605 else
606 mpt_turbo_reply(ioc, pa);
607 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
608 } while (pa != 0xFFFFFFFF);
609
610 return IRQ_HANDLED;
611}
612
613
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622
623
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625
626
627static int
628mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
629{
630 EventNotificationReply_t *pEventReply;
631 u8 event;
632 int evHandlers;
633 int freereq = 1;
634
635 switch (reply->u.hdr.Function) {
636 case MPI_FUNCTION_EVENT_NOTIFICATION:
637 pEventReply = (EventNotificationReply_t *)reply;
638 evHandlers = 0;
639 ProcessEventNotification(ioc, pEventReply, &evHandlers);
640 event = le32_to_cpu(pEventReply->Event) & 0xFF;
641 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
642 freereq = 0;
643 if (event != MPI_EVENT_EVENT_CHANGE)
644 break;
645 case MPI_FUNCTION_CONFIG:
646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
649 memcpy(ioc->mptbase_cmds.reply, reply,
650 min(MPT_DEFAULT_FRAME_SIZE,
651 4 * reply->u.reply.MsgLength));
652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
654 complete(&ioc->mptbase_cmds.done);
655 } else
656 freereq = 0;
657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
658 freereq = 1;
659 break;
660 case MPI_FUNCTION_EVENT_ACK:
661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
662 "EventAck reply received\n", ioc->name));
663 break;
664 default:
665 printk(MYIOC_s_ERR_FMT
666 "Unexpected msg function (=%02Xh) reply received!\n",
667 ioc->name, reply->u.hdr.Function);
668 break;
669 }
670
671
672
673
674
675 return freereq;
676}
677
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699u8
700mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
701{
702 u8 cb_idx;
703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
704
705
706
707
708
709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
710 if (MptCallbacks[cb_idx] == NULL) {
711 MptCallbacks[cb_idx] = cbfunc;
712 MptDriverClass[cb_idx] = dclass;
713 MptEvHandlers[cb_idx] = NULL;
714 last_drv_idx = cb_idx;
715 strlcpy(MptCallbacksName[cb_idx], func_name,
716 MPT_MAX_CALLBACKNAME_LEN+1);
717 break;
718 }
719 }
720
721 return last_drv_idx;
722}
723
724
725
726
727
728
729
730
731
732void
733mpt_deregister(u8 cb_idx)
734{
735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
736 MptCallbacks[cb_idx] = NULL;
737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
738 MptEvHandlers[cb_idx] = NULL;
739
740 last_drv_idx++;
741 }
742}
743
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754
755int
756mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
757{
758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
759 return -1;
760
761 MptEvHandlers[cb_idx] = ev_cbfunc;
762 return 0;
763}
764
765
766
767
768
769
770
771
772
773
774void
775mpt_event_deregister(u8 cb_idx)
776{
777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
778 return;
779
780 MptEvHandlers[cb_idx] = NULL;
781}
782
783
784
785
786
787
788
789
790
791
792
793
794int
795mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
796{
797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
798 return -1;
799
800 MptResetHandlers[cb_idx] = reset_func;
801 return 0;
802}
803
804
805
806
807
808
809
810
811
812
813void
814mpt_reset_deregister(u8 cb_idx)
815{
816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
817 return;
818
819 MptResetHandlers[cb_idx] = NULL;
820}
821
822
823
824
825
826
827
828int
829mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
830{
831 MPT_ADAPTER *ioc;
832 const struct pci_device_id *id;
833
834 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
835 return -EINVAL;
836
837 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
838
839
840 list_for_each_entry(ioc, &ioc_list, list) {
841 id = ioc->pcidev->driver ?
842 ioc->pcidev->driver->id_table : NULL;
843 if (dd_cbfunc->probe)
844 dd_cbfunc->probe(ioc->pcidev, id);
845 }
846
847 return 0;
848}
849
850
851
852
853
854
855void
856mpt_device_driver_deregister(u8 cb_idx)
857{
858 struct mpt_pci_driver *dd_cbfunc;
859 MPT_ADAPTER *ioc;
860
861 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
862 return;
863
864 dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
865
866 list_for_each_entry(ioc, &ioc_list, list) {
867 if (dd_cbfunc->remove)
868 dd_cbfunc->remove(ioc->pcidev);
869 }
870
871 MptDeviceDriverHandlers[cb_idx] = NULL;
872}
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887MPT_FRAME_HDR*
888mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
889{
890 MPT_FRAME_HDR *mf;
891 unsigned long flags;
892 u16 req_idx;
893
894
895
896#ifdef MFCNT
897 if (!ioc->active)
898 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
899 "returning NULL!\n", ioc->name);
900#endif
901
902
903 if (!ioc->active)
904 return NULL;
905
906 spin_lock_irqsave(&ioc->FreeQlock, flags);
907 if (!list_empty(&ioc->FreeQ)) {
908 int req_offset;
909
910 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
911 u.frame.linkage.list);
912 list_del(&mf->u.frame.linkage.list);
913 mf->u.frame.linkage.arg1 = 0;
914 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
915 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
916
917 req_idx = req_offset / ioc->req_sz;
918 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
919 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
920
921 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
922#ifdef MFCNT
923 ioc->mfcnt++;
924#endif
925 }
926 else
927 mf = NULL;
928 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
929
930#ifdef MFCNT
931 if (mf == NULL)
932 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
933 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
934 ioc->req_depth);
935 mfcounter++;
936 if (mfcounter == PRINT_MF_COUNT)
937 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
938 ioc->mfcnt, ioc->req_depth);
939#endif
940
941 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
942 ioc->name, cb_idx, ioc->id, mf));
943 return mf;
944}
945
946
947
948
949
950
951
952
953
954
955
956void
957mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
958{
959 u32 mf_dma_addr;
960 int req_offset;
961 u16 req_idx;
962
963
964 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
965 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
966
967 req_idx = req_offset / ioc->req_sz;
968 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
969 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
970
971 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
972
973 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
974 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
975 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
976 ioc->RequestNB[req_idx]));
977 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
978}
979
980
981
982
983
984
985
986
987
988
989
990
991
992void
993mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
994{
995 u32 mf_dma_addr;
996 int req_offset;
997 u16 req_idx;
998
999
1000 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1001 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
1002 req_idx = req_offset / ioc->req_sz;
1003 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
1004 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
1005
1006 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
1007
1008 mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
1009 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
1010 ioc->name, mf_dma_addr, req_idx));
1011 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
1012}
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023void
1024mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
1025{
1026 unsigned long flags;
1027
1028
1029 spin_lock_irqsave(&ioc->FreeQlock, flags);
1030 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
1031 goto out;
1032
1033 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
1034 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
1035#ifdef MFCNT
1036 ioc->mfcnt--;
1037#endif
1038 out:
1039 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
1040}
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052static void
1053mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1054{
1055 SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
1056 pSge->FlagsLength = cpu_to_le32(flagslength);
1057 pSge->Address = cpu_to_le32(dma_addr);
1058}
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069static void
1070mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1071{
1072 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1073 pSge->Address.Low = cpu_to_le32
1074 (lower_32_bits(dma_addr));
1075 pSge->Address.High = cpu_to_le32
1076 (upper_32_bits(dma_addr));
1077 pSge->FlagsLength = cpu_to_le32
1078 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1079}
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090static void
1091mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1092{
1093 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1094 u32 tmp;
1095
1096 pSge->Address.Low = cpu_to_le32
1097 (lower_32_bits(dma_addr));
1098 tmp = (u32)(upper_32_bits(dma_addr));
1099
1100
1101
1102
1103 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
1104 flagslength |=
1105 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
1106 tmp |= (1<<31);
1107 if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
1108 printk(KERN_DEBUG "1078 P0M2 addressing for "
1109 "addr = 0x%llx len = %d\n",
1110 (unsigned long long)dma_addr,
1111 MPI_SGE_LENGTH(flagslength));
1112 }
1113
1114 pSge->Address.High = cpu_to_le32(tmp);
1115 pSge->FlagsLength = cpu_to_le32(
1116 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128static void
1129mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1130{
1131 SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
1132 pChain->Length = cpu_to_le16(length);
1133 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
1134 pChain->NextChainOffset = next;
1135 pChain->Address = cpu_to_le32(dma_addr);
1136}
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147static void
1148mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1149{
1150 SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
1151 u32 tmp = dma_addr & 0xFFFFFFFF;
1152
1153 pChain->Length = cpu_to_le16(length);
1154 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
1155 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
1156
1157 pChain->NextChainOffset = next;
1158
1159 pChain->Address.Low = cpu_to_le32(tmp);
1160 tmp = (u32)(upper_32_bits(dma_addr));
1161 pChain->Address.High = cpu_to_le32(tmp);
1162}
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181int
1182mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
1183{
1184 int r = 0;
1185 u8 *req_as_bytes;
1186 int ii;
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
1199 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
1200 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
1201 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
1202 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1203 }
1204
1205
1206 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1207
1208 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1209 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
1210 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
1211
1212
1213 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
1214 return ii;
1215 }
1216
1217
1218 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
1219 return -5;
1220
1221 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
1222 ioc->name, ii));
1223
1224 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1225
1226 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1227 return -2;
1228 }
1229
1230
1231 req_as_bytes = (u8 *) req;
1232 for (ii = 0; ii < reqBytes/4; ii++) {
1233 u32 word;
1234
1235 word = ((req_as_bytes[(ii*4) + 0] << 0) |
1236 (req_as_bytes[(ii*4) + 1] << 8) |
1237 (req_as_bytes[(ii*4) + 2] << 16) |
1238 (req_as_bytes[(ii*4) + 3] << 24));
1239 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
1240 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1241 r = -3;
1242 break;
1243 }
1244 }
1245
1246 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
1247 r = 0;
1248 else
1249 r = -4;
1250
1251
1252 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1253
1254 return r;
1255}
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276static int
1277mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
1278{
1279 int r = 0;
1280
1281
1282 if (CHIPREG_READ32(&ioc->chip->Doorbell)
1283 & MPI_DOORBELL_ACTIVE)
1284 return -1;
1285
1286 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1287
1288 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1289 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
1290 <<MPI_DOORBELL_FUNCTION_SHIFT) |
1291 (access_control_value<<12)));
1292
1293
1294 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1295 return -2;
1296 }else
1297 return 0;
1298}
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309static int
1310mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
1311{
1312 char *psge;
1313 int flags_length;
1314 u32 host_page_buffer_sz=0;
1315
1316 if(!ioc->HostPageBuffer) {
1317
1318 host_page_buffer_sz =
1319 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
1320
1321 if(!host_page_buffer_sz)
1322 return 0;
1323
1324
1325 while(host_page_buffer_sz > 0) {
1326
1327 if((ioc->HostPageBuffer = pci_alloc_consistent(
1328 ioc->pcidev,
1329 host_page_buffer_sz,
1330 &ioc->HostPageBuffer_dma)) != NULL) {
1331
1332 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
1333 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
1334 ioc->name, ioc->HostPageBuffer,
1335 (u32)ioc->HostPageBuffer_dma,
1336 host_page_buffer_sz));
1337 ioc->alloc_total += host_page_buffer_sz;
1338 ioc->HostPageBuffer_sz = host_page_buffer_sz;
1339 break;
1340 }
1341
1342 host_page_buffer_sz -= (4*1024);
1343 }
1344 }
1345
1346 if(!ioc->HostPageBuffer) {
1347 printk(MYIOC_s_ERR_FMT
1348 "Failed to alloc memory for host_page_buffer!\n",
1349 ioc->name);
1350 return -999;
1351 }
1352
1353 psge = (char *)&ioc_init->HostPageBufferSGE;
1354 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
1355 MPI_SGE_FLAGS_SYSTEM_ADDRESS |
1356 MPI_SGE_FLAGS_HOST_TO_IOC |
1357 MPI_SGE_FLAGS_END_OF_BUFFER;
1358 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
1359 flags_length |= ioc->HostPageBuffer_sz;
1360 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
1361 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
1362
1363return 0;
1364}
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378int
1379mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
1380{
1381 MPT_ADAPTER *ioc;
1382
1383 list_for_each_entry(ioc,&ioc_list,list) {
1384 if (ioc->id == iocid) {
1385 *iocpp =ioc;
1386 return iocid;
1387 }
1388 }
1389
1390 *iocpp = NULL;
1391 return -1;
1392}
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static const char*
1405mpt_get_product_name(u16 vendor, u16 device, u8 revision)
1406{
1407 char *product_str = NULL;
1408
1409 if (vendor == PCI_VENDOR_ID_BROCADE) {
1410 switch (device)
1411 {
1412 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1413 switch (revision)
1414 {
1415 case 0x00:
1416 product_str = "BRE040 A0";
1417 break;
1418 case 0x01:
1419 product_str = "BRE040 A1";
1420 break;
1421 default:
1422 product_str = "BRE040";
1423 break;
1424 }
1425 break;
1426 }
1427 goto out;
1428 }
1429
1430 switch (device)
1431 {
1432 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1433 product_str = "LSIFC909 B1";
1434 break;
1435 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1436 product_str = "LSIFC919 B0";
1437 break;
1438 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1439 product_str = "LSIFC929 B0";
1440 break;
1441 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1442 if (revision < 0x80)
1443 product_str = "LSIFC919X A0";
1444 else
1445 product_str = "LSIFC919XL A1";
1446 break;
1447 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1448 if (revision < 0x80)
1449 product_str = "LSIFC929X A0";
1450 else
1451 product_str = "LSIFC929XL A1";
1452 break;
1453 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1454 product_str = "LSIFC939X A1";
1455 break;
1456 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1457 product_str = "LSIFC949X A1";
1458 break;
1459 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1460 switch (revision)
1461 {
1462 case 0x00:
1463 product_str = "LSIFC949E A0";
1464 break;
1465 case 0x01:
1466 product_str = "LSIFC949E A1";
1467 break;
1468 default:
1469 product_str = "LSIFC949E";
1470 break;
1471 }
1472 break;
1473 case MPI_MANUFACTPAGE_DEVID_53C1030:
1474 switch (revision)
1475 {
1476 case 0x00:
1477 product_str = "LSI53C1030 A0";
1478 break;
1479 case 0x01:
1480 product_str = "LSI53C1030 B0";
1481 break;
1482 case 0x03:
1483 product_str = "LSI53C1030 B1";
1484 break;
1485 case 0x07:
1486 product_str = "LSI53C1030 B2";
1487 break;
1488 case 0x08:
1489 product_str = "LSI53C1030 C0";
1490 break;
1491 case 0x80:
1492 product_str = "LSI53C1030T A0";
1493 break;
1494 case 0x83:
1495 product_str = "LSI53C1030T A2";
1496 break;
1497 case 0x87:
1498 product_str = "LSI53C1030T A3";
1499 break;
1500 case 0xc1:
1501 product_str = "LSI53C1020A A1";
1502 break;
1503 default:
1504 product_str = "LSI53C1030";
1505 break;
1506 }
1507 break;
1508 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1509 switch (revision)
1510 {
1511 case 0x03:
1512 product_str = "LSI53C1035 A2";
1513 break;
1514 case 0x04:
1515 product_str = "LSI53C1035 B0";
1516 break;
1517 default:
1518 product_str = "LSI53C1035";
1519 break;
1520 }
1521 break;
1522 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1523 switch (revision)
1524 {
1525 case 0x00:
1526 product_str = "LSISAS1064 A1";
1527 break;
1528 case 0x01:
1529 product_str = "LSISAS1064 A2";
1530 break;
1531 case 0x02:
1532 product_str = "LSISAS1064 A3";
1533 break;
1534 case 0x03:
1535 product_str = "LSISAS1064 A4";
1536 break;
1537 default:
1538 product_str = "LSISAS1064";
1539 break;
1540 }
1541 break;
1542 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1543 switch (revision)
1544 {
1545 case 0x00:
1546 product_str = "LSISAS1064E A0";
1547 break;
1548 case 0x01:
1549 product_str = "LSISAS1064E B0";
1550 break;
1551 case 0x02:
1552 product_str = "LSISAS1064E B1";
1553 break;
1554 case 0x04:
1555 product_str = "LSISAS1064E B2";
1556 break;
1557 case 0x08:
1558 product_str = "LSISAS1064E B3";
1559 break;
1560 default:
1561 product_str = "LSISAS1064E";
1562 break;
1563 }
1564 break;
1565 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1566 switch (revision)
1567 {
1568 case 0x00:
1569 product_str = "LSISAS1068 A0";
1570 break;
1571 case 0x01:
1572 product_str = "LSISAS1068 B0";
1573 break;
1574 case 0x02:
1575 product_str = "LSISAS1068 B1";
1576 break;
1577 default:
1578 product_str = "LSISAS1068";
1579 break;
1580 }
1581 break;
1582 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1583 switch (revision)
1584 {
1585 case 0x00:
1586 product_str = "LSISAS1068E A0";
1587 break;
1588 case 0x01:
1589 product_str = "LSISAS1068E B0";
1590 break;
1591 case 0x02:
1592 product_str = "LSISAS1068E B1";
1593 break;
1594 case 0x04:
1595 product_str = "LSISAS1068E B2";
1596 break;
1597 case 0x08:
1598 product_str = "LSISAS1068E B3";
1599 break;
1600 default:
1601 product_str = "LSISAS1068E";
1602 break;
1603 }
1604 break;
1605 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1606 switch (revision)
1607 {
1608 case 0x00:
1609 product_str = "LSISAS1078 A0";
1610 break;
1611 case 0x01:
1612 product_str = "LSISAS1078 B0";
1613 break;
1614 case 0x02:
1615 product_str = "LSISAS1078 C0";
1616 break;
1617 case 0x03:
1618 product_str = "LSISAS1078 C1";
1619 break;
1620 case 0x04:
1621 product_str = "LSISAS1078 C2";
1622 break;
1623 default:
1624 product_str = "LSISAS1078";
1625 break;
1626 }
1627 break;
1628 }
1629
1630 out:
1631 return product_str;
1632}
1633
1634
1635
1636
1637
1638
1639static int
1640mpt_mapresources(MPT_ADAPTER *ioc)
1641{
1642 u8 __iomem *mem;
1643 int ii;
1644 resource_size_t mem_phys;
1645 unsigned long port;
1646 u32 msize;
1647 u32 psize;
1648 int r = -ENODEV;
1649 struct pci_dev *pdev;
1650
1651 pdev = ioc->pcidev;
1652 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1653 if (pci_enable_device_mem(pdev)) {
1654 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
1655 "failed\n", ioc->name);
1656 return r;
1657 }
1658 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
1659 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
1660 "MEM failed\n", ioc->name);
1661 goto out_pci_disable_device;
1662 }
1663
1664 if (sizeof(dma_addr_t) > 4) {
1665 const uint64_t required_mask = dma_get_required_mask
1666 (&pdev->dev);
1667 if (required_mask > DMA_BIT_MASK(32)
1668 && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1669 && !pci_set_consistent_dma_mask(pdev,
1670 DMA_BIT_MASK(64))) {
1671 ioc->dma_mask = DMA_BIT_MASK(64);
1672 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1673 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1674 ioc->name));
1675 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1676 && !pci_set_consistent_dma_mask(pdev,
1677 DMA_BIT_MASK(32))) {
1678 ioc->dma_mask = DMA_BIT_MASK(32);
1679 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1680 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1681 ioc->name));
1682 } else {
1683 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1684 ioc->name, pci_name(pdev));
1685 goto out_pci_release_region;
1686 }
1687 } else {
1688 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1689 && !pci_set_consistent_dma_mask(pdev,
1690 DMA_BIT_MASK(32))) {
1691 ioc->dma_mask = DMA_BIT_MASK(32);
1692 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1693 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1694 ioc->name));
1695 } else {
1696 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1697 ioc->name, pci_name(pdev));
1698 goto out_pci_release_region;
1699 }
1700 }
1701
1702 mem_phys = msize = 0;
1703 port = psize = 0;
1704 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
1705 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
1706 if (psize)
1707 continue;
1708
1709 port = pci_resource_start(pdev, ii);
1710 psize = pci_resource_len(pdev, ii);
1711 } else {
1712 if (msize)
1713 continue;
1714
1715 mem_phys = pci_resource_start(pdev, ii);
1716 msize = pci_resource_len(pdev, ii);
1717 }
1718 }
1719 ioc->mem_size = msize;
1720
1721 mem = NULL;
1722
1723
1724 mem = ioremap(mem_phys, msize);
1725 if (mem == NULL) {
1726 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
1727 " memory!\n", ioc->name);
1728 r = -EINVAL;
1729 goto out_pci_release_region;
1730 }
1731 ioc->memmap = mem;
1732 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
1733 ioc->name, mem, (unsigned long long)mem_phys));
1734
1735 ioc->mem_phys = mem_phys;
1736 ioc->chip = (SYSIF_REGS __iomem *)mem;
1737
1738
1739 ioc->pio_mem_phys = port;
1740 ioc->pio_chip = (SYSIF_REGS __iomem *)port;
1741
1742 return 0;
1743
1744out_pci_release_region:
1745 pci_release_selected_regions(pdev, ioc->bars);
1746out_pci_disable_device:
1747 pci_disable_device(pdev);
1748 return r;
1749}
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769int
1770mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1771{
1772 MPT_ADAPTER *ioc;
1773 u8 cb_idx;
1774 int r = -ENODEV;
1775 u8 pcixcmd;
1776 static int mpt_ids = 0;
1777#ifdef CONFIG_PROC_FS
1778 struct proc_dir_entry *dent;
1779#endif
1780
1781 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_ATOMIC);
1782 if (ioc == NULL) {
1783 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
1784 return -ENOMEM;
1785 }
1786
1787 ioc->id = mpt_ids++;
1788 sprintf(ioc->name, "ioc%d", ioc->id);
1789 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
1790
1791
1792
1793
1794
1795
1796 ioc->debug_level = mpt_debug_level;
1797 if (mpt_debug_level)
1798 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
1799
1800 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
1801
1802 ioc->pcidev = pdev;
1803 if (mpt_mapresources(ioc)) {
1804 goto out_free_ioc;
1805 }
1806
1807
1808
1809
1810 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
1811 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
1812 ioc->add_sge = &mpt_add_sge_64bit_1078;
1813 else
1814 ioc->add_sge = &mpt_add_sge_64bit;
1815 ioc->add_chain = &mpt_add_chain_64bit;
1816 ioc->sg_addr_size = 8;
1817 } else {
1818 ioc->add_sge = &mpt_add_sge;
1819 ioc->add_chain = &mpt_add_chain;
1820 ioc->sg_addr_size = 4;
1821 }
1822 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
1823
1824 ioc->alloc_total = sizeof(MPT_ADAPTER);
1825 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE;
1826 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
1827
1828
1829 spin_lock_init(&ioc->taskmgmt_lock);
1830 mutex_init(&ioc->internal_cmds.mutex);
1831 init_completion(&ioc->internal_cmds.done);
1832 mutex_init(&ioc->mptbase_cmds.mutex);
1833 init_completion(&ioc->mptbase_cmds.done);
1834 mutex_init(&ioc->taskmgmt_cmds.mutex);
1835 init_completion(&ioc->taskmgmt_cmds.done);
1836
1837
1838
1839 ioc->eventTypes = 0;
1840 ioc->eventContext = 0;
1841 ioc->eventLogSize = 0;
1842 ioc->events = NULL;
1843
1844#ifdef MFCNT
1845 ioc->mfcnt = 0;
1846#endif
1847
1848 ioc->sh = NULL;
1849 ioc->cached_fw = NULL;
1850
1851
1852
1853 memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
1854
1855
1856
1857 INIT_LIST_HEAD(&ioc->fc_rports);
1858
1859
1860 INIT_LIST_HEAD(&ioc->list);
1861
1862
1863
1864 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
1865
1866 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
1867 "mpt_poll_%d", ioc->id);
1868 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name,
1869 WQ_MEM_RECLAIM, 0);
1870 if (!ioc->reset_work_q) {
1871 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1872 ioc->name);
1873 r = -ENOMEM;
1874 goto out_unmap_resources;
1875 }
1876
1877 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
1878 ioc->name, &ioc->facts, &ioc->pfacts[0]));
1879
1880 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
1881 pdev->revision);
1882
1883 switch (pdev->device)
1884 {
1885 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1886 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1887 ioc->errata_flag_1064 = 1;
1888 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1889 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1890 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1891 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1892 ioc->bus_type = FC;
1893 break;
1894
1895 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1896 if (pdev->revision < XL_929) {
1897
1898
1899
1900 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1901 pcixcmd &= 0x8F;
1902 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1903 } else {
1904
1905
1906 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1907 pcixcmd |= 0x08;
1908 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1909 }
1910 ioc->bus_type = FC;
1911 break;
1912
1913 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1914
1915
1916
1917 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1918 pcixcmd &= 0x8F;
1919 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1920 ioc->bus_type = FC;
1921 break;
1922
1923 case MPI_MANUFACTPAGE_DEVID_53C1030:
1924
1925
1926
1927 if (pdev->revision < C0_1030) {
1928 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1929 pcixcmd &= 0x8F;
1930 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1931 }
1932
1933 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1934 ioc->bus_type = SPI;
1935 break;
1936
1937 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1938 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1939 ioc->errata_flag_1064 = 1;
1940 ioc->bus_type = SAS;
1941 break;
1942
1943 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1944 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1945 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1946 ioc->bus_type = SAS;
1947 break;
1948 }
1949
1950
1951 switch (ioc->bus_type) {
1952
1953 case SAS:
1954 ioc->msi_enable = mpt_msi_enable_sas;
1955 break;
1956
1957 case SPI:
1958 ioc->msi_enable = mpt_msi_enable_spi;
1959 break;
1960
1961 case FC:
1962 ioc->msi_enable = mpt_msi_enable_fc;
1963 break;
1964
1965 default:
1966 ioc->msi_enable = 0;
1967 break;
1968 }
1969
1970 ioc->fw_events_off = 1;
1971
1972 if (ioc->errata_flag_1064)
1973 pci_disable_io_access(pdev);
1974
1975 spin_lock_init(&ioc->FreeQlock);
1976
1977
1978 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1979 ioc->active = 0;
1980 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1981
1982
1983 pci_set_drvdata(ioc->pcidev, ioc);
1984
1985
1986 list_add_tail(&ioc->list, &ioc_list);
1987
1988
1989
1990 mpt_detect_bound_ports(ioc, pdev);
1991
1992 INIT_LIST_HEAD(&ioc->fw_event_list);
1993 spin_lock_init(&ioc->fw_event_lock);
1994 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
1995 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name,
1996 WQ_MEM_RECLAIM, 0);
1997 if (!ioc->fw_event_q) {
1998 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1999 ioc->name);
2000 r = -ENOMEM;
2001 goto out_remove_ioc;
2002 }
2003
2004 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2005 CAN_SLEEP)) != 0){
2006 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
2007 ioc->name, r);
2008
2009 destroy_workqueue(ioc->fw_event_q);
2010 ioc->fw_event_q = NULL;
2011
2012 list_del(&ioc->list);
2013 if (ioc->alt_ioc)
2014 ioc->alt_ioc->alt_ioc = NULL;
2015 iounmap(ioc->memmap);
2016 if (pci_is_enabled(pdev))
2017 pci_disable_device(pdev);
2018 if (r != -5)
2019 pci_release_selected_regions(pdev, ioc->bars);
2020
2021 destroy_workqueue(ioc->reset_work_q);
2022 ioc->reset_work_q = NULL;
2023
2024 kfree(ioc);
2025 return r;
2026 }
2027
2028
2029 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2030 if(MptDeviceDriverHandlers[cb_idx] &&
2031 MptDeviceDriverHandlers[cb_idx]->probe) {
2032 MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
2033 }
2034 }
2035
2036#ifdef CONFIG_PROC_FS
2037
2038
2039
2040 dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
2041 if (dent) {
2042 proc_create_data("info", S_IRUGO, dent, &mpt_iocinfo_proc_fops, ioc);
2043 proc_create_data("summary", S_IRUGO, dent, &mpt_summary_proc_fops, ioc);
2044 }
2045#endif
2046
2047 if (!ioc->alt_ioc)
2048 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
2049 msecs_to_jiffies(MPT_POLLING_INTERVAL));
2050
2051 return 0;
2052
2053out_remove_ioc:
2054 list_del(&ioc->list);
2055 if (ioc->alt_ioc)
2056 ioc->alt_ioc->alt_ioc = NULL;
2057
2058 destroy_workqueue(ioc->reset_work_q);
2059 ioc->reset_work_q = NULL;
2060
2061out_unmap_resources:
2062 iounmap(ioc->memmap);
2063 pci_disable_device(pdev);
2064 pci_release_selected_regions(pdev, ioc->bars);
2065
2066out_free_ioc:
2067 kfree(ioc);
2068
2069 return r;
2070}
2071
2072
2073
2074
2075
2076
2077
2078void
2079mpt_detach(struct pci_dev *pdev)
2080{
2081 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2082 char pname[64];
2083 u8 cb_idx;
2084 unsigned long flags;
2085 struct workqueue_struct *wq;
2086
2087
2088
2089
2090 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
2091 wq = ioc->reset_work_q;
2092 ioc->reset_work_q = NULL;
2093 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
2094 cancel_delayed_work(&ioc->fault_reset_work);
2095 destroy_workqueue(wq);
2096
2097 spin_lock_irqsave(&ioc->fw_event_lock, flags);
2098 wq = ioc->fw_event_q;
2099 ioc->fw_event_q = NULL;
2100 spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
2101 destroy_workqueue(wq);
2102
2103 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
2104 remove_proc_entry(pname, NULL);
2105 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
2106 remove_proc_entry(pname, NULL);
2107 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
2108 remove_proc_entry(pname, NULL);
2109
2110
2111 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2112 if(MptDeviceDriverHandlers[cb_idx] &&
2113 MptDeviceDriverHandlers[cb_idx]->remove) {
2114 MptDeviceDriverHandlers[cb_idx]->remove(pdev);
2115 }
2116 }
2117
2118
2119 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2120
2121 ioc->active = 0;
2122 synchronize_irq(pdev->irq);
2123
2124
2125 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2126
2127 CHIPREG_READ32(&ioc->chip->IntStatus);
2128
2129 mpt_adapter_dispose(ioc);
2130
2131}
2132
2133
2134
2135
2136#ifdef CONFIG_PM
2137
2138
2139
2140
2141
2142
2143int
2144mpt_suspend(struct pci_dev *pdev, pm_message_t state)
2145{
2146 u32 device_state;
2147 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2148
2149 device_state = pci_choose_state(pdev, state);
2150 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
2151 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2152 device_state);
2153
2154
2155 if(SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
2156 printk(MYIOC_s_ERR_FMT
2157 "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
2158 }
2159
2160
2161 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2162 ioc->active = 0;
2163
2164
2165 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2166
2167 free_irq(ioc->pci_irq, ioc);
2168 if (ioc->msi_enable)
2169 pci_disable_msi(ioc->pcidev);
2170 ioc->pci_irq = -1;
2171 pci_save_state(pdev);
2172 pci_disable_device(pdev);
2173 pci_release_selected_regions(pdev, ioc->bars);
2174 pci_set_power_state(pdev, device_state);
2175 return 0;
2176}
2177
2178
2179
2180
2181
2182
2183int
2184mpt_resume(struct pci_dev *pdev)
2185{
2186 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2187 u32 device_state = pdev->current_state;
2188 int recovery_state;
2189 int err;
2190
2191 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
2192 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2193 device_state);
2194
2195 pci_set_power_state(pdev, PCI_D0);
2196 pci_enable_wake(pdev, PCI_D0, 0);
2197 pci_restore_state(pdev);
2198 ioc->pcidev = pdev;
2199 err = mpt_mapresources(ioc);
2200 if (err)
2201 return err;
2202
2203 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
2204 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
2205 ioc->add_sge = &mpt_add_sge_64bit_1078;
2206 else
2207 ioc->add_sge = &mpt_add_sge_64bit;
2208 ioc->add_chain = &mpt_add_chain_64bit;
2209 ioc->sg_addr_size = 8;
2210 } else {
2211
2212 ioc->add_sge = &mpt_add_sge;
2213 ioc->add_chain = &mpt_add_chain;
2214 ioc->sg_addr_size = 4;
2215 }
2216 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
2217
2218 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
2219 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
2220 CHIPREG_READ32(&ioc->chip->Doorbell));
2221
2222
2223
2224
2225
2226
2227
2228
2229 if (ioc->bus_type == SAS && (pdev->device ==
2230 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
2231 MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
2232 if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
2233 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
2234 ioc->name);
2235 goto out;
2236 }
2237 }
2238
2239
2240 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
2241 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2242 CAN_SLEEP);
2243 if (recovery_state != 0)
2244 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
2245 "error:[%x]\n", ioc->name, recovery_state);
2246 else
2247 printk(MYIOC_s_INFO_FMT
2248 "pci-resume: success\n", ioc->name);
2249 out:
2250 return 0;
2251
2252}
2253#endif
2254
2255static int
2256mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
2257{
2258 if ((MptDriverClass[index] == MPTSPI_DRIVER &&
2259 ioc->bus_type != SPI) ||
2260 (MptDriverClass[index] == MPTFC_DRIVER &&
2261 ioc->bus_type != FC) ||
2262 (MptDriverClass[index] == MPTSAS_DRIVER &&
2263 ioc->bus_type != SAS))
2264
2265
2266 return 0;
2267 return (MptResetHandlers[index])(ioc, reset_phase);
2268}
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292static int
2293mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
2294{
2295 int hard_reset_done = 0;
2296 int alt_ioc_ready = 0;
2297 int hard;
2298 int rc=0;
2299 int ii;
2300 int ret = 0;
2301 int reset_alt_ioc_active = 0;
2302 int irq_allocated = 0;
2303 u8 *a;
2304
2305 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
2306 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
2307
2308
2309 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2310 ioc->active = 0;
2311
2312 if (ioc->alt_ioc) {
2313 if (ioc->alt_ioc->active ||
2314 reason == MPT_HOSTEVENT_IOC_RECOVER) {
2315 reset_alt_ioc_active = 1;
2316
2317
2318
2319 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2320 0xFFFFFFFF);
2321 ioc->alt_ioc->active = 0;
2322 }
2323 }
2324
2325 hard = 1;
2326 if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
2327 hard = 0;
2328
2329 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
2330 if (hard_reset_done == -4) {
2331 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
2332 ioc->name);
2333
2334 if (reset_alt_ioc_active && ioc->alt_ioc) {
2335
2336 dprintk(ioc, printk(MYIOC_s_INFO_FMT
2337 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
2338 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
2339 ioc->alt_ioc->active = 1;
2340 }
2341
2342 } else {
2343 printk(MYIOC_s_WARN_FMT
2344 "NOT READY WARNING!\n", ioc->name);
2345 }
2346 ret = -1;
2347 goto out;
2348 }
2349
2350
2351
2352
2353 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
2354 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
2355 alt_ioc_ready = 1;
2356 else
2357 printk(MYIOC_s_WARN_FMT
2358 ": alt-ioc Not ready WARNING!\n",
2359 ioc->alt_ioc->name);
2360 }
2361
2362 for (ii=0; ii<5; ii++) {
2363
2364 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
2365 break;
2366 }
2367
2368
2369 if (ii == 5) {
2370 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2371 "Retry IocFacts failed rc=%x\n", ioc->name, rc));
2372 ret = -2;
2373 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2374 MptDisplayIocCapabilities(ioc);
2375 }
2376
2377 if (alt_ioc_ready) {
2378 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
2379 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2380 "Initial Alt IocFacts failed rc=%x\n",
2381 ioc->name, rc));
2382
2383
2384 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
2385 }
2386 if (rc) {
2387 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2388 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
2389 alt_ioc_ready = 0;
2390 reset_alt_ioc_active = 0;
2391 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2392 MptDisplayIocCapabilities(ioc->alt_ioc);
2393 }
2394 }
2395
2396 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
2397 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
2398 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2399 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
2400 IORESOURCE_IO);
2401 if (pci_enable_device(ioc->pcidev))
2402 return -5;
2403 if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
2404 "mpt"))
2405 return -5;
2406 }
2407
2408
2409
2410
2411
2412
2413 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2414 ioc->pci_irq = -1;
2415 if (ioc->pcidev->irq) {
2416 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
2417 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
2418 ioc->name);
2419 else
2420 ioc->msi_enable = 0;
2421 rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
2422 IRQF_SHARED, ioc->name, ioc);
2423 if (rc < 0) {
2424 printk(MYIOC_s_ERR_FMT "Unable to allocate "
2425 "interrupt %d!\n",
2426 ioc->name, ioc->pcidev->irq);
2427 if (ioc->msi_enable)
2428 pci_disable_msi(ioc->pcidev);
2429 ret = -EBUSY;
2430 goto out;
2431 }
2432 irq_allocated = 1;
2433 ioc->pci_irq = ioc->pcidev->irq;
2434 pci_set_master(ioc->pcidev);
2435 pci_set_drvdata(ioc->pcidev, ioc);
2436 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2437 "installed at interrupt %d\n", ioc->name,
2438 ioc->pcidev->irq));
2439 }
2440 }
2441
2442
2443
2444
2445
2446
2447 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
2448 ioc->name));
2449 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
2450 ret = -3;
2451
2452
2453
2454
2455 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
2456 ioc->name));
2457 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
2458 ret = -4;
2459
2460 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
2461 printk(MYIOC_s_WARN_FMT
2462 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
2463 ioc->alt_ioc->name, rc);
2464 alt_ioc_ready = 0;
2465 reset_alt_ioc_active = 0;
2466 }
2467
2468 if (alt_ioc_ready) {
2469 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
2470 alt_ioc_ready = 0;
2471 reset_alt_ioc_active = 0;
2472 printk(MYIOC_s_WARN_FMT
2473 ": alt-ioc: (%d) init failure WARNING!\n",
2474 ioc->alt_ioc->name, rc);
2475 }
2476 }
2477
2478 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
2479 if (ioc->upload_fw) {
2480 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2481 "firmware upload required!\n", ioc->name));
2482
2483
2484
2485 if (ret == 0) {
2486 rc = mpt_do_upload(ioc, sleepFlag);
2487 if (rc == 0) {
2488 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
2489
2490
2491
2492
2493
2494
2495
2496 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2497 "mpt_upload: alt_%s has cached_fw=%p \n",
2498 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
2499 ioc->cached_fw = NULL;
2500 }
2501 } else {
2502 printk(MYIOC_s_WARN_FMT
2503 "firmware upload failure!\n", ioc->name);
2504 ret = -6;
2505 }
2506 }
2507 }
2508 }
2509
2510
2511
2512
2513 if ((ret == 0) && (!ioc->facts.EventState)) {
2514 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2515 "SendEventNotification\n",
2516 ioc->name));
2517 ret = SendEventNotification(ioc, 1, sleepFlag);
2518 }
2519
2520 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
2521 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
2522
2523 if (ret == 0) {
2524
2525 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
2526 ioc->active = 1;
2527 }
2528 if (rc == 0) {
2529 if (reset_alt_ioc_active && ioc->alt_ioc) {
2530
2531 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
2532 "reply irq re-enabled\n",
2533 ioc->alt_ioc->name));
2534 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2535 MPI_HIM_DIM);
2536 ioc->alt_ioc->active = 1;
2537 }
2538 }
2539
2540
2541
2542
2543
2544
2545
2546
2547 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2548
2549
2550
2551
2552 mutex_init(&ioc->raid_data.inactive_list_mutex);
2553 INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
2554
2555 switch (ioc->bus_type) {
2556
2557 case SAS:
2558
2559 if(ioc->facts.IOCExceptions &
2560 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
2561 ret = mptbase_sas_persist_operation(ioc,
2562 MPI_SAS_OP_CLEAR_NOT_PRESENT);
2563 if(ret != 0)
2564 goto out;
2565 }
2566
2567
2568
2569 mpt_findImVolumes(ioc);
2570
2571
2572
2573 mpt_read_ioc_pg_1(ioc);
2574
2575 break;
2576
2577 case FC:
2578 if ((ioc->pfacts[0].ProtocolFlags &
2579 MPI_PORTFACTS_PROTOCOL_LAN) &&
2580 (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
2581
2582
2583
2584
2585 (void) GetLanConfigPages(ioc);
2586 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
2587 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2588 "LanAddr = %pMR\n", ioc->name, a));
2589 }
2590 break;
2591
2592 case SPI:
2593
2594
2595 mpt_GetScsiPortSettings(ioc, 0);
2596
2597
2598
2599 mpt_readScsiDevicePageHeaders(ioc, 0);
2600
2601
2602
2603 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
2604 mpt_findImVolumes(ioc);
2605
2606
2607
2608 mpt_read_ioc_pg_1(ioc);
2609
2610 mpt_read_ioc_pg_4(ioc);
2611
2612 break;
2613 }
2614
2615 GetIoUnitPage2(ioc);
2616 mpt_get_manufacturing_pg_0(ioc);
2617 }
2618
2619 out:
2620 if ((ret != 0) && irq_allocated) {
2621 free_irq(ioc->pci_irq, ioc);
2622 if (ioc->msi_enable)
2623 pci_disable_msi(ioc->pcidev);
2624 }
2625 return ret;
2626}
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641static void
2642mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
2643{
2644 struct pci_dev *peer=NULL;
2645 unsigned int slot = PCI_SLOT(pdev->devfn);
2646 unsigned int func = PCI_FUNC(pdev->devfn);
2647 MPT_ADAPTER *ioc_srch;
2648
2649 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
2650 " searching for devfn match on %x or %x\n",
2651 ioc->name, pci_name(pdev), pdev->bus->number,
2652 pdev->devfn, func-1, func+1));
2653
2654 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
2655 if (!peer) {
2656 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
2657 if (!peer)
2658 return;
2659 }
2660
2661 list_for_each_entry(ioc_srch, &ioc_list, list) {
2662 struct pci_dev *_pcidev = ioc_srch->pcidev;
2663 if (_pcidev == peer) {
2664
2665 if (ioc->alt_ioc != NULL) {
2666 printk(MYIOC_s_WARN_FMT
2667 "Oops, already bound (%s <==> %s)!\n",
2668 ioc->name, ioc->name, ioc->alt_ioc->name);
2669 break;
2670 } else if (ioc_srch->alt_ioc != NULL) {
2671 printk(MYIOC_s_WARN_FMT
2672 "Oops, already bound (%s <==> %s)!\n",
2673 ioc_srch->name, ioc_srch->name,
2674 ioc_srch->alt_ioc->name);
2675 break;
2676 }
2677 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2678 "FOUND! binding %s <==> %s\n",
2679 ioc->name, ioc->name, ioc_srch->name));
2680 ioc_srch->alt_ioc = ioc;
2681 ioc->alt_ioc = ioc_srch;
2682 }
2683 }
2684 pci_dev_put(peer);
2685}
2686
2687
2688
2689
2690
2691
2692static void
2693mpt_adapter_disable(MPT_ADAPTER *ioc)
2694{
2695 int sz;
2696 int ret;
2697
2698 if (ioc->cached_fw != NULL) {
2699 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2700 "%s: Pushing FW onto adapter\n", __func__, ioc->name));
2701 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
2702 ioc->cached_fw, CAN_SLEEP)) < 0) {
2703 printk(MYIOC_s_WARN_FMT
2704 ": firmware downloadboot failure (%d)!\n",
2705 ioc->name, ret);
2706 }
2707 }
2708
2709
2710
2711
2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
2713 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
2714 CAN_SLEEP)) {
2715 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
2716 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
2717 "reset failed to put ioc in ready state!\n",
2718 ioc->name, __func__);
2719 } else
2720 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
2721 "failed!\n", ioc->name, __func__);
2722 }
2723
2724
2725
2726 synchronize_irq(ioc->pcidev->irq);
2727 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2728 ioc->active = 0;
2729
2730
2731 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2732 CHIPREG_READ32(&ioc->chip->IntStatus);
2733
2734 if (ioc->alloc != NULL) {
2735 sz = ioc->alloc_sz;
2736 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
2737 ioc->name, ioc->alloc, ioc->alloc_sz));
2738 pci_free_consistent(ioc->pcidev, sz,
2739 ioc->alloc, ioc->alloc_dma);
2740 ioc->reply_frames = NULL;
2741 ioc->req_frames = NULL;
2742 ioc->alloc = NULL;
2743 ioc->alloc_total -= sz;
2744 }
2745
2746 if (ioc->sense_buf_pool != NULL) {
2747 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
2748 pci_free_consistent(ioc->pcidev, sz,
2749 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
2750 ioc->sense_buf_pool = NULL;
2751 ioc->alloc_total -= sz;
2752 }
2753
2754 if (ioc->events != NULL){
2755 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
2756 kfree(ioc->events);
2757 ioc->events = NULL;
2758 ioc->alloc_total -= sz;
2759 }
2760
2761 mpt_free_fw_memory(ioc);
2762
2763 kfree(ioc->spi_data.nvram);
2764 mpt_inactive_raid_list_free(ioc);
2765 kfree(ioc->raid_data.pIocPg2);
2766 kfree(ioc->raid_data.pIocPg3);
2767 ioc->spi_data.nvram = NULL;
2768 ioc->raid_data.pIocPg3 = NULL;
2769
2770 if (ioc->spi_data.pIocPg4 != NULL) {
2771 sz = ioc->spi_data.IocPg4Sz;
2772 pci_free_consistent(ioc->pcidev, sz,
2773 ioc->spi_data.pIocPg4,
2774 ioc->spi_data.IocPg4_dma);
2775 ioc->spi_data.pIocPg4 = NULL;
2776 ioc->alloc_total -= sz;
2777 }
2778
2779 if (ioc->ReqToChain != NULL) {
2780 kfree(ioc->ReqToChain);
2781 kfree(ioc->RequestNB);
2782 ioc->ReqToChain = NULL;
2783 }
2784
2785 kfree(ioc->ChainToChain);
2786 ioc->ChainToChain = NULL;
2787
2788 if (ioc->HostPageBuffer != NULL) {
2789 if((ret = mpt_host_page_access_control(ioc,
2790 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
2791 printk(MYIOC_s_ERR_FMT
2792 ": %s: host page buffers free failed (%d)!\n",
2793 ioc->name, __func__, ret);
2794 }
2795 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2796 "HostPageBuffer free @ %p, sz=%d bytes\n",
2797 ioc->name, ioc->HostPageBuffer,
2798 ioc->HostPageBuffer_sz));
2799 pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz,
2800 ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
2801 ioc->HostPageBuffer = NULL;
2802 ioc->HostPageBuffer_sz = 0;
2803 ioc->alloc_total -= ioc->HostPageBuffer_sz;
2804 }
2805
2806 pci_set_drvdata(ioc->pcidev, NULL);
2807}
2808
2809
2810
2811
2812
2813
2814
2815
2816static void
2817mpt_adapter_dispose(MPT_ADAPTER *ioc)
2818{
2819 int sz_first, sz_last;
2820
2821 if (ioc == NULL)
2822 return;
2823
2824 sz_first = ioc->alloc_total;
2825
2826 mpt_adapter_disable(ioc);
2827
2828 if (ioc->pci_irq != -1) {
2829 free_irq(ioc->pci_irq, ioc);
2830 if (ioc->msi_enable)
2831 pci_disable_msi(ioc->pcidev);
2832 ioc->pci_irq = -1;
2833 }
2834
2835 if (ioc->memmap != NULL) {
2836 iounmap(ioc->memmap);
2837 ioc->memmap = NULL;
2838 }
2839
2840 pci_disable_device(ioc->pcidev);
2841 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2842
2843
2844 list_del(&ioc->list);
2845
2846 sz_last = ioc->alloc_total;
2847 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
2848 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
2849
2850 if (ioc->alt_ioc)
2851 ioc->alt_ioc->alt_ioc = NULL;
2852
2853 kfree(ioc);
2854}
2855
2856
2857
2858
2859
2860
2861static void
2862MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
2863{
2864 int i = 0;
2865
2866 printk(KERN_INFO "%s: ", ioc->name);
2867 if (ioc->prod_name)
2868 pr_cont("%s: ", ioc->prod_name);
2869 pr_cont("Capabilities={");
2870
2871 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
2872 pr_cont("Initiator");
2873 i++;
2874 }
2875
2876 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2877 pr_cont("%sTarget", i ? "," : "");
2878 i++;
2879 }
2880
2881 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
2882 pr_cont("%sLAN", i ? "," : "");
2883 i++;
2884 }
2885
2886#if 0
2887
2888
2889
2890 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2891 pr_cont("%sLogBusAddr", i ? "," : "");
2892 i++;
2893 }
2894#endif
2895
2896 pr_cont("}\n");
2897}
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914static int
2915MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
2916{
2917 u32 ioc_state;
2918 int statefault = 0;
2919 int cntdn;
2920 int hard_reset_done = 0;
2921 int r;
2922 int ii;
2923 int whoinit;
2924
2925
2926 ioc_state = mpt_GetIocState(ioc, 0);
2927 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
2928
2929
2930
2931
2932
2933 if (ioc_state & MPI_DOORBELL_ACTIVE) {
2934 statefault = 1;
2935 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
2936 ioc->name);
2937 }
2938
2939
2940 if (!statefault &&
2941 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
2942 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2943 "IOC is in READY state\n", ioc->name));
2944 return 0;
2945 }
2946
2947
2948
2949
2950 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
2951 statefault = 2;
2952 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
2953 ioc->name);
2954 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
2955 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
2956 }
2957
2958
2959
2960
2961 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
2962 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
2963 ioc->name));
2964
2965
2966
2967
2968
2969
2970 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
2971 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2972 "whoinit 0x%x statefault %d force %d\n",
2973 ioc->name, whoinit, statefault, force));
2974 if (whoinit == MPI_WHOINIT_PCI_PEER)
2975 return -4;
2976 else {
2977 if ((statefault == 0 ) && (force == 0)) {
2978 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
2979 return 0;
2980 }
2981 statefault = 3;
2982 }
2983 }
2984
2985 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
2986 if (hard_reset_done < 0)
2987 return -1;
2988
2989
2990
2991
2992 ii = 0;
2993 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5;
2994
2995 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
2996 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
2997
2998
2999
3000
3001 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
3002 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
3003 return -2;
3004 }
3005 } else if (ioc_state == MPI_IOC_STATE_RESET) {
3006
3007
3008
3009
3010 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
3011 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
3012 return -3;
3013 }
3014 }
3015
3016 ii++; cntdn--;
3017 if (!cntdn) {
3018 printk(MYIOC_s_ERR_FMT
3019 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
3020 ioc->name, ioc_state, (int)((ii+5)/HZ));
3021 return -ETIME;
3022 }
3023
3024 if (sleepFlag == CAN_SLEEP) {
3025 msleep(1);
3026 } else {
3027 mdelay (1);
3028 }
3029
3030 }
3031
3032 if (statefault < 3) {
3033 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
3034 statefault == 1 ? "stuck handshake" : "IOC FAULT");
3035 }
3036
3037 return hard_reset_done;
3038}
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049u32
3050mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
3051{
3052 u32 s, sc;
3053
3054
3055 s = CHIPREG_READ32(&ioc->chip->Doorbell);
3056 sc = s & MPI_IOC_STATE_MASK;
3057
3058
3059 ioc->last_state = sc;
3060
3061 return cooked ? sc : s;
3062}
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073static int
3074GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
3075{
3076 IOCFacts_t get_facts;
3077 IOCFactsReply_t *facts;
3078 int r;
3079 int req_sz;
3080 int reply_sz;
3081 int sz;
3082 u32 status, vv;
3083 u8 shiftFactor=1;
3084
3085
3086 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3087 printk(KERN_ERR MYNAM
3088 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
3089 ioc->name, ioc->last_state);
3090 return -44;
3091 }
3092
3093 facts = &ioc->facts;
3094
3095
3096 reply_sz = sizeof(*facts);
3097 memset(facts, 0, reply_sz);
3098
3099
3100 req_sz = sizeof(get_facts);
3101 memset(&get_facts, 0, req_sz);
3102
3103 get_facts.Function = MPI_FUNCTION_IOC_FACTS;
3104
3105
3106 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3107 "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
3108 ioc->name, req_sz, reply_sz));
3109
3110
3111
3112
3113 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
3114 reply_sz, (u16*)facts, 5 , sleepFlag);
3115 if (r != 0)
3116 return r;
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
3127 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3128
3129
3130
3131 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
3132 ioc->FirstWhoInit = facts->WhoInit;
3133 }
3134
3135 facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
3136 facts->MsgContext = le32_to_cpu(facts->MsgContext);
3137 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
3138 facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
3139 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
3140 status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
3141
3142
3143 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
3144 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
3145
3146
3147
3148
3149
3150
3151 if (facts->MsgVersion < MPI_VERSION_01_02) {
3152
3153
3154
3155 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
3156 facts->FWVersion.Word =
3157 ((oldv<<12) & 0xFF000000) |
3158 ((oldv<<8) & 0x000FFF00);
3159 } else
3160 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
3161
3162 facts->ProductID = le16_to_cpu(facts->ProductID);
3163
3164 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
3165 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
3166 ioc->ir_firmware = 1;
3167
3168 facts->CurrentHostMfaHighAddr =
3169 le32_to_cpu(facts->CurrentHostMfaHighAddr);
3170 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
3171 facts->CurrentSenseBufferHighAddr =
3172 le32_to_cpu(facts->CurrentSenseBufferHighAddr);
3173 facts->CurReplyFrameSize =
3174 le16_to_cpu(facts->CurReplyFrameSize);
3175 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
3176
3177
3178
3179
3180
3181
3182 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
3183 facts->MsgVersion > MPI_VERSION_01_00) {
3184 facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
3185 }
3186
3187 facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
3188
3189 if (!facts->RequestFrameSize) {
3190
3191 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
3192 ioc->name);
3193 return -55;
3194 }
3195
3196 r = sz = facts->BlockSize;
3197 vv = ((63 / (sz * 4)) + 1) & 0x03;
3198 ioc->NB_for_64_byte_frame = vv;
3199 while ( sz )
3200 {
3201 shiftFactor++;
3202 sz = sz >> 1;
3203 }
3204 ioc->NBShiftFactor = shiftFactor;
3205 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3206 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
3207 ioc->name, vv, shiftFactor, r));
3208
3209 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3210
3211
3212
3213
3214 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
3215 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
3216 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
3217 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
3218
3219 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
3220 ioc->name, ioc->reply_sz, ioc->reply_depth));
3221 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
3222 ioc->name, ioc->req_sz, ioc->req_depth));
3223
3224
3225 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
3226 return r;
3227 }
3228 } else {
3229 printk(MYIOC_s_ERR_FMT
3230 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
3231 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
3232 RequestFrameSize)/sizeof(u32)));
3233 return -66;
3234 }
3235
3236 return 0;
3237}
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248static int
3249GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3250{
3251 PortFacts_t get_pfacts;
3252 PortFactsReply_t *pfacts;
3253 int ii;
3254 int req_sz;
3255 int reply_sz;
3256 int max_id;
3257
3258
3259 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3260 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
3261 ioc->name, ioc->last_state );
3262 return -4;
3263 }
3264
3265 pfacts = &ioc->pfacts[portnum];
3266
3267
3268 reply_sz = sizeof(*pfacts);
3269 memset(pfacts, 0, reply_sz);
3270
3271
3272 req_sz = sizeof(get_pfacts);
3273 memset(&get_pfacts, 0, req_sz);
3274
3275 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
3276 get_pfacts.PortNumber = portnum;
3277
3278
3279 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
3280 ioc->name, portnum));
3281
3282
3283
3284
3285 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
3286 reply_sz, (u16*)pfacts, 5 , sleepFlag);
3287 if (ii != 0)
3288 return ii;
3289
3290
3291
3292
3293 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
3294 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
3295 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
3296 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
3297 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
3298 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
3299 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
3300 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
3301 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
3302
3303 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
3304 pfacts->MaxDevices;
3305 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
3306 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
3307
3308
3309
3310
3311
3312
3313 if (mpt_channel_mapping) {
3314 ioc->devices_per_bus = 1;
3315 ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
3316 }
3317
3318 return 0;
3319}
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331static int
3332SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
3333{
3334 IOCInit_t ioc_init;
3335 MPIDefaultReply_t init_reply;
3336 u32 state;
3337 int r;
3338 int count;
3339 int cntdn;
3340
3341 memset(&ioc_init, 0, sizeof(ioc_init));
3342 memset(&init_reply, 0, sizeof(init_reply));
3343
3344 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
3345 ioc_init.Function = MPI_FUNCTION_IOC_INIT;
3346
3347
3348
3349
3350
3351 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
3352 ioc->upload_fw = 1;
3353 else
3354 ioc->upload_fw = 0;
3355 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
3356 ioc->name, ioc->upload_fw, ioc->facts.Flags));
3357
3358 ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
3359 ioc_init.MaxBuses = (U8)ioc->number_of_buses;
3360
3361 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
3362 ioc->name, ioc->facts.MsgVersion));
3363 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
3364
3365 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
3366 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
3367
3368 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
3369 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
3370 } else if(mpt_host_page_alloc(ioc, &ioc_init))
3371 return -99;
3372 }
3373 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz);
3374
3375 if (ioc->sg_addr_size == sizeof(u64)) {
3376
3377
3378
3379 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
3380 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
3381 } else {
3382
3383 ioc_init.HostMfaHighAddr = cpu_to_le32(0);
3384 ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
3385 }
3386
3387 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
3388 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
3389 ioc->facts.MaxDevices = ioc_init.MaxDevices;
3390 ioc->facts.MaxBuses = ioc_init.MaxBuses;
3391
3392 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
3393 ioc->name, &ioc_init));
3394
3395 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
3396 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 , sleepFlag);
3397 if (r != 0) {
3398 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
3399 return r;
3400 }
3401
3402
3403
3404
3405
3406 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
3407 ioc->name, &ioc_init));
3408
3409 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
3410 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
3411 return r;
3412 }
3413
3414
3415
3416
3417
3418 count = 0;
3419 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60;
3420 state = mpt_GetIocState(ioc, 1);
3421 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
3422 if (sleepFlag == CAN_SLEEP) {
3423 msleep(1);
3424 } else {
3425 mdelay(1);
3426 }
3427
3428 if (!cntdn) {
3429 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
3430 ioc->name, (int)((count+5)/HZ));
3431 return -9;
3432 }
3433
3434 state = mpt_GetIocState(ioc, 1);
3435 count++;
3436 }
3437 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
3438 ioc->name, count));
3439
3440 ioc->aen_event_read_flag=0;
3441 return r;
3442}
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455static int
3456SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3457{
3458 PortEnable_t port_enable;
3459 MPIDefaultReply_t reply_buf;
3460 int rc;
3461 int req_sz;
3462 int reply_sz;
3463
3464
3465 reply_sz = sizeof(MPIDefaultReply_t);
3466 memset(&reply_buf, 0, reply_sz);
3467
3468 req_sz = sizeof(PortEnable_t);
3469 memset(&port_enable, 0, req_sz);
3470
3471 port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
3472 port_enable.PortNumber = portnum;
3473
3474
3475
3476
3477 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
3478 ioc->name, portnum, &port_enable));
3479
3480
3481
3482 if (ioc->ir_firmware || ioc->bus_type == SAS) {
3483 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3484 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3485 300 , sleepFlag);
3486 } else {
3487 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3488 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3489 30 , sleepFlag);
3490 }
3491 return rc;
3492}
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504int
3505mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
3506{
3507 int rc;
3508
3509 if (ioc->cached_fw) {
3510 rc = 0;
3511 goto out;
3512 }
3513 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
3514 ioc->cached_fw = ioc->alt_ioc->cached_fw;
3515 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
3516 rc = 0;
3517 goto out;
3518 }
3519 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
3520 if (!ioc->cached_fw) {
3521 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
3522 ioc->name);
3523 rc = -1;
3524 } else {
3525 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
3526 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
3527 ioc->alloc_total += size;
3528 rc = 0;
3529 }
3530 out:
3531 return rc;
3532}
3533
3534
3535
3536
3537
3538
3539
3540
3541void
3542mpt_free_fw_memory(MPT_ADAPTER *ioc)
3543{
3544 int sz;
3545
3546 if (!ioc->cached_fw)
3547 return;
3548
3549 sz = ioc->facts.FWImageSize;
3550 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
3551 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3552 pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
3553 ioc->alloc_total -= sz;
3554 ioc->cached_fw = NULL;
3555}
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571static int
3572mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
3573{
3574 u8 reply[sizeof(FWUploadReply_t)];
3575 FWUpload_t *prequest;
3576 FWUploadReply_t *preply;
3577 FWUploadTCSGE_t *ptcsge;
3578 u32 flagsLength;
3579 int ii, sz, reply_sz;
3580 int cmdStatus;
3581 int request_size;
3582
3583
3584 if ((sz = ioc->facts.FWImageSize) == 0)
3585 return 0;
3586
3587 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
3588 return -ENOMEM;
3589
3590 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
3591 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3592
3593 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
3594 kzalloc(ioc->req_sz, GFP_KERNEL);
3595 if (!prequest) {
3596 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
3597 "while allocating memory \n", ioc->name));
3598 mpt_free_fw_memory(ioc);
3599 return -ENOMEM;
3600 }
3601
3602 preply = (FWUploadReply_t *)&reply;
3603
3604 reply_sz = sizeof(reply);
3605 memset(preply, 0, reply_sz);
3606
3607 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
3608 prequest->Function = MPI_FUNCTION_FW_UPLOAD;
3609
3610 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
3611 ptcsge->DetailsLength = 12;
3612 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
3613 ptcsge->ImageSize = cpu_to_le32(sz);
3614 ptcsge++;
3615
3616 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
3617 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
3618 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
3619 ioc->SGE_size;
3620 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
3621 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
3622 ioc->facts.FWImageSize, request_size));
3623 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
3624
3625 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
3626 reply_sz, (u16 *)preply, 65 , sleepFlag);
3627
3628 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
3629 "rc=%x \n", ioc->name, ii));
3630
3631 cmdStatus = -EFAULT;
3632 if (ii == 0) {
3633
3634
3635
3636 int status;
3637 status = le16_to_cpu(preply->IOCStatus) &
3638 MPI_IOCSTATUS_MASK;
3639 if (status == MPI_IOCSTATUS_SUCCESS &&
3640 ioc->facts.FWImageSize ==
3641 le32_to_cpu(preply->ActualImageSize))
3642 cmdStatus = 0;
3643 }
3644 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
3645 ioc->name, cmdStatus));
3646
3647
3648 if (cmdStatus) {
3649 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
3650 "freeing image \n", ioc->name));
3651 mpt_free_fw_memory(ioc);
3652 }
3653 kfree(prequest);
3654
3655 return cmdStatus;
3656}
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672static int
3673mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
3674{
3675 MpiExtImageHeader_t *pExtImage;
3676 u32 fwSize;
3677 u32 diag0val;
3678 int count;
3679 u32 *ptrFw;
3680 u32 diagRwData;
3681 u32 nextImage;
3682 u32 load_addr;
3683 u32 ioc_state=0;
3684
3685 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
3686 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
3687
3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3691 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3692 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3693 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3694
3695 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
3696
3697
3698 if (sleepFlag == CAN_SLEEP) {
3699 msleep(1);
3700 } else {
3701 mdelay (1);
3702 }
3703
3704 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3705 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
3706
3707 for (count = 0; count < 30; count ++) {
3708 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3709 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
3710 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
3711 ioc->name, count));
3712 break;
3713 }
3714
3715 if (sleepFlag == CAN_SLEEP) {
3716 msleep (100);
3717 } else {
3718 mdelay (100);
3719 }
3720 }
3721
3722 if ( count == 30 ) {
3723 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
3724 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
3725 ioc->name, diag0val));
3726 return -3;
3727 }
3728
3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3732 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3733 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3734 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3735
3736
3737 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
3738
3739 fwSize = (pFwHeader->ImageSize + 3)/4;
3740 ptrFw = (u32 *) pFwHeader;
3741
3742
3743
3744
3745 if (ioc->errata_flag_1064)
3746 pci_enable_io_access(ioc->pcidev);
3747
3748 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
3749 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
3750 ioc->name, pFwHeader->LoadStartAddress));
3751
3752 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
3753 ioc->name, fwSize*4, ptrFw));
3754 while (fwSize--) {
3755 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3756 }
3757
3758 nextImage = pFwHeader->NextImageHeaderOffset;
3759 while (nextImage) {
3760 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
3761
3762 load_addr = pExtImage->LoadStartAddress;
3763
3764 fwSize = (pExtImage->ImageSize + 3) >> 2;
3765 ptrFw = (u32 *)pExtImage;
3766
3767 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
3768 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
3769 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
3770
3771 while (fwSize--) {
3772 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3773 }
3774 nextImage = pExtImage->NextImageHeaderOffset;
3775 }
3776
3777
3778 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
3779 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
3780
3781
3782 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
3783 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
3784
3785
3786
3787
3788 if (ioc->bus_type == SPI) {
3789
3790
3791
3792
3793 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3794 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
3795 diagRwData |= 0x40000000;
3796 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3797 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
3798
3799 } else {
3800 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3801 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
3802 MPI_DIAG_CLEAR_FLASH_BAD_SIG);
3803
3804
3805 if (sleepFlag == CAN_SLEEP) {
3806 msleep (1);
3807 } else {
3808 mdelay (1);
3809 }
3810 }
3811
3812 if (ioc->errata_flag_1064)
3813 pci_disable_io_access(ioc->pcidev);
3814
3815 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3816 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
3817 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
3818 ioc->name, diag0val));
3819 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
3820 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
3821 ioc->name, diag0val));
3822 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
3823
3824
3825 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3826
3827 if (ioc->bus_type == SAS) {
3828 ioc_state = mpt_GetIocState(ioc, 0);
3829 if ( (GetIocFacts(ioc, sleepFlag,
3830 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
3831 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
3832 ioc->name, ioc_state));
3833 return -EFAULT;
3834 }
3835 }
3836
3837 for (count=0; count<HZ*20; count++) {
3838 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
3839 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3840 "downloadboot successful! (count=%d) IocState=%x\n",
3841 ioc->name, count, ioc_state));
3842 if (ioc->bus_type == SAS) {
3843 return 0;
3844 }
3845 if ((SendIocInit(ioc, sleepFlag)) != 0) {
3846 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3847 "downloadboot: SendIocInit failed\n",
3848 ioc->name));
3849 return -EFAULT;
3850 }
3851 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3852 "downloadboot: SendIocInit successful\n",
3853 ioc->name));
3854 return 0;
3855 }
3856 if (sleepFlag == CAN_SLEEP) {
3857 msleep (10);
3858 } else {
3859 mdelay (10);
3860 }
3861 }
3862 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3863 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
3864 return -EFAULT;
3865}
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893static int
3894KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
3895{
3896 int hard_reset_done = 0;
3897 u32 ioc_state=0;
3898 int cnt,cntdn;
3899
3900 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
3901 if (ioc->bus_type == SPI) {
3902
3903
3904
3905 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
3906
3907 if (sleepFlag == CAN_SLEEP) {
3908 msleep (1000);
3909 } else {
3910 mdelay (1000);
3911 }
3912 }
3913
3914 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
3915 if (hard_reset_done < 0)
3916 return hard_reset_done;
3917
3918 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
3919 ioc->name));
3920
3921 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2;
3922 for (cnt=0; cnt<cntdn; cnt++) {
3923 ioc_state = mpt_GetIocState(ioc, 1);
3924 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
3925 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
3926 ioc->name, cnt));
3927 return hard_reset_done;
3928 }
3929 if (sleepFlag == CAN_SLEEP) {
3930 msleep (10);
3931 } else {
3932 mdelay (10);
3933 }
3934 }
3935
3936 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
3937 ioc->name, mpt_GetIocState(ioc, 0)));
3938 return -1;
3939}
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960static int
3961mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
3962{
3963 u32 diag0val;
3964 u32 doorbell;
3965 int hard_reset_done = 0;
3966 int count = 0;
3967 u32 diag1val = 0;
3968 MpiFwHeader_t *cached_fw;
3969 u8 cb_idx;
3970
3971
3972 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
3973
3974 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
3975
3976 if (!ignore)
3977 return 0;
3978
3979 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
3980 "address=%p\n", ioc->name, __func__,
3981 &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
3982 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
3983 if (sleepFlag == CAN_SLEEP)
3984 msleep(1);
3985 else
3986 mdelay(1);
3987
3988
3989
3990
3991
3992
3993
3994 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
3995 if (MptResetHandlers[cb_idx])
3996 (*(MptResetHandlers[cb_idx]))(ioc,
3997 MPT_IOC_PRE_RESET);
3998 }
3999
4000 for (count = 0; count < 60; count ++) {
4001 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4002 doorbell &= MPI_IOC_STATE_MASK;
4003
4004 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4005 "looking for READY STATE: doorbell=%x"
4006 " count=%d\n",
4007 ioc->name, doorbell, count));
4008
4009 if (doorbell == MPI_IOC_STATE_READY) {
4010 return 1;
4011 }
4012
4013
4014 if (sleepFlag == CAN_SLEEP)
4015 msleep(1000);
4016 else
4017 mdelay(1000);
4018 }
4019 return -1;
4020 }
4021
4022
4023 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4024
4025 if (ioc->debug_level & MPT_DEBUG) {
4026 if (ioc->alt_ioc)
4027 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4028 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
4029 ioc->name, diag0val, diag1val));
4030 }
4031
4032
4033
4034
4035 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
4036 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4037
4038
4039
4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4043 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4044 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4045 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4046
4047
4048 if (sleepFlag == CAN_SLEEP) {
4049 msleep (100);
4050 } else {
4051 mdelay (100);
4052 }
4053
4054 count++;
4055 if (count > 20) {
4056 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4057 ioc->name, diag0val);
4058 return -2;
4059
4060 }
4061
4062 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4063
4064 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
4065 ioc->name, diag0val));
4066 }
4067
4068 if (ioc->debug_level & MPT_DEBUG) {
4069 if (ioc->alt_ioc)
4070 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4071 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
4072 ioc->name, diag0val, diag1val));
4073 }
4074
4075
4076
4077
4078 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
4079 mdelay(1);
4080
4081
4082
4083
4084
4085 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
4086 hard_reset_done = 1;
4087 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
4088 ioc->name));
4089
4090
4091
4092
4093
4094
4095
4096 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
4097 if (MptResetHandlers[cb_idx]) {
4098 mpt_signal_reset(cb_idx,
4099 ioc, MPT_IOC_PRE_RESET);
4100 if (ioc->alt_ioc) {
4101 mpt_signal_reset(cb_idx,
4102 ioc->alt_ioc, MPT_IOC_PRE_RESET);
4103 }
4104 }
4105 }
4106
4107 if (ioc->cached_fw)
4108 cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
4109 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
4110 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
4111 else
4112 cached_fw = NULL;
4113 if (cached_fw) {
4114
4115
4116
4117
4118 for (count = 0; count < 30; count ++) {
4119 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4120 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
4121 break;
4122 }
4123
4124 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
4125 ioc->name, diag0val, count));
4126
4127 if (sleepFlag == CAN_SLEEP) {
4128 msleep (1000);
4129 } else {
4130 mdelay (1000);
4131 }
4132 }
4133 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
4134 printk(MYIOC_s_WARN_FMT
4135 "firmware downloadboot failure (%d)!\n", ioc->name, count);
4136 }
4137
4138 } else {
4139
4140
4141
4142
4143
4144
4145 for (count = 0; count < 60; count ++) {
4146 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4147 doorbell &= MPI_IOC_STATE_MASK;
4148
4149 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4150 "looking for READY STATE: doorbell=%x"
4151 " count=%d\n", ioc->name, doorbell, count));
4152
4153 if (doorbell == MPI_IOC_STATE_READY) {
4154 break;
4155 }
4156
4157
4158 if (sleepFlag == CAN_SLEEP) {
4159 msleep (1000);
4160 } else {
4161 mdelay (1000);
4162 }
4163 }
4164
4165 if (doorbell != MPI_IOC_STATE_READY)
4166 printk(MYIOC_s_ERR_FMT "Failed to come READY "
4167 "after reset! IocState=%x", ioc->name,
4168 doorbell);
4169 }
4170 }
4171
4172 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4173 if (ioc->debug_level & MPT_DEBUG) {
4174 if (ioc->alt_ioc)
4175 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4176 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
4177 ioc->name, diag0val, diag1val));
4178 }
4179
4180
4181
4182
4183 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4184 count = 0;
4185 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4186
4187
4188
4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4192 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4193 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4194 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4195
4196
4197 if (sleepFlag == CAN_SLEEP) {
4198 msleep (100);
4199 } else {
4200 mdelay (100);
4201 }
4202
4203 count++;
4204 if (count > 20) {
4205 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4206 ioc->name, diag0val);
4207 break;
4208 }
4209 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4210 }
4211 diag0val &= ~MPI_DIAG_RESET_HISTORY;
4212 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
4213 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4214 if (diag0val & MPI_DIAG_RESET_HISTORY) {
4215 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
4216 ioc->name);
4217 }
4218
4219
4220
4221 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
4222
4223
4224
4225 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4226 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
4227 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
4228 ioc->name, diag0val);
4229 return -3;
4230 }
4231
4232 if (ioc->debug_level & MPT_DEBUG) {
4233 if (ioc->alt_ioc)
4234 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4235 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
4236 ioc->name, diag0val, diag1val));
4237 }
4238
4239
4240
4241
4242 ioc->facts.EventState = 0;
4243
4244 if (ioc->alt_ioc)
4245 ioc->alt_ioc->facts.EventState = 0;
4246
4247 return hard_reset_done;
4248}
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262static int
4263SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
4264{
4265 int r;
4266 u32 state;
4267 int cntdn, count;
4268
4269 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
4270 ioc->name, reset_type));
4271 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
4272 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4273 return r;
4274
4275
4276
4277 count = 0;
4278 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15;
4279
4280 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
4281 cntdn--;
4282 count++;
4283 if (!cntdn) {
4284 if (sleepFlag != CAN_SLEEP)
4285 count *= 10;
4286
4287 printk(MYIOC_s_ERR_FMT
4288 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
4289 ioc->name, state, (int)((count+5)/HZ));
4290 return -ETIME;
4291 }
4292
4293 if (sleepFlag == CAN_SLEEP) {
4294 msleep(1);
4295 } else {
4296 mdelay (1);
4297 }
4298 }
4299
4300
4301
4302
4303
4304 if (ioc->facts.Function)
4305 ioc->facts.EventState = 0;
4306
4307 return 0;
4308}
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318static int
4319initChainBuffers(MPT_ADAPTER *ioc)
4320{
4321 u8 *mem;
4322 int sz, ii, num_chain;
4323 int scale, num_sge, numSGE;
4324
4325
4326
4327
4328 if (ioc->ReqToChain == NULL) {
4329 sz = ioc->req_depth * sizeof(int);
4330 mem = kmalloc(sz, GFP_ATOMIC);
4331 if (mem == NULL)
4332 return -1;
4333
4334 ioc->ReqToChain = (int *) mem;
4335 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
4336 ioc->name, mem, sz));
4337 mem = kmalloc(sz, GFP_ATOMIC);
4338 if (mem == NULL)
4339 return -1;
4340
4341 ioc->RequestNB = (int *) mem;
4342 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
4343 ioc->name, mem, sz));
4344 }
4345 for (ii = 0; ii < ioc->req_depth; ii++) {
4346 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
4347 }
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359 scale = ioc->req_sz / ioc->SGE_size;
4360 if (ioc->sg_addr_size == sizeof(u64))
4361 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
4362 else
4363 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
4364
4365 if (ioc->sg_addr_size == sizeof(u64)) {
4366 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
4367 (ioc->req_sz - 60) / ioc->SGE_size;
4368 } else {
4369 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
4370 scale + (ioc->req_sz - 64) / ioc->SGE_size;
4371 }
4372 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
4373 ioc->name, num_sge, numSGE));
4374
4375 if (ioc->bus_type == FC) {
4376 if (numSGE > MPT_SCSI_FC_SG_DEPTH)
4377 numSGE = MPT_SCSI_FC_SG_DEPTH;
4378 } else {
4379 if (numSGE > MPT_SCSI_SG_DEPTH)
4380 numSGE = MPT_SCSI_SG_DEPTH;
4381 }
4382
4383 num_chain = 1;
4384 while (numSGE - num_sge > 0) {
4385 num_chain++;
4386 num_sge += (scale - 1);
4387 }
4388 num_chain++;
4389
4390 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
4391 ioc->name, numSGE, num_sge, num_chain));
4392
4393 if (ioc->bus_type == SPI)
4394 num_chain *= MPT_SCSI_CAN_QUEUE;
4395 else if (ioc->bus_type == SAS)
4396 num_chain *= MPT_SAS_CAN_QUEUE;
4397 else
4398 num_chain *= MPT_FC_CAN_QUEUE;
4399
4400 ioc->num_chain = num_chain;
4401
4402 sz = num_chain * sizeof(int);
4403 if (ioc->ChainToChain == NULL) {
4404 mem = kmalloc(sz, GFP_ATOMIC);
4405 if (mem == NULL)
4406 return -1;
4407
4408 ioc->ChainToChain = (int *) mem;
4409 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
4410 ioc->name, mem, sz));
4411 } else {
4412 mem = (u8 *) ioc->ChainToChain;
4413 }
4414 memset(mem, 0xFF, sz);
4415 return num_chain;
4416}
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429static int
4430PrimeIocFifos(MPT_ADAPTER *ioc)
4431{
4432 MPT_FRAME_HDR *mf;
4433 unsigned long flags;
4434 dma_addr_t alloc_dma;
4435 u8 *mem;
4436 int i, reply_sz, sz, total_size, num_chain;
4437 u64 dma_mask;
4438
4439 dma_mask = 0;
4440
4441
4442
4443 if (ioc->reply_frames == NULL) {
4444 if ( (num_chain = initChainBuffers(ioc)) < 0)
4445 return -1;
4446
4447
4448
4449 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
4450 ioc->dma_mask > DMA_BIT_MASK(35)) {
4451 if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
4452 && !pci_set_consistent_dma_mask(ioc->pcidev,
4453 DMA_BIT_MASK(32))) {
4454 dma_mask = DMA_BIT_MASK(35);
4455 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4456 "setting 35 bit addressing for "
4457 "Request/Reply/Chain and Sense Buffers\n",
4458 ioc->name));
4459 } else {
4460
4461 pci_set_dma_mask(ioc->pcidev,
4462 DMA_BIT_MASK(64));
4463 pci_set_consistent_dma_mask(ioc->pcidev,
4464 DMA_BIT_MASK(64));
4465
4466 printk(MYIOC_s_ERR_FMT
4467 "failed setting 35 bit addressing for "
4468 "Request/Reply/Chain and Sense Buffers\n",
4469 ioc->name);
4470 return -1;
4471 }
4472 }
4473
4474 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
4475 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
4476 ioc->name, ioc->reply_sz, ioc->reply_depth));
4477 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
4478 ioc->name, reply_sz, reply_sz));
4479
4480 sz = (ioc->req_sz * ioc->req_depth);
4481 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
4482 ioc->name, ioc->req_sz, ioc->req_depth));
4483 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
4484 ioc->name, sz, sz));
4485 total_size += sz;
4486
4487 sz = num_chain * ioc->req_sz;
4488 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
4489 ioc->name, ioc->req_sz, num_chain));
4490 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
4491 ioc->name, sz, sz, num_chain));
4492
4493 total_size += sz;
4494 mem = pci_alloc_consistent(ioc->pcidev, total_size, &alloc_dma);
4495 if (mem == NULL) {
4496 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
4497 ioc->name);
4498 goto out_fail;
4499 }
4500
4501 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
4502 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
4503
4504 memset(mem, 0, total_size);
4505 ioc->alloc_total += total_size;
4506 ioc->alloc = mem;
4507 ioc->alloc_dma = alloc_dma;
4508 ioc->alloc_sz = total_size;
4509 ioc->reply_frames = (MPT_FRAME_HDR *) mem;
4510 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4511
4512 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4513 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4514
4515 alloc_dma += reply_sz;
4516 mem += reply_sz;
4517
4518
4519
4520 ioc->req_frames = (MPT_FRAME_HDR *) mem;
4521 ioc->req_frames_dma = alloc_dma;
4522
4523 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
4524 ioc->name, mem, (void *)(ulong)alloc_dma));
4525
4526 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4527
4528 for (i = 0; i < ioc->req_depth; i++) {
4529 alloc_dma += ioc->req_sz;
4530 mem += ioc->req_sz;
4531 }
4532
4533 ioc->ChainBuffer = mem;
4534 ioc->ChainBufferDMA = alloc_dma;
4535
4536 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
4537 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
4538
4539
4540
4541
4542 INIT_LIST_HEAD(&ioc->FreeChainQ);
4543
4544
4545
4546 mem = (u8 *)ioc->ChainBuffer;
4547 for (i=0; i < num_chain; i++) {
4548 mf = (MPT_FRAME_HDR *) mem;
4549 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
4550 mem += ioc->req_sz;
4551 }
4552
4553
4554
4555 alloc_dma = ioc->req_frames_dma;
4556 mem = (u8 *) ioc->req_frames;
4557
4558 spin_lock_irqsave(&ioc->FreeQlock, flags);
4559 INIT_LIST_HEAD(&ioc->FreeQ);
4560 for (i = 0; i < ioc->req_depth; i++) {
4561 mf = (MPT_FRAME_HDR *) mem;
4562
4563
4564 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
4565
4566 mem += ioc->req_sz;
4567 }
4568 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
4569
4570 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4571 ioc->sense_buf_pool =
4572 pci_alloc_consistent(ioc->pcidev, sz, &ioc->sense_buf_pool_dma);
4573 if (ioc->sense_buf_pool == NULL) {
4574 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
4575 ioc->name);
4576 goto out_fail;
4577 }
4578
4579 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
4580 ioc->alloc_total += sz;
4581 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
4582 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
4583
4584 }
4585
4586
4587
4588 alloc_dma = ioc->alloc_dma;
4589 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4590 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4591
4592 for (i = 0; i < ioc->reply_depth; i++) {
4593
4594 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
4595 alloc_dma += ioc->reply_sz;
4596 }
4597
4598 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4599 ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
4600 ioc->dma_mask))
4601 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4602 "restoring 64 bit addressing\n", ioc->name));
4603
4604 return 0;
4605
4606out_fail:
4607
4608 if (ioc->alloc != NULL) {
4609 sz = ioc->alloc_sz;
4610 pci_free_consistent(ioc->pcidev,
4611 sz,
4612 ioc->alloc, ioc->alloc_dma);
4613 ioc->reply_frames = NULL;
4614 ioc->req_frames = NULL;
4615 ioc->alloc_total -= sz;
4616 }
4617 if (ioc->sense_buf_pool != NULL) {
4618 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4619 pci_free_consistent(ioc->pcidev,
4620 sz,
4621 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
4622 ioc->sense_buf_pool = NULL;
4623 }
4624
4625 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4626 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
4627 DMA_BIT_MASK(64)))
4628 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4629 "restoring 64 bit addressing\n", ioc->name));
4630
4631 return -1;
4632}
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653static int
4654mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
4655 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
4656{
4657 MPIDefaultReply_t *mptReply;
4658 int failcnt = 0;
4659 int t;
4660
4661
4662
4663
4664 ioc->hs_reply_idx = 0;
4665 mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4666 mptReply->MsgLength = 0;
4667
4668
4669
4670
4671
4672
4673 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4674 CHIPREG_WRITE32(&ioc->chip->Doorbell,
4675 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
4676 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
4677
4678
4679
4680
4681 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4682 failcnt++;
4683
4684 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
4685 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4686
4687
4688 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
4689 return -1;
4690
4691
4692
4693
4694
4695
4696 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4697 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4698 failcnt++;
4699
4700 if (!failcnt) {
4701 int ii;
4702 u8 *req_as_bytes = (u8 *) req;
4703
4704
4705
4706
4707
4708 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
4709 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
4710 (req_as_bytes[(ii*4) + 1] << 8) |
4711 (req_as_bytes[(ii*4) + 2] << 16) |
4712 (req_as_bytes[(ii*4) + 3] << 24));
4713
4714 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
4715 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4716 failcnt++;
4717 }
4718
4719 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
4720 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
4721
4722 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
4723 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
4724
4725
4726
4727
4728 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
4729 failcnt++;
4730
4731 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
4732 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
4733
4734
4735
4736
4737 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
4738 u16reply[ii] = ioc->hs_reply[ii];
4739 } else {
4740 return -99;
4741 }
4742
4743 return -failcnt;
4744}
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759static int
4760WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4761{
4762 int cntdn;
4763 int count = 0;
4764 u32 intstat=0;
4765
4766 cntdn = 1000 * howlong;
4767
4768 if (sleepFlag == CAN_SLEEP) {
4769 while (--cntdn) {
4770 msleep (1);
4771 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4772 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4773 break;
4774 count++;
4775 }
4776 } else {
4777 while (--cntdn) {
4778 udelay (1000);
4779 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4780 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4781 break;
4782 count++;
4783 }
4784 }
4785
4786 if (cntdn) {
4787 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
4788 ioc->name, count));
4789 return count;
4790 }
4791
4792 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
4793 ioc->name, count, intstat);
4794 return -1;
4795}
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809static int
4810WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4811{
4812 int cntdn;
4813 int count = 0;
4814 u32 intstat=0;
4815
4816 cntdn = 1000 * howlong;
4817 if (sleepFlag == CAN_SLEEP) {
4818 while (--cntdn) {
4819 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4820 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4821 break;
4822 msleep(1);
4823 count++;
4824 }
4825 } else {
4826 while (--cntdn) {
4827 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4828 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4829 break;
4830 udelay (1000);
4831 count++;
4832 }
4833 }
4834
4835 if (cntdn) {
4836 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
4837 ioc->name, count, howlong));
4838 return count;
4839 }
4840
4841 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
4842 ioc->name, count, intstat);
4843 return -1;
4844}
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859static int
4860WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4861{
4862 int u16cnt = 0;
4863 int failcnt = 0;
4864 int t;
4865 u16 *hs_reply = ioc->hs_reply;
4866 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4867 u16 hword;
4868
4869 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
4870
4871
4872
4873
4874 u16cnt=0;
4875 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
4876 failcnt++;
4877 } else {
4878 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4879 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4880 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4881 failcnt++;
4882 else {
4883 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4884 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4885 }
4886 }
4887
4888 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
4889 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
4890 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4891
4892
4893
4894
4895
4896 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
4897 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4898 failcnt++;
4899 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4900
4901 if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
4902 hs_reply[u16cnt] = hword;
4903 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4904 }
4905
4906 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4907 failcnt++;
4908 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4909
4910 if (failcnt) {
4911 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
4912 ioc->name);
4913 return -failcnt;
4914 }
4915#if 0
4916 else if (u16cnt != (2 * mptReply->MsgLength)) {
4917 return -101;
4918 }
4919 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
4920 return -102;
4921 }
4922#endif
4923
4924 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
4925 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
4926
4927 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
4928 ioc->name, t, u16cnt/2));
4929 return u16cnt/2;
4930}
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943static int
4944GetLanConfigPages(MPT_ADAPTER *ioc)
4945{
4946 ConfigPageHeader_t hdr;
4947 CONFIGPARMS cfg;
4948 LANPage0_t *ppage0_alloc;
4949 dma_addr_t page0_dma;
4950 LANPage1_t *ppage1_alloc;
4951 dma_addr_t page1_dma;
4952 int rc = 0;
4953 int data_sz;
4954 int copy_sz;
4955
4956
4957 hdr.PageVersion = 0;
4958 hdr.PageLength = 0;
4959 hdr.PageNumber = 0;
4960 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4961 cfg.cfghdr.hdr = &hdr;
4962 cfg.physAddr = -1;
4963 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4964 cfg.dir = 0;
4965 cfg.pageAddr = 0;
4966 cfg.timeout = 0;
4967
4968 if ((rc = mpt_config(ioc, &cfg)) != 0)
4969 return rc;
4970
4971 if (hdr.PageLength > 0) {
4972 data_sz = hdr.PageLength * 4;
4973 ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
4974 rc = -ENOMEM;
4975 if (ppage0_alloc) {
4976 memset((u8 *)ppage0_alloc, 0, data_sz);
4977 cfg.physAddr = page0_dma;
4978 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4979
4980 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4981
4982 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
4983 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
4984
4985 }
4986
4987 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
4988
4989
4990
4991
4992
4993
4994 }
4995
4996 if (rc)
4997 return rc;
4998 }
4999
5000
5001 hdr.PageVersion = 0;
5002 hdr.PageLength = 0;
5003 hdr.PageNumber = 1;
5004 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
5005 cfg.cfghdr.hdr = &hdr;
5006 cfg.physAddr = -1;
5007 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5008 cfg.dir = 0;
5009 cfg.pageAddr = 0;
5010
5011 if ((rc = mpt_config(ioc, &cfg)) != 0)
5012 return rc;
5013
5014 if (hdr.PageLength == 0)
5015 return 0;
5016
5017 data_sz = hdr.PageLength * 4;
5018 rc = -ENOMEM;
5019 ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
5020 if (ppage1_alloc) {
5021 memset((u8 *)ppage1_alloc, 0, data_sz);
5022 cfg.physAddr = page1_dma;
5023 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5024
5025 if ((rc = mpt_config(ioc, &cfg)) == 0) {
5026
5027 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
5028 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
5029 }
5030
5031 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
5032
5033
5034
5035
5036
5037
5038 }
5039
5040 return rc;
5041}
5042
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059int
5060mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
5061{
5062 SasIoUnitControlRequest_t *sasIoUnitCntrReq;
5063 SasIoUnitControlReply_t *sasIoUnitCntrReply;
5064 MPT_FRAME_HDR *mf = NULL;
5065 MPIHeader_t *mpi_hdr;
5066 int ret = 0;
5067 unsigned long timeleft;
5068
5069 mutex_lock(&ioc->mptbase_cmds.mutex);
5070
5071
5072 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
5073 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
5074
5075
5076 switch(persist_opcode) {
5077
5078 case MPI_SAS_OP_CLEAR_NOT_PRESENT:
5079 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
5080 break;
5081
5082 default:
5083 ret = -1;
5084 goto out;
5085 }
5086
5087 printk(KERN_DEBUG "%s: persist_opcode=%x\n",
5088 __func__, persist_opcode);
5089
5090
5091
5092 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
5093 printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
5094 ret = -1;
5095 goto out;
5096 }
5097
5098 mpi_hdr = (MPIHeader_t *) mf;
5099 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
5100 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
5101 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
5102 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
5103 sasIoUnitCntrReq->Operation = persist_opcode;
5104
5105 mpt_put_msg_frame(mpt_base_index, ioc, mf);
5106 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
5107 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
5108 ret = -ETIME;
5109 printk(KERN_DEBUG "%s: failed\n", __func__);
5110 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
5111 goto out;
5112 if (!timeleft) {
5113 printk(MYIOC_s_WARN_FMT
5114 "Issuing Reset from %s!!, doorbell=0x%08x\n",
5115 ioc->name, __func__, mpt_GetIocState(ioc, 0));
5116 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
5117 mpt_free_msg_frame(ioc, mf);
5118 }
5119 goto out;
5120 }
5121
5122 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
5123 ret = -1;
5124 goto out;
5125 }
5126
5127 sasIoUnitCntrReply =
5128 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
5129 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
5130 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
5131 __func__, sasIoUnitCntrReply->IOCStatus,
5132 sasIoUnitCntrReply->IOCLogInfo);
5133 printk(KERN_DEBUG "%s: failed\n", __func__);
5134 ret = -1;
5135 } else
5136 printk(KERN_DEBUG "%s: success\n", __func__);
5137 out:
5138
5139 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
5140 mutex_unlock(&ioc->mptbase_cmds.mutex);
5141 return ret;
5142}
5143
5144
5145
5146static void
5147mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
5148 MpiEventDataRaid_t * pRaidEventData)
5149{
5150 int volume;
5151 int reason;
5152 int disk;
5153 int status;
5154 int flags;
5155 int state;
5156
5157 volume = pRaidEventData->VolumeID;
5158 reason = pRaidEventData->ReasonCode;
5159 disk = pRaidEventData->PhysDiskNum;
5160 status = le32_to_cpu(pRaidEventData->SettingsStatus);
5161 flags = (status >> 0) & 0xff;
5162 state = (status >> 8) & 0xff;
5163
5164 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
5165 return;
5166 }
5167
5168 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
5169 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
5170 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
5171 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
5172 ioc->name, disk, volume);
5173 } else {
5174 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
5175 ioc->name, volume);
5176 }
5177
5178 switch(reason) {
5179 case MPI_EVENT_RAID_RC_VOLUME_CREATED:
5180 printk(MYIOC_s_INFO_FMT " volume has been created\n",
5181 ioc->name);
5182 break;
5183
5184 case MPI_EVENT_RAID_RC_VOLUME_DELETED:
5185
5186 printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
5187 ioc->name);
5188 break;
5189
5190 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
5191 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
5192 ioc->name);
5193 break;
5194
5195 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
5196 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
5197 ioc->name,
5198 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
5199 ? "optimal"
5200 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
5201 ? "degraded"
5202 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
5203 ? "failed"
5204 : "state unknown",
5205 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
5206 ? ", enabled" : "",
5207 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
5208 ? ", quiesced" : "",
5209 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
5210 ? ", resync in progress" : "" );
5211 break;
5212
5213 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
5214 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
5215 ioc->name, disk);
5216 break;
5217
5218 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
5219 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
5220 ioc->name);
5221 break;
5222
5223 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
5224 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
5225 ioc->name);
5226 break;
5227
5228 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
5229 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
5230 ioc->name);
5231 break;
5232
5233 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
5234 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
5235 ioc->name,
5236 state == MPI_PHYSDISK0_STATUS_ONLINE
5237 ? "online"
5238 : state == MPI_PHYSDISK0_STATUS_MISSING
5239 ? "missing"
5240 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
5241 ? "not compatible"
5242 : state == MPI_PHYSDISK0_STATUS_FAILED
5243 ? "failed"
5244 : state == MPI_PHYSDISK0_STATUS_INITIALIZING
5245 ? "initializing"
5246 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
5247 ? "offline requested"
5248 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
5249 ? "failed requested"
5250 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
5251 ? "offline"
5252 : "state unknown",
5253 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
5254 ? ", out of sync" : "",
5255 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
5256 ? ", quiesced" : "" );
5257 break;
5258
5259 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
5260 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
5261 ioc->name, disk);
5262 break;
5263
5264 case MPI_EVENT_RAID_RC_SMART_DATA:
5265 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
5266 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
5267 break;
5268
5269 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
5270 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
5271 ioc->name, disk);
5272 break;
5273 }
5274}
5275
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286
5287static int
5288GetIoUnitPage2(MPT_ADAPTER *ioc)
5289{
5290 ConfigPageHeader_t hdr;
5291 CONFIGPARMS cfg;
5292 IOUnitPage2_t *ppage_alloc;
5293 dma_addr_t page_dma;
5294 int data_sz;
5295 int rc;
5296
5297
5298 hdr.PageVersion = 0;
5299 hdr.PageLength = 0;
5300 hdr.PageNumber = 2;
5301 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
5302 cfg.cfghdr.hdr = &hdr;
5303 cfg.physAddr = -1;
5304 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5305 cfg.dir = 0;
5306 cfg.pageAddr = 0;
5307 cfg.timeout = 0;
5308
5309 if ((rc = mpt_config(ioc, &cfg)) != 0)
5310 return rc;
5311
5312 if (hdr.PageLength == 0)
5313 return 0;
5314
5315
5316 data_sz = hdr.PageLength * 4;
5317 rc = -ENOMEM;
5318 ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
5319 if (ppage_alloc) {
5320 memset((u8 *)ppage_alloc, 0, data_sz);
5321 cfg.physAddr = page_dma;
5322 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5323
5324
5325 if ((rc = mpt_config(ioc, &cfg)) == 0)
5326 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
5327
5328 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
5329 }
5330
5331 return rc;
5332}
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355static int
5356mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
5357{
5358 u8 *pbuf;
5359 dma_addr_t buf_dma;
5360 CONFIGPARMS cfg;
5361 ConfigPageHeader_t header;
5362 int ii;
5363 int data, rc = 0;
5364
5365
5366
5367 if (!ioc->spi_data.nvram) {
5368 int sz;
5369 u8 *mem;
5370 sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
5371 mem = kmalloc(sz, GFP_ATOMIC);
5372 if (mem == NULL)
5373 return -EFAULT;
5374
5375 ioc->spi_data.nvram = (int *) mem;
5376
5377 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
5378 ioc->name, ioc->spi_data.nvram, sz));
5379 }
5380
5381
5382
5383 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5384 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
5385 }
5386
5387
5388
5389 header.PageVersion = 0;
5390 header.PageLength = 0;
5391 header.PageNumber = 0;
5392 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5393 cfg.cfghdr.hdr = &header;
5394 cfg.physAddr = -1;
5395 cfg.pageAddr = portnum;
5396 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5397 cfg.dir = 0;
5398 cfg.timeout = 0;
5399 if (mpt_config(ioc, &cfg) != 0)
5400 return -EFAULT;
5401
5402 if (header.PageLength > 0) {
5403 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5404 if (pbuf) {
5405 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5406 cfg.physAddr = buf_dma;
5407 if (mpt_config(ioc, &cfg) != 0) {
5408 ioc->spi_data.maxBusWidth = MPT_NARROW;
5409 ioc->spi_data.maxSyncOffset = 0;
5410 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5411 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
5412 rc = 1;
5413 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5414 "Unable to read PortPage0 minSyncFactor=%x\n",
5415 ioc->name, ioc->spi_data.minSyncFactor));
5416 } else {
5417
5418
5419 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
5420 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
5421 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
5422
5423 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
5424 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
5425 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5426 "noQas due to Capabilities=%x\n",
5427 ioc->name, pPP0->Capabilities));
5428 }
5429 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
5430 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
5431 if (data) {
5432 ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
5433 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
5434 ioc->spi_data.minSyncFactor = (u8) (data >> 8);
5435 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5436 "PortPage0 minSyncFactor=%x\n",
5437 ioc->name, ioc->spi_data.minSyncFactor));
5438 } else {
5439 ioc->spi_data.maxSyncOffset = 0;
5440 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5441 }
5442
5443 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
5444
5445
5446
5447 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
5448 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
5449
5450 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
5451 ioc->spi_data.minSyncFactor = MPT_ULTRA;
5452 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5453 "HVD or SE detected, minSyncFactor=%x\n",
5454 ioc->name, ioc->spi_data.minSyncFactor));
5455 }
5456 }
5457 }
5458 if (pbuf) {
5459 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5460 }
5461 }
5462 }
5463
5464
5465
5466 header.PageVersion = 0;
5467 header.PageLength = 0;
5468 header.PageNumber = 2;
5469 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5470 cfg.cfghdr.hdr = &header;
5471 cfg.physAddr = -1;
5472 cfg.pageAddr = portnum;
5473 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5474 cfg.dir = 0;
5475 if (mpt_config(ioc, &cfg) != 0)
5476 return -EFAULT;
5477
5478 if (header.PageLength > 0) {
5479
5480
5481 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5482 if (pbuf) {
5483 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
5484 cfg.physAddr = buf_dma;
5485 if (mpt_config(ioc, &cfg) != 0) {
5486
5487
5488 rc = 1;
5489 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
5490
5491
5492
5493 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
5494 ATTODeviceInfo_t *pdevice = NULL;
5495 u16 ATTOFlags;
5496
5497
5498
5499
5500 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5501 pdevice = &pPP2->DeviceSettings[ii];
5502 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
5503 data = 0;
5504
5505
5506
5507 if (ATTOFlags & ATTOFLAG_DISC)
5508 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
5509 if (ATTOFlags & ATTOFLAG_ID_ENB)
5510 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
5511 if (ATTOFlags & ATTOFLAG_LUN_ENB)
5512 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
5513 if (ATTOFlags & ATTOFLAG_TAGGED)
5514 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
5515 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
5516 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
5517
5518 data = (data << 16) | (pdevice->Period << 8) | 10;
5519 ioc->spi_data.nvram[ii] = data;
5520 }
5521 } else {
5522 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
5523 MpiDeviceInfo_t *pdevice = NULL;
5524
5525
5526
5527
5528 ioc->spi_data.bus_reset =
5529 (le32_to_cpu(pPP2->PortFlags) &
5530 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
5531 0 : 1 ;
5532
5533
5534
5535
5536 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
5537 ioc->spi_data.PortFlags = data;
5538 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5539 pdevice = &pPP2->DeviceSettings[ii];
5540 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
5541 (pdevice->SyncFactor << 8) | pdevice->Timeout;
5542 ioc->spi_data.nvram[ii] = data;
5543 }
5544 }
5545
5546 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5547 }
5548 }
5549
5550
5551
5552
5553
5554
5555 return rc;
5556}
5557
5558
5559
5560
5561
5562
5563
5564
5565
5566
5567static int
5568mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
5569{
5570 CONFIGPARMS cfg;
5571 ConfigPageHeader_t header;
5572
5573
5574
5575 header.PageVersion = 0;
5576 header.PageLength = 0;
5577 header.PageNumber = 1;
5578 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5579 cfg.cfghdr.hdr = &header;
5580 cfg.physAddr = -1;
5581 cfg.pageAddr = portnum;
5582 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5583 cfg.dir = 0;
5584 cfg.timeout = 0;
5585 if (mpt_config(ioc, &cfg) != 0)
5586 return -EFAULT;
5587
5588 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
5589 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
5590
5591 header.PageVersion = 0;
5592 header.PageLength = 0;
5593 header.PageNumber = 0;
5594 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5595 if (mpt_config(ioc, &cfg) != 0)
5596 return -EFAULT;
5597
5598 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
5599 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
5600
5601 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
5602 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
5603
5604 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
5605 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
5606 return 0;
5607}
5608
5609
5610
5611
5612
5613static void
5614mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
5615{
5616 struct inactive_raid_component_info *component_info, *pNext;
5617
5618 if (list_empty(&ioc->raid_data.inactive_list))
5619 return;
5620
5621 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5622 list_for_each_entry_safe(component_info, pNext,
5623 &ioc->raid_data.inactive_list, list) {
5624 list_del(&component_info->list);
5625 kfree(component_info);
5626 }
5627 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5628}
5629
5630
5631
5632
5633
5634
5635
5636
5637static void
5638mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
5639{
5640 CONFIGPARMS cfg;
5641 ConfigPageHeader_t hdr;
5642 dma_addr_t dma_handle;
5643 pRaidVolumePage0_t buffer = NULL;
5644 int i;
5645 RaidPhysDiskPage0_t phys_disk;
5646 struct inactive_raid_component_info *component_info;
5647 int handle_inactive_volumes;
5648
5649 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5650 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5651 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
5652 cfg.pageAddr = (channel << 8) + id;
5653 cfg.cfghdr.hdr = &hdr;
5654 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5655
5656 if (mpt_config(ioc, &cfg) != 0)
5657 goto out;
5658
5659 if (!hdr.PageLength)
5660 goto out;
5661
5662 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5663 &dma_handle);
5664
5665 if (!buffer)
5666 goto out;
5667
5668 cfg.physAddr = dma_handle;
5669 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5670
5671 if (mpt_config(ioc, &cfg) != 0)
5672 goto out;
5673
5674 if (!buffer->NumPhysDisks)
5675 goto out;
5676
5677 handle_inactive_volumes =
5678 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
5679 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
5680 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
5681 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
5682
5683 if (!handle_inactive_volumes)
5684 goto out;
5685
5686 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5687 for (i = 0; i < buffer->NumPhysDisks; i++) {
5688 if(mpt_raid_phys_disk_pg0(ioc,
5689 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
5690 continue;
5691
5692 if ((component_info = kmalloc(sizeof (*component_info),
5693 GFP_KERNEL)) == NULL)
5694 continue;
5695
5696 component_info->volumeID = id;
5697 component_info->volumeBus = channel;
5698 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
5699 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
5700 component_info->d.PhysDiskID = phys_disk.PhysDiskID;
5701 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
5702
5703 list_add_tail(&component_info->list,
5704 &ioc->raid_data.inactive_list);
5705 }
5706 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5707
5708 out:
5709 if (buffer)
5710 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5711 dma_handle);
5712}
5713
5714
5715
5716
5717
5718
5719
5720
5721
5722
5723
5724
5725int
5726mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
5727 RaidPhysDiskPage0_t *phys_disk)
5728{
5729 CONFIGPARMS cfg;
5730 ConfigPageHeader_t hdr;
5731 dma_addr_t dma_handle;
5732 pRaidPhysDiskPage0_t buffer = NULL;
5733 int rc;
5734
5735 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5736 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5737 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
5738
5739 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
5740 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5741 cfg.cfghdr.hdr = &hdr;
5742 cfg.physAddr = -1;
5743 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5744
5745 if (mpt_config(ioc, &cfg) != 0) {
5746 rc = -EFAULT;
5747 goto out;
5748 }
5749
5750 if (!hdr.PageLength) {
5751 rc = -EFAULT;
5752 goto out;
5753 }
5754
5755 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5756 &dma_handle);
5757
5758 if (!buffer) {
5759 rc = -ENOMEM;
5760 goto out;
5761 }
5762
5763 cfg.physAddr = dma_handle;
5764 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5765 cfg.pageAddr = phys_disk_num;
5766
5767 if (mpt_config(ioc, &cfg) != 0) {
5768 rc = -EFAULT;
5769 goto out;
5770 }
5771
5772 rc = 0;
5773 memcpy(phys_disk, buffer, sizeof(*buffer));
5774 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
5775
5776 out:
5777
5778 if (buffer)
5779 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5780 dma_handle);
5781
5782 return rc;
5783}
5784
5785
5786
5787
5788
5789
5790
5791
5792
5793int
5794mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
5795{
5796 CONFIGPARMS cfg;
5797 ConfigPageHeader_t hdr;
5798 dma_addr_t dma_handle;
5799 pRaidPhysDiskPage1_t buffer = NULL;
5800 int rc;
5801
5802 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5803 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5804
5805 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5806 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5807 hdr.PageNumber = 1;
5808 cfg.cfghdr.hdr = &hdr;
5809 cfg.physAddr = -1;
5810 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5811
5812 if (mpt_config(ioc, &cfg) != 0) {
5813 rc = 0;
5814 goto out;
5815 }
5816
5817 if (!hdr.PageLength) {
5818 rc = 0;
5819 goto out;
5820 }
5821
5822 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5823 &dma_handle);
5824
5825 if (!buffer) {
5826 rc = 0;
5827 goto out;
5828 }
5829
5830 cfg.physAddr = dma_handle;
5831 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5832 cfg.pageAddr = phys_disk_num;
5833
5834 if (mpt_config(ioc, &cfg) != 0) {
5835 rc = 0;
5836 goto out;
5837 }
5838
5839 rc = buffer->NumPhysDiskPaths;
5840 out:
5841
5842 if (buffer)
5843 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5844 dma_handle);
5845
5846 return rc;
5847}
5848EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
5849
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861int
5862mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
5863 RaidPhysDiskPage1_t *phys_disk)
5864{
5865 CONFIGPARMS cfg;
5866 ConfigPageHeader_t hdr;
5867 dma_addr_t dma_handle;
5868 pRaidPhysDiskPage1_t buffer = NULL;
5869 int rc;
5870 int i;
5871 __le64 sas_address;
5872
5873 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5874 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5875 rc = 0;
5876
5877 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5878 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5879 hdr.PageNumber = 1;
5880 cfg.cfghdr.hdr = &hdr;
5881 cfg.physAddr = -1;
5882 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5883
5884 if (mpt_config(ioc, &cfg) != 0) {
5885 rc = -EFAULT;
5886 goto out;
5887 }
5888
5889 if (!hdr.PageLength) {
5890 rc = -EFAULT;
5891 goto out;
5892 }
5893
5894 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5895 &dma_handle);
5896
5897 if (!buffer) {
5898 rc = -ENOMEM;
5899 goto out;
5900 }
5901
5902 cfg.physAddr = dma_handle;
5903 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5904 cfg.pageAddr = phys_disk_num;
5905
5906 if (mpt_config(ioc, &cfg) != 0) {
5907 rc = -EFAULT;
5908 goto out;
5909 }
5910
5911 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
5912 phys_disk->PhysDiskNum = phys_disk_num;
5913 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
5914 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
5915 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
5916 phys_disk->Path[i].OwnerIdentifier =
5917 buffer->Path[i].OwnerIdentifier;
5918 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
5919 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
5920 sas_address = le64_to_cpu(sas_address);
5921 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
5922 memcpy(&sas_address,
5923 &buffer->Path[i].OwnerWWID, sizeof(__le64));
5924 sas_address = le64_to_cpu(sas_address);
5925 memcpy(&phys_disk->Path[i].OwnerWWID,
5926 &sas_address, sizeof(__le64));
5927 }
5928
5929 out:
5930
5931 if (buffer)
5932 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5933 dma_handle);
5934
5935 return rc;
5936}
5937EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
5938
5939
5940
5941
5942
5943
5944
5945
5946
5947
5948
5949int
5950mpt_findImVolumes(MPT_ADAPTER *ioc)
5951{
5952 IOCPage2_t *pIoc2;
5953 u8 *mem;
5954 dma_addr_t ioc2_dma;
5955 CONFIGPARMS cfg;
5956 ConfigPageHeader_t header;
5957 int rc = 0;
5958 int iocpage2sz;
5959 int i;
5960
5961 if (!ioc->ir_firmware)
5962 return 0;
5963
5964
5965
5966 kfree(ioc->raid_data.pIocPg2);
5967 ioc->raid_data.pIocPg2 = NULL;
5968 mpt_inactive_raid_list_free(ioc);
5969
5970
5971
5972 header.PageVersion = 0;
5973 header.PageLength = 0;
5974 header.PageNumber = 2;
5975 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5976 cfg.cfghdr.hdr = &header;
5977 cfg.physAddr = -1;
5978 cfg.pageAddr = 0;
5979 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5980 cfg.dir = 0;
5981 cfg.timeout = 0;
5982 if (mpt_config(ioc, &cfg) != 0)
5983 return -EFAULT;
5984
5985 if (header.PageLength == 0)
5986 return -EFAULT;
5987
5988 iocpage2sz = header.PageLength * 4;
5989 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
5990 if (!pIoc2)
5991 return -ENOMEM;
5992
5993 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5994 cfg.physAddr = ioc2_dma;
5995 if (mpt_config(ioc, &cfg) != 0)
5996 goto out;
5997
5998 mem = kmalloc(iocpage2sz, GFP_KERNEL);
5999 if (!mem) {
6000 rc = -ENOMEM;
6001 goto out;
6002 }
6003
6004 memcpy(mem, (u8 *)pIoc2, iocpage2sz);
6005 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
6006
6007 mpt_read_ioc_pg_3(ioc);
6008
6009 for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
6010 mpt_inactive_raid_volumes(ioc,
6011 pIoc2->RaidVolume[i].VolumeBus,
6012 pIoc2->RaidVolume[i].VolumeID);
6013
6014 out:
6015 pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
6016
6017 return rc;
6018}
6019
6020static int
6021mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
6022{
6023 IOCPage3_t *pIoc3;
6024 u8 *mem;
6025 CONFIGPARMS cfg;
6026 ConfigPageHeader_t header;
6027 dma_addr_t ioc3_dma;
6028 int iocpage3sz = 0;
6029
6030
6031
6032 kfree(ioc->raid_data.pIocPg3);
6033 ioc->raid_data.pIocPg3 = NULL;
6034
6035
6036
6037
6038 header.PageVersion = 0;
6039 header.PageLength = 0;
6040 header.PageNumber = 3;
6041 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6042 cfg.cfghdr.hdr = &header;
6043 cfg.physAddr = -1;
6044 cfg.pageAddr = 0;
6045 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6046 cfg.dir = 0;
6047 cfg.timeout = 0;
6048 if (mpt_config(ioc, &cfg) != 0)
6049 return 0;
6050
6051 if (header.PageLength == 0)
6052 return 0;
6053
6054
6055
6056 iocpage3sz = header.PageLength * 4;
6057 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
6058 if (!pIoc3)
6059 return 0;
6060
6061
6062
6063
6064 cfg.physAddr = ioc3_dma;
6065 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6066 if (mpt_config(ioc, &cfg) == 0) {
6067 mem = kmalloc(iocpage3sz, GFP_KERNEL);
6068 if (mem) {
6069 memcpy(mem, (u8 *)pIoc3, iocpage3sz);
6070 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
6071 }
6072 }
6073
6074 pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
6075
6076 return 0;
6077}
6078
6079static void
6080mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
6081{
6082 IOCPage4_t *pIoc4;
6083 CONFIGPARMS cfg;
6084 ConfigPageHeader_t header;
6085 dma_addr_t ioc4_dma;
6086 int iocpage4sz;
6087
6088
6089
6090 header.PageVersion = 0;
6091 header.PageLength = 0;
6092 header.PageNumber = 4;
6093 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6094 cfg.cfghdr.hdr = &header;
6095 cfg.physAddr = -1;
6096 cfg.pageAddr = 0;
6097 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6098 cfg.dir = 0;
6099 cfg.timeout = 0;
6100 if (mpt_config(ioc, &cfg) != 0)
6101 return;
6102
6103 if (header.PageLength == 0)
6104 return;
6105
6106 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
6107 iocpage4sz = (header.PageLength + 4) * 4;
6108 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
6109 if (!pIoc4)
6110 return;
6111 ioc->alloc_total += iocpage4sz;
6112 } else {
6113 ioc4_dma = ioc->spi_data.IocPg4_dma;
6114 iocpage4sz = ioc->spi_data.IocPg4Sz;
6115 }
6116
6117
6118
6119 cfg.physAddr = ioc4_dma;
6120 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6121 if (mpt_config(ioc, &cfg) == 0) {
6122 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
6123 ioc->spi_data.IocPg4_dma = ioc4_dma;
6124 ioc->spi_data.IocPg4Sz = iocpage4sz;
6125 } else {
6126 pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
6127 ioc->spi_data.pIocPg4 = NULL;
6128 ioc->alloc_total -= iocpage4sz;
6129 }
6130}
6131
6132static void
6133mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
6134{
6135 IOCPage1_t *pIoc1;
6136 CONFIGPARMS cfg;
6137 ConfigPageHeader_t header;
6138 dma_addr_t ioc1_dma;
6139 int iocpage1sz = 0;
6140 u32 tmp;
6141
6142
6143
6144 header.PageVersion = 0;
6145 header.PageLength = 0;
6146 header.PageNumber = 1;
6147 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6148 cfg.cfghdr.hdr = &header;
6149 cfg.physAddr = -1;
6150 cfg.pageAddr = 0;
6151 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6152 cfg.dir = 0;
6153 cfg.timeout = 0;
6154 if (mpt_config(ioc, &cfg) != 0)
6155 return;
6156
6157 if (header.PageLength == 0)
6158 return;
6159
6160
6161
6162 iocpage1sz = header.PageLength * 4;
6163 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
6164 if (!pIoc1)
6165 return;
6166
6167
6168
6169 cfg.physAddr = ioc1_dma;
6170 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6171 if (mpt_config(ioc, &cfg) == 0) {
6172
6173 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
6174 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
6175 tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
6176
6177 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
6178 ioc->name, tmp));
6179
6180 if (tmp > MPT_COALESCING_TIMEOUT) {
6181 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
6182
6183
6184
6185 cfg.dir = 1;
6186 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
6187 if (mpt_config(ioc, &cfg) == 0) {
6188 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
6189 ioc->name, MPT_COALESCING_TIMEOUT));
6190
6191 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
6192 if (mpt_config(ioc, &cfg) == 0) {
6193 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6194 "Reset NVRAM Coalescing Timeout to = %d\n",
6195 ioc->name, MPT_COALESCING_TIMEOUT));
6196 } else {
6197 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6198 "Reset NVRAM Coalescing Timeout Failed\n",
6199 ioc->name));
6200 }
6201
6202 } else {
6203 dprintk(ioc, printk(MYIOC_s_WARN_FMT
6204 "Reset of Current Coalescing Timeout Failed!\n",
6205 ioc->name));
6206 }
6207 }
6208
6209 } else {
6210 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
6211 }
6212 }
6213
6214 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
6215
6216 return;
6217}
6218
6219static void
6220mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
6221{
6222 CONFIGPARMS cfg;
6223 ConfigPageHeader_t hdr;
6224 dma_addr_t buf_dma;
6225 ManufacturingPage0_t *pbuf = NULL;
6226
6227 memset(&cfg, 0 , sizeof(CONFIGPARMS));
6228 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
6229
6230 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
6231 cfg.cfghdr.hdr = &hdr;
6232 cfg.physAddr = -1;
6233 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6234 cfg.timeout = 10;
6235
6236 if (mpt_config(ioc, &cfg) != 0)
6237 goto out;
6238
6239 if (!cfg.cfghdr.hdr->PageLength)
6240 goto out;
6241
6242 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6243 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
6244 if (!pbuf)
6245 goto out;
6246
6247 cfg.physAddr = buf_dma;
6248
6249 if (mpt_config(ioc, &cfg) != 0)
6250 goto out;
6251
6252 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
6253 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
6254 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
6255
6256out:
6257
6258 if (pbuf)
6259 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
6260}
6261
6262
6263
6264
6265
6266
6267
6268
6269static int
6270SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
6271{
6272 EventNotification_t evn;
6273 MPIDefaultReply_t reply_buf;
6274
6275 memset(&evn, 0, sizeof(EventNotification_t));
6276 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
6277
6278 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
6279 evn.Switch = EvSwitch;
6280 evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
6281
6282 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6283 "Sending EventNotification (%d) request %p\n",
6284 ioc->name, EvSwitch, &evn));
6285
6286 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
6287 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
6288 sleepFlag);
6289}
6290
6291
6292
6293
6294
6295
6296
6297static int
6298SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
6299{
6300 EventAck_t *pAck;
6301
6302 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6303 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
6304 ioc->name, __func__));
6305 return -1;
6306 }
6307
6308 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
6309
6310 pAck->Function = MPI_FUNCTION_EVENT_ACK;
6311 pAck->ChainOffset = 0;
6312 pAck->Reserved[0] = pAck->Reserved[1] = 0;
6313 pAck->MsgFlags = 0;
6314 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
6315 pAck->Event = evnp->Event;
6316 pAck->EventContext = evnp->EventContext;
6317
6318 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
6319
6320 return 0;
6321}
6322
6323
6324
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335
6336
6337int
6338mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
6339{
6340 Config_t *pReq;
6341 ConfigReply_t *pReply;
6342 ConfigExtendedPageHeader_t *pExtHdr = NULL;
6343 MPT_FRAME_HDR *mf;
6344 int ii;
6345 int flagsLength;
6346 long timeout;
6347 int ret;
6348 u8 page_type = 0, extend_page;
6349 unsigned long timeleft;
6350 unsigned long flags;
6351 int in_isr;
6352 u8 issue_hard_reset = 0;
6353 u8 retry_count = 0;
6354
6355
6356
6357
6358 in_isr = in_interrupt();
6359 if (in_isr) {
6360 dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
6361 ioc->name));
6362 return -EPERM;
6363 }
6364
6365
6366 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6367 if (ioc->ioc_reset_in_progress) {
6368 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6369 "%s: busy with host reset\n", ioc->name, __func__));
6370 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6371 return -EBUSY;
6372 }
6373 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6374
6375
6376 if (!ioc->active ||
6377 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
6378 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6379 "%s: ioc not operational, %d, %xh\n",
6380 ioc->name, __func__, ioc->active,
6381 mpt_GetIocState(ioc, 0)));
6382 return -EFAULT;
6383 }
6384
6385 retry_config:
6386 mutex_lock(&ioc->mptbase_cmds.mutex);
6387
6388 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
6389 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
6390
6391
6392
6393 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6394 dcprintk(ioc, printk(MYIOC_s_WARN_FMT
6395 "mpt_config: no msg frames!\n", ioc->name));
6396 ret = -EAGAIN;
6397 goto out;
6398 }
6399
6400 pReq = (Config_t *)mf;
6401 pReq->Action = pCfg->action;
6402 pReq->Reserved = 0;
6403 pReq->ChainOffset = 0;
6404 pReq->Function = MPI_FUNCTION_CONFIG;
6405
6406
6407 pReq->ExtPageLength = 0;
6408 pReq->ExtPageType = 0;
6409 pReq->MsgFlags = 0;
6410
6411 for (ii=0; ii < 8; ii++)
6412 pReq->Reserved2[ii] = 0;
6413
6414 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
6415 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
6416 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
6417 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
6418
6419 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
6420 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
6421 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
6422 pReq->ExtPageType = pExtHdr->ExtPageType;
6423 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
6424
6425
6426
6427
6428 pReq->Header.PageLength = 0;
6429 }
6430
6431 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
6432
6433
6434
6435 if (pCfg->dir)
6436 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
6437 else
6438 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
6439
6440 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
6441 MPI_CONFIG_PAGETYPE_EXTENDED) {
6442 flagsLength |= pExtHdr->ExtPageLength * 4;
6443 page_type = pReq->ExtPageType;
6444 extend_page = 1;
6445 } else {
6446 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
6447 page_type = pReq->Header.PageType;
6448 extend_page = 0;
6449 }
6450
6451 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6452 "Sending Config request type 0x%x, page 0x%x and action %d\n",
6453 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
6454
6455 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
6456 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
6457 mpt_put_msg_frame(mpt_base_index, ioc, mf);
6458 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
6459 timeout);
6460 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
6461 ret = -ETIME;
6462 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6463 "Failed Sending Config request type 0x%x, page 0x%x,"
6464 " action %d, status %xh, time left %ld\n\n",
6465 ioc->name, page_type, pReq->Header.PageNumber,
6466 pReq->Action, ioc->mptbase_cmds.status, timeleft));
6467 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
6468 goto out;
6469 if (!timeleft) {
6470 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6471 if (ioc->ioc_reset_in_progress) {
6472 spin_unlock_irqrestore(&ioc->taskmgmt_lock,
6473 flags);
6474 printk(MYIOC_s_INFO_FMT "%s: host reset in"
6475 " progress mpt_config timed out.!!\n",
6476 __func__, ioc->name);
6477 mutex_unlock(&ioc->mptbase_cmds.mutex);
6478 return -EFAULT;
6479 }
6480 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6481 issue_hard_reset = 1;
6482 }
6483 goto out;
6484 }
6485
6486 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
6487 ret = -1;
6488 goto out;
6489 }
6490 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
6491 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
6492 if (ret == MPI_IOCSTATUS_SUCCESS) {
6493 if (extend_page) {
6494 pCfg->cfghdr.ehdr->ExtPageLength =
6495 le16_to_cpu(pReply->ExtPageLength);
6496 pCfg->cfghdr.ehdr->ExtPageType =
6497 pReply->ExtPageType;
6498 }
6499 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
6500 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
6501 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
6502 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
6503
6504 }
6505
6506 if (retry_count)
6507 printk(MYIOC_s_INFO_FMT "Retry completed "
6508 "ret=0x%x timeleft=%ld\n",
6509 ioc->name, ret, timeleft);
6510
6511 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
6512 ret, le32_to_cpu(pReply->IOCLogInfo)));
6513
6514out:
6515
6516 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
6517 mutex_unlock(&ioc->mptbase_cmds.mutex);
6518 if (issue_hard_reset) {
6519 issue_hard_reset = 0;
6520 printk(MYIOC_s_WARN_FMT
6521 "Issuing Reset from %s!!, doorbell=0x%08x\n",
6522 ioc->name, __func__, mpt_GetIocState(ioc, 0));
6523 if (retry_count == 0) {
6524 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
6525 retry_count++;
6526 } else
6527 mpt_HardResetHandler(ioc, CAN_SLEEP);
6528
6529 mpt_free_msg_frame(ioc, mf);
6530
6531 if (retry_count < 2) {
6532 printk(MYIOC_s_INFO_FMT
6533 "Attempting Retry Config request"
6534 " type 0x%x, page 0x%x,"
6535 " action %d\n", ioc->name, page_type,
6536 pCfg->cfghdr.hdr->PageNumber, pCfg->action);
6537 retry_count++;
6538 goto retry_config;
6539 }
6540 }
6541 return ret;
6542
6543}
6544
6545
6546
6547
6548
6549
6550
6551
6552
6553static int
6554mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
6555{
6556 switch (reset_phase) {
6557 case MPT_IOC_SETUP_RESET:
6558 ioc->taskmgmt_quiesce_io = 1;
6559 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6560 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
6561 break;
6562 case MPT_IOC_PRE_RESET:
6563 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6564 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
6565 break;
6566 case MPT_IOC_POST_RESET:
6567 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6568 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
6569
6570 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
6571 ioc->mptbase_cmds.status |=
6572 MPT_MGMT_STATUS_DID_IOCRESET;
6573 complete(&ioc->mptbase_cmds.done);
6574 }
6575
6576 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
6577 ioc->taskmgmt_cmds.status |=
6578 MPT_MGMT_STATUS_DID_IOCRESET;
6579 complete(&ioc->taskmgmt_cmds.done);
6580 }
6581 break;
6582 default:
6583 break;
6584 }
6585
6586 return 1;
6587}
6588
6589
6590#ifdef CONFIG_PROC_FS
6591
6592
6593
6594
6595
6596
6597
6598
6599
6600
6601static int
6602procmpt_create(void)
6603{
6604 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
6605 if (mpt_proc_root_dir == NULL)
6606 return -ENOTDIR;
6607
6608 proc_create("summary", S_IRUGO, mpt_proc_root_dir, &mpt_summary_proc_fops);
6609 proc_create("version", S_IRUGO, mpt_proc_root_dir, &mpt_version_proc_fops);
6610 return 0;
6611}
6612
6613
6614
6615
6616
6617
6618
6619static void
6620procmpt_destroy(void)
6621{
6622 remove_proc_entry("version", mpt_proc_root_dir);
6623 remove_proc_entry("summary", mpt_proc_root_dir);
6624 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
6625}
6626
6627
6628
6629
6630
6631static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
6632
6633static int mpt_summary_proc_show(struct seq_file *m, void *v)
6634{
6635 MPT_ADAPTER *ioc = m->private;
6636
6637 if (ioc) {
6638 seq_mpt_print_ioc_summary(ioc, m, 1);
6639 } else {
6640 list_for_each_entry(ioc, &ioc_list, list) {
6641 seq_mpt_print_ioc_summary(ioc, m, 1);
6642 }
6643 }
6644
6645 return 0;
6646}
6647
6648static int mpt_summary_proc_open(struct inode *inode, struct file *file)
6649{
6650 return single_open(file, mpt_summary_proc_show, PDE_DATA(inode));
6651}
6652
6653static const struct file_operations mpt_summary_proc_fops = {
6654 .owner = THIS_MODULE,
6655 .open = mpt_summary_proc_open,
6656 .read = seq_read,
6657 .llseek = seq_lseek,
6658 .release = single_release,
6659};
6660
6661static int mpt_version_proc_show(struct seq_file *m, void *v)
6662{
6663 u8 cb_idx;
6664 int scsi, fc, sas, lan, ctl, targ, dmp;
6665 char *drvname;
6666
6667 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
6668 seq_printf(m, " Fusion MPT base driver\n");
6669
6670 scsi = fc = sas = lan = ctl = targ = dmp = 0;
6671 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6672 drvname = NULL;
6673 if (MptCallbacks[cb_idx]) {
6674 switch (MptDriverClass[cb_idx]) {
6675 case MPTSPI_DRIVER:
6676 if (!scsi++) drvname = "SPI host";
6677 break;
6678 case MPTFC_DRIVER:
6679 if (!fc++) drvname = "FC host";
6680 break;
6681 case MPTSAS_DRIVER:
6682 if (!sas++) drvname = "SAS host";
6683 break;
6684 case MPTLAN_DRIVER:
6685 if (!lan++) drvname = "LAN";
6686 break;
6687 case MPTSTM_DRIVER:
6688 if (!targ++) drvname = "SCSI target";
6689 break;
6690 case MPTCTL_DRIVER:
6691 if (!ctl++) drvname = "ioctl";
6692 break;
6693 }
6694
6695 if (drvname)
6696 seq_printf(m, " Fusion MPT %s driver\n", drvname);
6697 }
6698 }
6699
6700 return 0;
6701}
6702
6703static int mpt_version_proc_open(struct inode *inode, struct file *file)
6704{
6705 return single_open(file, mpt_version_proc_show, NULL);
6706}
6707
6708static const struct file_operations mpt_version_proc_fops = {
6709 .owner = THIS_MODULE,
6710 .open = mpt_version_proc_open,
6711 .read = seq_read,
6712 .llseek = seq_lseek,
6713 .release = single_release,
6714};
6715
6716static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
6717{
6718 MPT_ADAPTER *ioc = m->private;
6719 char expVer[32];
6720 int sz;
6721 int p;
6722
6723 mpt_get_fw_exp_ver(expVer, ioc);
6724
6725 seq_printf(m, "%s:", ioc->name);
6726 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
6727 seq_printf(m, " (f/w download boot flag set)");
6728
6729
6730
6731 seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
6732 ioc->facts.ProductID,
6733 ioc->prod_name);
6734 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
6735 if (ioc->facts.FWImageSize)
6736 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
6737 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
6738 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
6739 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
6740
6741 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
6742 ioc->facts.CurrentHostMfaHighAddr);
6743 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
6744 ioc->facts.CurrentSenseBufferHighAddr);
6745
6746 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
6747 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
6748
6749 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
6750 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
6751
6752
6753
6754 sz = (ioc->req_sz * ioc->req_depth) + 128;
6755 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
6756 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
6757 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
6758 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
6759 4*ioc->facts.RequestFrameSize,
6760 ioc->facts.GlobalCredits);
6761
6762 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
6763 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
6764 sz = (ioc->reply_sz * ioc->reply_depth) + 128;
6765 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
6766 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
6767 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
6768 ioc->facts.CurReplyFrameSize,
6769 ioc->facts.ReplyQueueDepth);
6770
6771 seq_printf(m, " MaxDevices = %d\n",
6772 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
6773 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
6774
6775
6776 for (p=0; p < ioc->facts.NumberOfPorts; p++) {
6777 seq_printf(m, " PortNumber = %d (of %d)\n",
6778 p+1,
6779 ioc->facts.NumberOfPorts);
6780 if (ioc->bus_type == FC) {
6781 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
6782 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6783 seq_printf(m, " LanAddr = %pMR\n", a);
6784 }
6785 seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
6786 ioc->fc_port_page0[p].WWNN.High,
6787 ioc->fc_port_page0[p].WWNN.Low,
6788 ioc->fc_port_page0[p].WWPN.High,
6789 ioc->fc_port_page0[p].WWPN.Low);
6790 }
6791 }
6792
6793 return 0;
6794}
6795
6796static int mpt_iocinfo_proc_open(struct inode *inode, struct file *file)
6797{
6798 return single_open(file, mpt_iocinfo_proc_show, PDE_DATA(inode));
6799}
6800
6801static const struct file_operations mpt_iocinfo_proc_fops = {
6802 .owner = THIS_MODULE,
6803 .open = mpt_iocinfo_proc_open,
6804 .read = seq_read,
6805 .llseek = seq_lseek,
6806 .release = single_release,
6807};
6808#endif
6809
6810
6811static void
6812mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
6813{
6814 buf[0] ='\0';
6815 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
6816 sprintf(buf, " (Exp %02d%02d)",
6817 (ioc->facts.FWVersion.Word >> 16) & 0x00FF,
6818 (ioc->facts.FWVersion.Word >> 8) & 0x1F);
6819
6820
6821 if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
6822 strcat(buf, " [MDBG]");
6823 }
6824}
6825
6826
6827
6828
6829
6830
6831
6832
6833
6834
6835
6836
6837
6838void
6839mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
6840{
6841 char expVer[32];
6842 int y;
6843
6844 mpt_get_fw_exp_ver(expVer, ioc);
6845
6846
6847
6848
6849 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6850 ioc->name,
6851 ioc->prod_name,
6852 MPT_FW_REV_MAGIC_ID_STRING,
6853 ioc->facts.FWVersion.Word,
6854 expVer,
6855 ioc->facts.NumberOfPorts,
6856 ioc->req_depth);
6857
6858 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6859 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6860 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
6861 }
6862
6863 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
6864
6865 if (!ioc->active)
6866 y += sprintf(buffer+len+y, " (disabled)");
6867
6868 y += sprintf(buffer+len+y, "\n");
6869
6870 *size = y;
6871}
6872
6873#ifdef CONFIG_PROC_FS
6874static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
6875{
6876 char expVer[32];
6877
6878 mpt_get_fw_exp_ver(expVer, ioc);
6879
6880
6881
6882
6883 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6884 ioc->name,
6885 ioc->prod_name,
6886 MPT_FW_REV_MAGIC_ID_STRING,
6887 ioc->facts.FWVersion.Word,
6888 expVer,
6889 ioc->facts.NumberOfPorts,
6890 ioc->req_depth);
6891
6892 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6893 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6894 seq_printf(m, ", LanAddr=%pMR", a);
6895 }
6896
6897 seq_printf(m, ", IRQ=%d", ioc->pci_irq);
6898
6899 if (!ioc->active)
6900 seq_printf(m, " (disabled)");
6901
6902 seq_putc(m, '\n');
6903}
6904#endif
6905
6906
6907
6908
6909
6910
6911
6912
6913
6914int
6915mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6916{
6917 unsigned long flags;
6918 int retval;
6919
6920 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6921 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
6922 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
6923 retval = -1;
6924 goto out;
6925 }
6926 retval = 0;
6927 ioc->taskmgmt_in_progress = 1;
6928 ioc->taskmgmt_quiesce_io = 1;
6929 if (ioc->alt_ioc) {
6930 ioc->alt_ioc->taskmgmt_in_progress = 1;
6931 ioc->alt_ioc->taskmgmt_quiesce_io = 1;
6932 }
6933 out:
6934 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6935 return retval;
6936}
6937EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
6938
6939
6940
6941
6942
6943
6944void
6945mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6946{
6947 unsigned long flags;
6948
6949 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6950 ioc->taskmgmt_in_progress = 0;
6951 ioc->taskmgmt_quiesce_io = 0;
6952 if (ioc->alt_ioc) {
6953 ioc->alt_ioc->taskmgmt_in_progress = 0;
6954 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
6955 }
6956 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6957}
6958EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
6959
6960
6961
6962
6963
6964
6965
6966
6967void
6968mpt_halt_firmware(MPT_ADAPTER *ioc)
6969{
6970 u32 ioc_raw_state;
6971
6972 ioc_raw_state = mpt_GetIocState(ioc, 0);
6973
6974 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
6975 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
6976 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6977 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
6978 ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6979 } else {
6980 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
6981 panic("%s: Firmware is halted due to command timeout\n",
6982 ioc->name);
6983 }
6984}
6985EXPORT_SYMBOL(mpt_halt_firmware);
6986
6987
6988
6989
6990
6991
6992
6993
6994
6995
6996
6997
6998
6999
7000static int
7001mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7002{
7003 int rc;
7004 int ii;
7005 u8 cb_idx;
7006 unsigned long flags;
7007 u32 ioc_state;
7008 unsigned long time_count;
7009
7010 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
7011 ioc->name));
7012
7013 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7014
7015 if (mpt_fwfault_debug)
7016 mpt_halt_firmware(ioc);
7017
7018 if (ioc_state == MPI_IOC_STATE_FAULT ||
7019 ioc_state == MPI_IOC_STATE_RESET) {
7020 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7021 "skipping, either in FAULT or RESET state!\n", ioc->name));
7022 return -1;
7023 }
7024
7025 if (ioc->bus_type == FC) {
7026 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7027 "skipping, because the bus type is FC!\n", ioc->name));
7028 return -1;
7029 }
7030
7031 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7032 if (ioc->ioc_reset_in_progress) {
7033 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7034 return -1;
7035 }
7036 ioc->ioc_reset_in_progress = 1;
7037 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7038
7039 rc = -1;
7040
7041 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7042 if (MptResetHandlers[cb_idx])
7043 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7044 }
7045
7046 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7047 if (ioc->taskmgmt_in_progress) {
7048 ioc->ioc_reset_in_progress = 0;
7049 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7050 return -1;
7051 }
7052 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7053
7054 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
7055 ioc->active = 0;
7056 time_count = jiffies;
7057
7058 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
7059
7060 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7061 if (MptResetHandlers[cb_idx])
7062 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
7063 }
7064
7065 if (rc)
7066 goto out;
7067
7068 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7069 if (ioc_state != MPI_IOC_STATE_READY)
7070 goto out;
7071
7072 for (ii = 0; ii < 5; ii++) {
7073
7074 rc = GetIocFacts(ioc, sleepFlag,
7075 MPT_HOSTEVENT_IOC_RECOVER);
7076 if (rc == 0)
7077 break;
7078 if (sleepFlag == CAN_SLEEP)
7079 msleep(100);
7080 else
7081 mdelay(100);
7082 }
7083 if (ii == 5)
7084 goto out;
7085
7086 rc = PrimeIocFifos(ioc);
7087 if (rc != 0)
7088 goto out;
7089
7090 rc = SendIocInit(ioc, sleepFlag);
7091 if (rc != 0)
7092 goto out;
7093
7094 rc = SendEventNotification(ioc, 1, sleepFlag);
7095 if (rc != 0)
7096 goto out;
7097
7098 if (ioc->hard_resets < -1)
7099 ioc->hard_resets++;
7100
7101
7102
7103
7104
7105 ioc->active = 1;
7106 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
7107
7108 out:
7109 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7110 ioc->ioc_reset_in_progress = 0;
7111 ioc->taskmgmt_quiesce_io = 0;
7112 ioc->taskmgmt_in_progress = 0;
7113 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7114
7115 if (ioc->active) {
7116 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7117 if (MptResetHandlers[cb_idx])
7118 mpt_signal_reset(cb_idx, ioc,
7119 MPT_IOC_POST_RESET);
7120 }
7121 }
7122
7123 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7124 "SoftResetHandler: completed (%d seconds): %s\n",
7125 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
7126 ((rc == 0) ? "SUCCESS" : "FAILED")));
7127
7128 return rc;
7129}
7130
7131
7132
7133
7134
7135
7136
7137
7138
7139
7140int
7141mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
7142 int ret = -1;
7143
7144 ret = mpt_SoftResetHandler(ioc, sleepFlag);
7145 if (ret == 0)
7146 return ret;
7147 ret = mpt_HardResetHandler(ioc, sleepFlag);
7148 return ret;
7149}
7150EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173int
7174mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7175{
7176 int rc;
7177 u8 cb_idx;
7178 unsigned long flags;
7179 unsigned long time_count;
7180
7181 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
7182#ifdef MFCNT
7183 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
7184 printk("MF count 0x%x !\n", ioc->mfcnt);
7185#endif
7186 if (mpt_fwfault_debug)
7187 mpt_halt_firmware(ioc);
7188
7189
7190
7191
7192 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7193 if (ioc->ioc_reset_in_progress) {
7194 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7195 ioc->wait_on_reset_completion = 1;
7196 do {
7197 ssleep(1);
7198 } while (ioc->ioc_reset_in_progress == 1);
7199 ioc->wait_on_reset_completion = 0;
7200 return ioc->reset_status;
7201 }
7202 if (ioc->wait_on_reset_completion) {
7203 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7204 rc = 0;
7205 time_count = jiffies;
7206 goto exit;
7207 }
7208 ioc->ioc_reset_in_progress = 1;
7209 if (ioc->alt_ioc)
7210 ioc->alt_ioc->ioc_reset_in_progress = 1;
7211 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7212
7213
7214
7215
7216
7217
7218
7219 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7220 if (MptResetHandlers[cb_idx]) {
7221 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7222 if (ioc->alt_ioc)
7223 mpt_signal_reset(cb_idx, ioc->alt_ioc,
7224 MPT_IOC_SETUP_RESET);
7225 }
7226 }
7227
7228 time_count = jiffies;
7229 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
7230 if (rc != 0) {
7231 printk(KERN_WARNING MYNAM
7232 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
7233 rc, ioc->name, mpt_GetIocState(ioc, 0));
7234 } else {
7235 if (ioc->hard_resets < -1)
7236 ioc->hard_resets++;
7237 }
7238
7239 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7240 ioc->ioc_reset_in_progress = 0;
7241 ioc->taskmgmt_quiesce_io = 0;
7242 ioc->taskmgmt_in_progress = 0;
7243 ioc->reset_status = rc;
7244 if (ioc->alt_ioc) {
7245 ioc->alt_ioc->ioc_reset_in_progress = 0;
7246 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
7247 ioc->alt_ioc->taskmgmt_in_progress = 0;
7248 }
7249 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7250
7251 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7252 if (MptResetHandlers[cb_idx]) {
7253 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
7254 if (ioc->alt_ioc)
7255 mpt_signal_reset(cb_idx,
7256 ioc->alt_ioc, MPT_IOC_POST_RESET);
7257 }
7258 }
7259exit:
7260 dtmprintk(ioc,
7261 printk(MYIOC_s_DEBUG_FMT
7262 "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
7263 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
7264 "SUCCESS" : "FAILED")));
7265
7266 return rc;
7267}
7268
7269#ifdef CONFIG_FUSION_LOGGING
7270static void
7271mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
7272{
7273 char *ds = NULL;
7274 u32 evData0;
7275 int ii;
7276 u8 event;
7277 char *evStr = ioc->evStr;
7278
7279 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7280 evData0 = le32_to_cpu(pEventReply->Data[0]);
7281
7282 switch(event) {
7283 case MPI_EVENT_NONE:
7284 ds = "None";
7285 break;
7286 case MPI_EVENT_LOG_DATA:
7287 ds = "Log Data";
7288 break;
7289 case MPI_EVENT_STATE_CHANGE:
7290 ds = "State Change";
7291 break;
7292 case MPI_EVENT_UNIT_ATTENTION:
7293 ds = "Unit Attention";
7294 break;
7295 case MPI_EVENT_IOC_BUS_RESET:
7296 ds = "IOC Bus Reset";
7297 break;
7298 case MPI_EVENT_EXT_BUS_RESET:
7299 ds = "External Bus Reset";
7300 break;
7301 case MPI_EVENT_RESCAN:
7302 ds = "Bus Rescan Event";
7303 break;
7304 case MPI_EVENT_LINK_STATUS_CHANGE:
7305 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
7306 ds = "Link Status(FAILURE) Change";
7307 else
7308 ds = "Link Status(ACTIVE) Change";
7309 break;
7310 case MPI_EVENT_LOOP_STATE_CHANGE:
7311 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
7312 ds = "Loop State(LIP) Change";
7313 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
7314 ds = "Loop State(LPE) Change";
7315 else
7316 ds = "Loop State(LPB) Change";
7317 break;
7318 case MPI_EVENT_LOGOUT:
7319 ds = "Logout";
7320 break;
7321 case MPI_EVENT_EVENT_CHANGE:
7322 if (evData0)
7323 ds = "Events ON";
7324 else
7325 ds = "Events OFF";
7326 break;
7327 case MPI_EVENT_INTEGRATED_RAID:
7328 {
7329 u8 ReasonCode = (u8)(evData0 >> 16);
7330 switch (ReasonCode) {
7331 case MPI_EVENT_RAID_RC_VOLUME_CREATED :
7332 ds = "Integrated Raid: Volume Created";
7333 break;
7334 case MPI_EVENT_RAID_RC_VOLUME_DELETED :
7335 ds = "Integrated Raid: Volume Deleted";
7336 break;
7337 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
7338 ds = "Integrated Raid: Volume Settings Changed";
7339 break;
7340 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
7341 ds = "Integrated Raid: Volume Status Changed";
7342 break;
7343 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
7344 ds = "Integrated Raid: Volume Physdisk Changed";
7345 break;
7346 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
7347 ds = "Integrated Raid: Physdisk Created";
7348 break;
7349 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
7350 ds = "Integrated Raid: Physdisk Deleted";
7351 break;
7352 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
7353 ds = "Integrated Raid: Physdisk Settings Changed";
7354 break;
7355 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
7356 ds = "Integrated Raid: Physdisk Status Changed";
7357 break;
7358 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
7359 ds = "Integrated Raid: Domain Validation Needed";
7360 break;
7361 case MPI_EVENT_RAID_RC_SMART_DATA :
7362 ds = "Integrated Raid; Smart Data";
7363 break;
7364 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
7365 ds = "Integrated Raid: Replace Action Started";
7366 break;
7367 default:
7368 ds = "Integrated Raid";
7369 break;
7370 }
7371 break;
7372 }
7373 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
7374 ds = "SCSI Device Status Change";
7375 break;
7376 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
7377 {
7378 u8 id = (u8)(evData0);
7379 u8 channel = (u8)(evData0 >> 8);
7380 u8 ReasonCode = (u8)(evData0 >> 16);
7381 switch (ReasonCode) {
7382 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
7383 snprintf(evStr, EVENT_DESCR_STR_SZ,
7384 "SAS Device Status Change: Added: "
7385 "id=%d channel=%d", id, channel);
7386 break;
7387 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
7388 snprintf(evStr, EVENT_DESCR_STR_SZ,
7389 "SAS Device Status Change: Deleted: "
7390 "id=%d channel=%d", id, channel);
7391 break;
7392 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7393 snprintf(evStr, EVENT_DESCR_STR_SZ,
7394 "SAS Device Status Change: SMART Data: "
7395 "id=%d channel=%d", id, channel);
7396 break;
7397 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
7398 snprintf(evStr, EVENT_DESCR_STR_SZ,
7399 "SAS Device Status Change: No Persistency: "
7400 "id=%d channel=%d", id, channel);
7401 break;
7402 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7403 snprintf(evStr, EVENT_DESCR_STR_SZ,
7404 "SAS Device Status Change: Unsupported Device "
7405 "Discovered : id=%d channel=%d", id, channel);
7406 break;
7407 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7408 snprintf(evStr, EVENT_DESCR_STR_SZ,
7409 "SAS Device Status Change: Internal Device "
7410 "Reset : id=%d channel=%d", id, channel);
7411 break;
7412 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7413 snprintf(evStr, EVENT_DESCR_STR_SZ,
7414 "SAS Device Status Change: Internal Task "
7415 "Abort : id=%d channel=%d", id, channel);
7416 break;
7417 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7418 snprintf(evStr, EVENT_DESCR_STR_SZ,
7419 "SAS Device Status Change: Internal Abort "
7420 "Task Set : id=%d channel=%d", id, channel);
7421 break;
7422 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7423 snprintf(evStr, EVENT_DESCR_STR_SZ,
7424 "SAS Device Status Change: Internal Clear "
7425 "Task Set : id=%d channel=%d", id, channel);
7426 break;
7427 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7428 snprintf(evStr, EVENT_DESCR_STR_SZ,
7429 "SAS Device Status Change: Internal Query "
7430 "Task : id=%d channel=%d", id, channel);
7431 break;
7432 default:
7433 snprintf(evStr, EVENT_DESCR_STR_SZ,
7434 "SAS Device Status Change: Unknown: "
7435 "id=%d channel=%d", id, channel);
7436 break;
7437 }
7438 break;
7439 }
7440 case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
7441 ds = "Bus Timer Expired";
7442 break;
7443 case MPI_EVENT_QUEUE_FULL:
7444 {
7445 u16 curr_depth = (u16)(evData0 >> 16);
7446 u8 channel = (u8)(evData0 >> 8);
7447 u8 id = (u8)(evData0);
7448
7449 snprintf(evStr, EVENT_DESCR_STR_SZ,
7450 "Queue Full: channel=%d id=%d depth=%d",
7451 channel, id, curr_depth);
7452 break;
7453 }
7454 case MPI_EVENT_SAS_SES:
7455 ds = "SAS SES Event";
7456 break;
7457 case MPI_EVENT_PERSISTENT_TABLE_FULL:
7458 ds = "Persistent Table Full";
7459 break;
7460 case MPI_EVENT_SAS_PHY_LINK_STATUS:
7461 {
7462 u8 LinkRates = (u8)(evData0 >> 8);
7463 u8 PhyNumber = (u8)(evData0);
7464 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
7465 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
7466 switch (LinkRates) {
7467 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
7468 snprintf(evStr, EVENT_DESCR_STR_SZ,
7469 "SAS PHY Link Status: Phy=%d:"
7470 " Rate Unknown",PhyNumber);
7471 break;
7472 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
7473 snprintf(evStr, EVENT_DESCR_STR_SZ,
7474 "SAS PHY Link Status: Phy=%d:"
7475 " Phy Disabled",PhyNumber);
7476 break;
7477 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
7478 snprintf(evStr, EVENT_DESCR_STR_SZ,
7479 "SAS PHY Link Status: Phy=%d:"
7480 " Failed Speed Nego",PhyNumber);
7481 break;
7482 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
7483 snprintf(evStr, EVENT_DESCR_STR_SZ,
7484 "SAS PHY Link Status: Phy=%d:"
7485 " Sata OOB Completed",PhyNumber);
7486 break;
7487 case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
7488 snprintf(evStr, EVENT_DESCR_STR_SZ,
7489 "SAS PHY Link Status: Phy=%d:"
7490 " Rate 1.5 Gbps",PhyNumber);
7491 break;
7492 case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
7493 snprintf(evStr, EVENT_DESCR_STR_SZ,
7494 "SAS PHY Link Status: Phy=%d:"
7495 " Rate 3.0 Gbps", PhyNumber);
7496 break;
7497 case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
7498 snprintf(evStr, EVENT_DESCR_STR_SZ,
7499 "SAS PHY Link Status: Phy=%d:"
7500 " Rate 6.0 Gbps", PhyNumber);
7501 break;
7502 default:
7503 snprintf(evStr, EVENT_DESCR_STR_SZ,
7504 "SAS PHY Link Status: Phy=%d", PhyNumber);
7505 break;
7506 }
7507 break;
7508 }
7509 case MPI_EVENT_SAS_DISCOVERY_ERROR:
7510 ds = "SAS Discovery Error";
7511 break;
7512 case MPI_EVENT_IR_RESYNC_UPDATE:
7513 {
7514 u8 resync_complete = (u8)(evData0 >> 16);
7515 snprintf(evStr, EVENT_DESCR_STR_SZ,
7516 "IR Resync Update: Complete = %d:",resync_complete);
7517 break;
7518 }
7519 case MPI_EVENT_IR2:
7520 {
7521 u8 id = (u8)(evData0);
7522 u8 channel = (u8)(evData0 >> 8);
7523 u8 phys_num = (u8)(evData0 >> 24);
7524 u8 ReasonCode = (u8)(evData0 >> 16);
7525
7526 switch (ReasonCode) {
7527 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
7528 snprintf(evStr, EVENT_DESCR_STR_SZ,
7529 "IR2: LD State Changed: "
7530 "id=%d channel=%d phys_num=%d",
7531 id, channel, phys_num);
7532 break;
7533 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
7534 snprintf(evStr, EVENT_DESCR_STR_SZ,
7535 "IR2: PD State Changed "
7536 "id=%d channel=%d phys_num=%d",
7537 id, channel, phys_num);
7538 break;
7539 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
7540 snprintf(evStr, EVENT_DESCR_STR_SZ,
7541 "IR2: Bad Block Table Full: "
7542 "id=%d channel=%d phys_num=%d",
7543 id, channel, phys_num);
7544 break;
7545 case MPI_EVENT_IR2_RC_PD_INSERTED:
7546 snprintf(evStr, EVENT_DESCR_STR_SZ,
7547 "IR2: PD Inserted: "
7548 "id=%d channel=%d phys_num=%d",
7549 id, channel, phys_num);
7550 break;
7551 case MPI_EVENT_IR2_RC_PD_REMOVED:
7552 snprintf(evStr, EVENT_DESCR_STR_SZ,
7553 "IR2: PD Removed: "
7554 "id=%d channel=%d phys_num=%d",
7555 id, channel, phys_num);
7556 break;
7557 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
7558 snprintf(evStr, EVENT_DESCR_STR_SZ,
7559 "IR2: Foreign CFG Detected: "
7560 "id=%d channel=%d phys_num=%d",
7561 id, channel, phys_num);
7562 break;
7563 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
7564 snprintf(evStr, EVENT_DESCR_STR_SZ,
7565 "IR2: Rebuild Medium Error: "
7566 "id=%d channel=%d phys_num=%d",
7567 id, channel, phys_num);
7568 break;
7569 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
7570 snprintf(evStr, EVENT_DESCR_STR_SZ,
7571 "IR2: Dual Port Added: "
7572 "id=%d channel=%d phys_num=%d",
7573 id, channel, phys_num);
7574 break;
7575 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
7576 snprintf(evStr, EVENT_DESCR_STR_SZ,
7577 "IR2: Dual Port Removed: "
7578 "id=%d channel=%d phys_num=%d",
7579 id, channel, phys_num);
7580 break;
7581 default:
7582 ds = "IR2";
7583 break;
7584 }
7585 break;
7586 }
7587 case MPI_EVENT_SAS_DISCOVERY:
7588 {
7589 if (evData0)
7590 ds = "SAS Discovery: Start";
7591 else
7592 ds = "SAS Discovery: Stop";
7593 break;
7594 }
7595 case MPI_EVENT_LOG_ENTRY_ADDED:
7596 ds = "SAS Log Entry Added";
7597 break;
7598
7599 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
7600 {
7601 u8 phy_num = (u8)(evData0);
7602 u8 port_num = (u8)(evData0 >> 8);
7603 u8 port_width = (u8)(evData0 >> 16);
7604 u8 primative = (u8)(evData0 >> 24);
7605 snprintf(evStr, EVENT_DESCR_STR_SZ,
7606 "SAS Broadcase Primative: phy=%d port=%d "
7607 "width=%d primative=0x%02x",
7608 phy_num, port_num, port_width, primative);
7609 break;
7610 }
7611
7612 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
7613 {
7614 u8 reason = (u8)(evData0);
7615
7616 switch (reason) {
7617 case MPI_EVENT_SAS_INIT_RC_ADDED:
7618 ds = "SAS Initiator Status Change: Added";
7619 break;
7620 case MPI_EVENT_SAS_INIT_RC_REMOVED:
7621 ds = "SAS Initiator Status Change: Deleted";
7622 break;
7623 default:
7624 ds = "SAS Initiator Status Change";
7625 break;
7626 }
7627 break;
7628 }
7629
7630 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
7631 {
7632 u8 max_init = (u8)(evData0);
7633 u8 current_init = (u8)(evData0 >> 8);
7634
7635 snprintf(evStr, EVENT_DESCR_STR_SZ,
7636 "SAS Initiator Device Table Overflow: max initiators=%02d "
7637 "current initators=%02d",
7638 max_init, current_init);
7639 break;
7640 }
7641 case MPI_EVENT_SAS_SMP_ERROR:
7642 {
7643 u8 status = (u8)(evData0);
7644 u8 port_num = (u8)(evData0 >> 8);
7645 u8 result = (u8)(evData0 >> 16);
7646
7647 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
7648 snprintf(evStr, EVENT_DESCR_STR_SZ,
7649 "SAS SMP Error: port=%d result=0x%02x",
7650 port_num, result);
7651 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
7652 snprintf(evStr, EVENT_DESCR_STR_SZ,
7653 "SAS SMP Error: port=%d : CRC Error",
7654 port_num);
7655 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
7656 snprintf(evStr, EVENT_DESCR_STR_SZ,
7657 "SAS SMP Error: port=%d : Timeout",
7658 port_num);
7659 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
7660 snprintf(evStr, EVENT_DESCR_STR_SZ,
7661 "SAS SMP Error: port=%d : No Destination",
7662 port_num);
7663 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
7664 snprintf(evStr, EVENT_DESCR_STR_SZ,
7665 "SAS SMP Error: port=%d : Bad Destination",
7666 port_num);
7667 else
7668 snprintf(evStr, EVENT_DESCR_STR_SZ,
7669 "SAS SMP Error: port=%d : status=0x%02x",
7670 port_num, status);
7671 break;
7672 }
7673
7674 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
7675 {
7676 u8 reason = (u8)(evData0);
7677
7678 switch (reason) {
7679 case MPI_EVENT_SAS_EXP_RC_ADDED:
7680 ds = "Expander Status Change: Added";
7681 break;
7682 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
7683 ds = "Expander Status Change: Deleted";
7684 break;
7685 default:
7686 ds = "Expander Status Change";
7687 break;
7688 }
7689 break;
7690 }
7691
7692
7693
7694
7695 default:
7696 ds = "Unknown";
7697 break;
7698 }
7699 if (ds)
7700 strncpy(evStr, ds, EVENT_DESCR_STR_SZ);
7701
7702
7703 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7704 "MPT event:(%02Xh) : %s\n",
7705 ioc->name, event, evStr));
7706
7707 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
7708 ": Event data:\n"));
7709 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
7710 devtverboseprintk(ioc, printk(" %08x",
7711 le32_to_cpu(pEventReply->Data[ii])));
7712 devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
7713}
7714#endif
7715
7716
7717
7718
7719
7720
7721
7722
7723
7724
7725
7726static int
7727ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
7728{
7729 u16 evDataLen;
7730 u32 evData0 = 0;
7731 int ii;
7732 u8 cb_idx;
7733 int r = 0;
7734 int handlers = 0;
7735 u8 event;
7736
7737
7738
7739
7740 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7741 evDataLen = le16_to_cpu(pEventReply->EventDataLength);
7742 if (evDataLen) {
7743 evData0 = le32_to_cpu(pEventReply->Data[0]);
7744 }
7745
7746#ifdef CONFIG_FUSION_LOGGING
7747 if (evDataLen)
7748 mpt_display_event_info(ioc, pEventReply);
7749#endif
7750
7751
7752
7753
7754 switch(event) {
7755 case MPI_EVENT_EVENT_CHANGE:
7756 if (evDataLen) {
7757 u8 evState = evData0 & 0xFF;
7758
7759
7760
7761
7762 if (ioc->facts.Function) {
7763 ioc->facts.EventState = evState;
7764 }
7765 }
7766 break;
7767 case MPI_EVENT_INTEGRATED_RAID:
7768 mptbase_raid_process_event_data(ioc,
7769 (MpiEventDataRaid_t *)pEventReply->Data);
7770 break;
7771 default:
7772 break;
7773 }
7774
7775
7776
7777
7778
7779 if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
7780 int idx;
7781
7782 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
7783
7784 ioc->events[idx].event = event;
7785 ioc->events[idx].eventContext = ioc->eventContext;
7786
7787 for (ii = 0; ii < 2; ii++) {
7788 if (ii < evDataLen)
7789 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
7790 else
7791 ioc->events[idx].data[ii] = 0;
7792 }
7793
7794 ioc->eventContext++;
7795 }
7796
7797
7798
7799
7800
7801 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7802 if (MptEvHandlers[cb_idx]) {
7803 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7804 "Routing Event to event handler #%d\n",
7805 ioc->name, cb_idx));
7806 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
7807 handlers++;
7808 }
7809 }
7810
7811
7812
7813
7814
7815 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
7816 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7817 "EventAck required\n",ioc->name));
7818 if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
7819 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
7820 ioc->name, ii));
7821 }
7822 }
7823
7824 *evHandlers = handlers;
7825 return r;
7826}
7827
7828
7829
7830
7831
7832
7833
7834
7835
7836static void
7837mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
7838{
7839 char *desc = "unknown";
7840
7841 switch (log_info & 0xFF000000) {
7842 case MPI_IOCLOGINFO_FC_INIT_BASE:
7843 desc = "FCP Initiator";
7844 break;
7845 case MPI_IOCLOGINFO_FC_TARGET_BASE:
7846 desc = "FCP Target";
7847 break;
7848 case MPI_IOCLOGINFO_FC_LAN_BASE:
7849 desc = "LAN";
7850 break;
7851 case MPI_IOCLOGINFO_FC_MSG_BASE:
7852 desc = "MPI Message Layer";
7853 break;
7854 case MPI_IOCLOGINFO_FC_LINK_BASE:
7855 desc = "FC Link";
7856 break;
7857 case MPI_IOCLOGINFO_FC_CTX_BASE:
7858 desc = "Context Manager";
7859 break;
7860 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
7861 desc = "Invalid Field Offset";
7862 break;
7863 case MPI_IOCLOGINFO_FC_STATE_CHANGE:
7864 desc = "State Change Info";
7865 break;
7866 }
7867
7868 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
7869 ioc->name, log_info, desc, (log_info & 0xFFFFFF));
7870}
7871
7872
7873
7874
7875
7876
7877
7878
7879
7880static void
7881mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
7882{
7883 u32 info = log_info & 0x00FF0000;
7884 char *desc = "unknown";
7885
7886 switch (info) {
7887 case 0x00010000:
7888 desc = "bug! MID not found";
7889 break;
7890
7891 case 0x00020000:
7892 desc = "Parity Error";
7893 break;
7894
7895 case 0x00030000:
7896 desc = "ASYNC Outbound Overrun";
7897 break;
7898
7899 case 0x00040000:
7900 desc = "SYNC Offset Error";
7901 break;
7902
7903 case 0x00050000:
7904 desc = "BM Change";
7905 break;
7906
7907 case 0x00060000:
7908 desc = "Msg In Overflow";
7909 break;
7910
7911 case 0x00070000:
7912 desc = "DMA Error";
7913 break;
7914
7915 case 0x00080000:
7916 desc = "Outbound DMA Overrun";
7917 break;
7918
7919 case 0x00090000:
7920 desc = "Task Management";
7921 break;
7922
7923 case 0x000A0000:
7924 desc = "Device Problem";
7925 break;
7926
7927 case 0x000B0000:
7928 desc = "Invalid Phase Change";
7929 break;
7930
7931 case 0x000C0000:
7932 desc = "Untagged Table Size";
7933 break;
7934
7935 }
7936
7937 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
7938}
7939
7940
7941 static char *originator_str[] = {
7942 "IOP",
7943 "PL",
7944 "IR"
7945 };
7946 static char *iop_code_str[] = {
7947 NULL,
7948 "Invalid SAS Address",
7949 NULL,
7950 "Invalid Page",
7951 "Diag Message Error",
7952 "Task Terminated",
7953 "Enclosure Management",
7954 "Target Mode"
7955 };
7956 static char *pl_code_str[] = {
7957 NULL,
7958 "Open Failure",
7959 "Invalid Scatter Gather List",
7960 "Wrong Relative Offset or Frame Length",
7961 "Frame Transfer Error",
7962 "Transmit Frame Connected Low",
7963 "SATA Non-NCQ RW Error Bit Set",
7964 "SATA Read Log Receive Data Error",
7965 "SATA NCQ Fail All Commands After Error",
7966 "SATA Error in Receive Set Device Bit FIS",
7967 "Receive Frame Invalid Message",
7968 "Receive Context Message Valid Error",
7969 "Receive Frame Current Frame Error",
7970 "SATA Link Down",
7971 "Discovery SATA Init W IOS",
7972 "Config Invalid Page",
7973 "Discovery SATA Init Timeout",
7974 "Reset",
7975 "Abort",
7976 "IO Not Yet Executed",
7977 "IO Executed",
7978 "Persistent Reservation Out Not Affiliation "
7979 "Owner",
7980 "Open Transmit DMA Abort",
7981 "IO Device Missing Delay Retry",
7982 "IO Cancelled Due to Receive Error",
7983 NULL,
7984 NULL,
7985 NULL,
7986 NULL,
7987 NULL,
7988 NULL,
7989 NULL,
7990 "Enclosure Management"
7991 };
7992 static char *ir_code_str[] = {
7993 "Raid Action Error",
7994 NULL,
7995 NULL,
7996 NULL,
7997 NULL,
7998 NULL,
7999 NULL,
8000 NULL,
8001 NULL
8002 };
8003 static char *raid_sub_code_str[] = {
8004 NULL,
8005 "Volume Creation Failed: Data Passed too "
8006 "Large",
8007 "Volume Creation Failed: Duplicate Volumes "
8008 "Attempted",
8009 "Volume Creation Failed: Max Number "
8010 "Supported Volumes Exceeded",
8011 "Volume Creation Failed: DMA Error",
8012 "Volume Creation Failed: Invalid Volume Type",
8013 "Volume Creation Failed: Error Reading "
8014 "MFG Page 4",
8015 "Volume Creation Failed: Creating Internal "
8016 "Structures",
8017 NULL,
8018 NULL,
8019 NULL,
8020 NULL,
8021 NULL,
8022 NULL,
8023 NULL,
8024 NULL,
8025 "Activation failed: Already Active Volume",
8026 "Activation failed: Unsupported Volume Type",
8027 "Activation failed: Too Many Active Volumes",
8028 "Activation failed: Volume ID in Use",
8029 "Activation failed: Reported Failure",
8030 "Activation failed: Importing a Volume",
8031 NULL,
8032 NULL,
8033 NULL,
8034 NULL,
8035 NULL,
8036 NULL,
8037 NULL,
8038 NULL,
8039 NULL,
8040 NULL,
8041 "Phys Disk failed: Too Many Phys Disks",
8042 "Phys Disk failed: Data Passed too Large",
8043 "Phys Disk failed: DMA Error",
8044 "Phys Disk failed: Invalid <channel:id>",
8045 "Phys Disk failed: Creating Phys Disk Config "
8046 "Page",
8047 NULL,
8048 NULL,
8049 NULL,
8050 NULL,
8051 NULL,
8052 NULL,
8053 NULL,
8054 NULL,
8055 NULL,
8056 NULL,
8057 NULL,
8058 "Compatibility Error: IR Disabled",
8059 "Compatibility Error: Inquiry Command Failed",
8060 "Compatibility Error: Device not Direct Access "
8061 "Device ",
8062 "Compatibility Error: Removable Device Found",
8063 "Compatibility Error: Device SCSI Version not "
8064 "2 or Higher",
8065 "Compatibility Error: SATA Device, 48 BIT LBA "
8066 "not Supported",
8067 "Compatibility Error: Device doesn't have "
8068 "512 Byte Block Sizes",
8069 "Compatibility Error: Volume Type Check Failed",
8070 "Compatibility Error: Volume Type is "
8071 "Unsupported by FW",
8072 "Compatibility Error: Disk Drive too Small for "
8073 "use in Volume",
8074 "Compatibility Error: Phys Disk for Create "
8075 "Volume not Found",
8076 "Compatibility Error: Too Many or too Few "
8077 "Disks for Volume Type",
8078 "Compatibility Error: Disk stripe Sizes "
8079 "Must be 64KB",
8080 "Compatibility Error: IME Size Limited to < 2TB",
8081 };
8082
8083
8084
8085
8086
8087
8088
8089
8090
8091
8092static void
8093mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
8094{
8095union loginfo_type {
8096 u32 loginfo;
8097 struct {
8098 u32 subcode:16;
8099 u32 code:8;
8100 u32 originator:4;
8101 u32 bus_type:4;
8102 }dw;
8103};
8104 union loginfo_type sas_loginfo;
8105 char *originator_desc = NULL;
8106 char *code_desc = NULL;
8107 char *sub_code_desc = NULL;
8108
8109 sas_loginfo.loginfo = log_info;
8110 if ((sas_loginfo.dw.bus_type != 3 ) &&
8111 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
8112 return;
8113
8114 originator_desc = originator_str[sas_loginfo.dw.originator];
8115
8116 switch (sas_loginfo.dw.originator) {
8117
8118 case 0:
8119 if (sas_loginfo.dw.code <
8120 ARRAY_SIZE(iop_code_str))
8121 code_desc = iop_code_str[sas_loginfo.dw.code];
8122 break;
8123 case 1:
8124 if (sas_loginfo.dw.code <
8125 ARRAY_SIZE(pl_code_str))
8126 code_desc = pl_code_str[sas_loginfo.dw.code];
8127 break;
8128 case 2:
8129 if (sas_loginfo.dw.code >=
8130 ARRAY_SIZE(ir_code_str))
8131 break;
8132 code_desc = ir_code_str[sas_loginfo.dw.code];
8133 if (sas_loginfo.dw.subcode >=
8134 ARRAY_SIZE(raid_sub_code_str))
8135 break;
8136 if (sas_loginfo.dw.code == 0)
8137 sub_code_desc =
8138 raid_sub_code_str[sas_loginfo.dw.subcode];
8139 break;
8140 default:
8141 return;
8142 }
8143
8144 if (sub_code_desc != NULL)
8145 printk(MYIOC_s_INFO_FMT
8146 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8147 " SubCode={%s} cb_idx %s\n",
8148 ioc->name, log_info, originator_desc, code_desc,
8149 sub_code_desc, MptCallbacksName[cb_idx]);
8150 else if (code_desc != NULL)
8151 printk(MYIOC_s_INFO_FMT
8152 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8153 " SubCode(0x%04x) cb_idx %s\n",
8154 ioc->name, log_info, originator_desc, code_desc,
8155 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
8156 else
8157 printk(MYIOC_s_INFO_FMT
8158 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
8159 " SubCode(0x%04x) cb_idx %s\n",
8160 ioc->name, log_info, originator_desc,
8161 sas_loginfo.dw.code, sas_loginfo.dw.subcode,
8162 MptCallbacksName[cb_idx]);
8163}
8164
8165
8166
8167
8168
8169
8170
8171
8172
8173
8174static void
8175mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8176{
8177 Config_t *pReq = (Config_t *)mf;
8178 char extend_desc[EVENT_DESCR_STR_SZ];
8179 char *desc = NULL;
8180 u32 form;
8181 u8 page_type;
8182
8183 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
8184 page_type = pReq->ExtPageType;
8185 else
8186 page_type = pReq->Header.PageType;
8187
8188
8189
8190
8191 form = le32_to_cpu(pReq->PageAddress);
8192 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
8193 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
8194 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
8195 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
8196 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
8197 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
8198 return;
8199 }
8200 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
8201 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
8202 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
8203 return;
8204 }
8205
8206 snprintf(extend_desc, EVENT_DESCR_STR_SZ,
8207 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
8208 page_type, pReq->Header.PageNumber, pReq->Action, form);
8209
8210 switch (ioc_status) {
8211
8212 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION:
8213 desc = "Config Page Invalid Action";
8214 break;
8215
8216 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE:
8217 desc = "Config Page Invalid Type";
8218 break;
8219
8220 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE:
8221 desc = "Config Page Invalid Page";
8222 break;
8223
8224 case MPI_IOCSTATUS_CONFIG_INVALID_DATA:
8225 desc = "Config Page Invalid Data";
8226 break;
8227
8228 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS:
8229 desc = "Config Page No Defaults";
8230 break;
8231
8232 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT:
8233 desc = "Config Page Can't Commit";
8234 break;
8235 }
8236
8237 if (!desc)
8238 return;
8239
8240 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
8241 ioc->name, ioc_status, desc, extend_desc));
8242}
8243
8244
8245
8246
8247
8248
8249
8250
8251
8252static void
8253mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8254{
8255 u32 status = ioc_status & MPI_IOCSTATUS_MASK;
8256 char *desc = NULL;
8257
8258 switch (status) {
8259
8260
8261
8262
8263
8264 case MPI_IOCSTATUS_INVALID_FUNCTION:
8265 desc = "Invalid Function";
8266 break;
8267
8268 case MPI_IOCSTATUS_BUSY:
8269 desc = "Busy";
8270 break;
8271
8272 case MPI_IOCSTATUS_INVALID_SGL:
8273 desc = "Invalid SGL";
8274 break;
8275
8276 case MPI_IOCSTATUS_INTERNAL_ERROR:
8277 desc = "Internal Error";
8278 break;
8279
8280 case MPI_IOCSTATUS_RESERVED:
8281 desc = "Reserved";
8282 break;
8283
8284 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES:
8285 desc = "Insufficient Resources";
8286 break;
8287
8288 case MPI_IOCSTATUS_INVALID_FIELD:
8289 desc = "Invalid Field";
8290 break;
8291
8292 case MPI_IOCSTATUS_INVALID_STATE:
8293 desc = "Invalid State";
8294 break;
8295
8296
8297
8298
8299
8300 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION:
8301 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE:
8302 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE:
8303 case MPI_IOCSTATUS_CONFIG_INVALID_DATA:
8304 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS:
8305 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT:
8306 mpt_iocstatus_info_config(ioc, status, mf);
8307 break;
8308
8309
8310
8311
8312
8313
8314
8315
8316 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR:
8317 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN:
8318 case MPI_IOCSTATUS_SCSI_INVALID_BUS:
8319 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID:
8320 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
8321 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN:
8322 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR:
8323 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR:
8324 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED:
8325 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
8326 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
8327 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED:
8328 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED:
8329 break;
8330
8331
8332
8333
8334
8335 case MPI_IOCSTATUS_TARGET_PRIORITY_IO:
8336 desc = "Target: Priority IO";
8337 break;
8338
8339 case MPI_IOCSTATUS_TARGET_INVALID_PORT:
8340 desc = "Target: Invalid Port";
8341 break;
8342
8343 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX:
8344 desc = "Target Invalid IO Index:";
8345 break;
8346
8347 case MPI_IOCSTATUS_TARGET_ABORTED:
8348 desc = "Target: Aborted";
8349 break;
8350
8351 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
8352 desc = "Target: No Conn Retryable";
8353 break;
8354
8355 case MPI_IOCSTATUS_TARGET_NO_CONNECTION:
8356 desc = "Target: No Connection";
8357 break;
8358
8359 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
8360 desc = "Target: Transfer Count Mismatch";
8361 break;
8362
8363 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT:
8364 desc = "Target: STS Data not Sent";
8365 break;
8366
8367 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
8368 desc = "Target: Data Offset Error";
8369 break;
8370
8371 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
8372 desc = "Target: Too Much Write Data";
8373 break;
8374
8375 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT:
8376 desc = "Target: IU Too Short";
8377 break;
8378
8379 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
8380 desc = "Target: ACK NAK Timeout";
8381 break;
8382
8383 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED:
8384 desc = "Target: Nak Received";
8385 break;
8386
8387
8388
8389
8390
8391 case MPI_IOCSTATUS_FC_ABORTED:
8392 desc = "FC: Aborted";
8393 break;
8394
8395 case MPI_IOCSTATUS_FC_RX_ID_INVALID:
8396 desc = "FC: RX ID Invalid";
8397 break;
8398
8399 case MPI_IOCSTATUS_FC_DID_INVALID:
8400 desc = "FC: DID Invalid";
8401 break;
8402
8403 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT:
8404 desc = "FC: Node Logged Out";
8405 break;
8406
8407 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED:
8408 desc = "FC: Exchange Canceled";
8409 break;
8410
8411
8412
8413
8414
8415 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND:
8416 desc = "LAN: Device not Found";
8417 break;
8418
8419 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE:
8420 desc = "LAN: Device Failure";
8421 break;
8422
8423 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR:
8424 desc = "LAN: Transmit Error";
8425 break;
8426
8427 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED:
8428 desc = "LAN: Transmit Aborted";
8429 break;
8430
8431 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR:
8432 desc = "LAN: Receive Error";
8433 break;
8434
8435 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED:
8436 desc = "LAN: Receive Aborted";
8437 break;
8438
8439 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET:
8440 desc = "LAN: Partial Packet";
8441 break;
8442
8443 case MPI_IOCSTATUS_LAN_CANCELED:
8444 desc = "LAN: Canceled";
8445 break;
8446
8447
8448
8449
8450
8451 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
8452 desc = "SAS: SMP Request Failed";
8453 break;
8454
8455 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
8456 desc = "SAS: SMP Data Overrun";
8457 break;
8458
8459 default:
8460 desc = "Others";
8461 break;
8462 }
8463
8464 if (!desc)
8465 return;
8466
8467 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
8468 ioc->name, status, desc));
8469}
8470
8471
8472EXPORT_SYMBOL(mpt_attach);
8473EXPORT_SYMBOL(mpt_detach);
8474#ifdef CONFIG_PM
8475EXPORT_SYMBOL(mpt_resume);
8476EXPORT_SYMBOL(mpt_suspend);
8477#endif
8478EXPORT_SYMBOL(ioc_list);
8479EXPORT_SYMBOL(mpt_register);
8480EXPORT_SYMBOL(mpt_deregister);
8481EXPORT_SYMBOL(mpt_event_register);
8482EXPORT_SYMBOL(mpt_event_deregister);
8483EXPORT_SYMBOL(mpt_reset_register);
8484EXPORT_SYMBOL(mpt_reset_deregister);
8485EXPORT_SYMBOL(mpt_device_driver_register);
8486EXPORT_SYMBOL(mpt_device_driver_deregister);
8487EXPORT_SYMBOL(mpt_get_msg_frame);
8488EXPORT_SYMBOL(mpt_put_msg_frame);
8489EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
8490EXPORT_SYMBOL(mpt_free_msg_frame);
8491EXPORT_SYMBOL(mpt_send_handshake_request);
8492EXPORT_SYMBOL(mpt_verify_adapter);
8493EXPORT_SYMBOL(mpt_GetIocState);
8494EXPORT_SYMBOL(mpt_print_ioc_summary);
8495EXPORT_SYMBOL(mpt_HardResetHandler);
8496EXPORT_SYMBOL(mpt_config);
8497EXPORT_SYMBOL(mpt_findImVolumes);
8498EXPORT_SYMBOL(mpt_alloc_fw_memory);
8499EXPORT_SYMBOL(mpt_free_fw_memory);
8500EXPORT_SYMBOL(mptbase_sas_persist_operation);
8501EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
8502
8503
8504
8505
8506
8507
8508
8509static int __init
8510fusion_init(void)
8511{
8512 u8 cb_idx;
8513
8514 show_mptmod_ver(my_NAME, my_VERSION);
8515 printk(KERN_INFO COPYRIGHT "\n");
8516
8517 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
8518 MptCallbacks[cb_idx] = NULL;
8519 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
8520 MptEvHandlers[cb_idx] = NULL;
8521 MptResetHandlers[cb_idx] = NULL;
8522 }
8523
8524
8525
8526
8527 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
8528 "mptbase_reply");
8529
8530
8531
8532 mpt_reset_register(mpt_base_index, mpt_ioc_reset);
8533
8534#ifdef CONFIG_PROC_FS
8535 (void) procmpt_create();
8536#endif
8537 return 0;
8538}
8539
8540
8541
8542
8543
8544
8545
8546
8547static void __exit
8548fusion_exit(void)
8549{
8550
8551 mpt_reset_deregister(mpt_base_index);
8552
8553#ifdef CONFIG_PROC_FS
8554 procmpt_destroy();
8555#endif
8556}
8557
8558module_init(fusion_init);
8559module_exit(fusion_exit);
8560