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13#ifndef __SDHCI_HW_H
14#define __SDHCI_HW_H
15
16#include <linux/scatterlist.h>
17#include <linux/compiler.h>
18#include <linux/types.h>
19#include <linux/io.h>
20#include <linux/leds.h>
21#include <linux/interrupt.h>
22
23#include <linux/mmc/host.h>
24
25
26
27
28
29#define SDHCI_DMA_ADDRESS 0x00
30#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
31
32#define SDHCI_BLOCK_SIZE 0x04
33#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
34
35#define SDHCI_BLOCK_COUNT 0x06
36
37#define SDHCI_ARGUMENT 0x08
38
39#define SDHCI_TRANSFER_MODE 0x0C
40#define SDHCI_TRNS_DMA 0x01
41#define SDHCI_TRNS_BLK_CNT_EN 0x02
42#define SDHCI_TRNS_AUTO_CMD12 0x04
43#define SDHCI_TRNS_AUTO_CMD23 0x08
44#define SDHCI_TRNS_READ 0x10
45#define SDHCI_TRNS_MULTI 0x20
46
47#define SDHCI_COMMAND 0x0E
48#define SDHCI_CMD_RESP_MASK 0x03
49#define SDHCI_CMD_CRC 0x08
50#define SDHCI_CMD_INDEX 0x10
51#define SDHCI_CMD_DATA 0x20
52#define SDHCI_CMD_ABORTCMD 0xC0
53
54#define SDHCI_CMD_RESP_NONE 0x00
55#define SDHCI_CMD_RESP_LONG 0x01
56#define SDHCI_CMD_RESP_SHORT 0x02
57#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
58
59#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
60#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
61
62#define SDHCI_RESPONSE 0x10
63
64#define SDHCI_BUFFER 0x20
65
66#define SDHCI_PRESENT_STATE 0x24
67#define SDHCI_CMD_INHIBIT 0x00000001
68#define SDHCI_DATA_INHIBIT 0x00000002
69#define SDHCI_DOING_WRITE 0x00000100
70#define SDHCI_DOING_READ 0x00000200
71#define SDHCI_SPACE_AVAILABLE 0x00000400
72#define SDHCI_DATA_AVAILABLE 0x00000800
73#define SDHCI_CARD_PRESENT 0x00010000
74#define SDHCI_WRITE_PROTECT 0x00080000
75#define SDHCI_DATA_LVL_MASK 0x00F00000
76#define SDHCI_DATA_LVL_SHIFT 20
77#define SDHCI_DATA_0_LVL_MASK 0x00100000
78#define SDHCI_CMD_LVL 0x01000000
79
80#define SDHCI_HOST_CONTROL 0x28
81#define SDHCI_CTRL_LED 0x01
82#define SDHCI_CTRL_4BITBUS 0x02
83#define SDHCI_CTRL_HISPD 0x04
84#define SDHCI_CTRL_DMA_MASK 0x18
85#define SDHCI_CTRL_SDMA 0x00
86#define SDHCI_CTRL_ADMA1 0x08
87#define SDHCI_CTRL_ADMA32 0x10
88#define SDHCI_CTRL_ADMA64 0x18
89#define SDHCI_CTRL_8BITBUS 0x20
90#define SDHCI_CTRL_CDTEST_INS 0x40
91#define SDHCI_CTRL_CDTEST_EN 0x80
92
93#define SDHCI_POWER_CONTROL 0x29
94#define SDHCI_POWER_ON 0x01
95#define SDHCI_POWER_180 0x0A
96#define SDHCI_POWER_300 0x0C
97#define SDHCI_POWER_330 0x0E
98
99#define SDHCI_BLOCK_GAP_CONTROL 0x2A
100
101#define SDHCI_WAKE_UP_CONTROL 0x2B
102#define SDHCI_WAKE_ON_INT 0x01
103#define SDHCI_WAKE_ON_INSERT 0x02
104#define SDHCI_WAKE_ON_REMOVE 0x04
105
106#define SDHCI_CLOCK_CONTROL 0x2C
107#define SDHCI_DIVIDER_SHIFT 8
108#define SDHCI_DIVIDER_HI_SHIFT 6
109#define SDHCI_DIV_MASK 0xFF
110#define SDHCI_DIV_MASK_LEN 8
111#define SDHCI_DIV_HI_MASK 0x300
112#define SDHCI_PROG_CLOCK_MODE 0x0020
113#define SDHCI_CLOCK_CARD_EN 0x0004
114#define SDHCI_CLOCK_INT_STABLE 0x0002
115#define SDHCI_CLOCK_INT_EN 0x0001
116
117#define SDHCI_TIMEOUT_CONTROL 0x2E
118
119#define SDHCI_SOFTWARE_RESET 0x2F
120#define SDHCI_RESET_ALL 0x01
121#define SDHCI_RESET_CMD 0x02
122#define SDHCI_RESET_DATA 0x04
123
124#define SDHCI_INT_STATUS 0x30
125#define SDHCI_INT_ENABLE 0x34
126#define SDHCI_SIGNAL_ENABLE 0x38
127#define SDHCI_INT_RESPONSE 0x00000001
128#define SDHCI_INT_DATA_END 0x00000002
129#define SDHCI_INT_BLK_GAP 0x00000004
130#define SDHCI_INT_DMA_END 0x00000008
131#define SDHCI_INT_SPACE_AVAIL 0x00000010
132#define SDHCI_INT_DATA_AVAIL 0x00000020
133#define SDHCI_INT_CARD_INSERT 0x00000040
134#define SDHCI_INT_CARD_REMOVE 0x00000080
135#define SDHCI_INT_CARD_INT 0x00000100
136#define SDHCI_INT_RETUNE 0x00001000
137#define SDHCI_INT_CQE 0x00004000
138#define SDHCI_INT_ERROR 0x00008000
139#define SDHCI_INT_TIMEOUT 0x00010000
140#define SDHCI_INT_CRC 0x00020000
141#define SDHCI_INT_END_BIT 0x00040000
142#define SDHCI_INT_INDEX 0x00080000
143#define SDHCI_INT_DATA_TIMEOUT 0x00100000
144#define SDHCI_INT_DATA_CRC 0x00200000
145#define SDHCI_INT_DATA_END_BIT 0x00400000
146#define SDHCI_INT_BUS_POWER 0x00800000
147#define SDHCI_INT_ACMD12ERR 0x01000000
148#define SDHCI_INT_ADMA_ERROR 0x02000000
149
150#define SDHCI_INT_NORMAL_MASK 0x00007FFF
151#define SDHCI_INT_ERROR_MASK 0xFFFF8000
152
153#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
154 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
155#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
156 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
157 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
158 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
159 SDHCI_INT_BLK_GAP)
160#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
161
162#define SDHCI_CQE_INT_ERR_MASK ( \
163 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
164 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
165 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
166
167#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
168
169#define SDHCI_ACMD12_ERR 0x3C
170
171#define SDHCI_HOST_CONTROL2 0x3E
172#define SDHCI_CTRL_UHS_MASK 0x0007
173#define SDHCI_CTRL_UHS_SDR12 0x0000
174#define SDHCI_CTRL_UHS_SDR25 0x0001
175#define SDHCI_CTRL_UHS_SDR50 0x0002
176#define SDHCI_CTRL_UHS_SDR104 0x0003
177#define SDHCI_CTRL_UHS_DDR50 0x0004
178#define SDHCI_CTRL_HS400 0x0005
179#define SDHCI_CTRL_VDD_180 0x0008
180#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
181#define SDHCI_CTRL_DRV_TYPE_B 0x0000
182#define SDHCI_CTRL_DRV_TYPE_A 0x0010
183#define SDHCI_CTRL_DRV_TYPE_C 0x0020
184#define SDHCI_CTRL_DRV_TYPE_D 0x0030
185#define SDHCI_CTRL_EXEC_TUNING 0x0040
186#define SDHCI_CTRL_TUNED_CLK 0x0080
187#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
188
189#define SDHCI_CAPABILITIES 0x40
190#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
191#define SDHCI_TIMEOUT_CLK_SHIFT 0
192#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
193#define SDHCI_CLOCK_BASE_MASK 0x00003F00
194#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
195#define SDHCI_CLOCK_BASE_SHIFT 8
196#define SDHCI_MAX_BLOCK_MASK 0x00030000
197#define SDHCI_MAX_BLOCK_SHIFT 16
198#define SDHCI_CAN_DO_8BIT 0x00040000
199#define SDHCI_CAN_DO_ADMA2 0x00080000
200#define SDHCI_CAN_DO_ADMA1 0x00100000
201#define SDHCI_CAN_DO_HISPD 0x00200000
202#define SDHCI_CAN_DO_SDMA 0x00400000
203#define SDHCI_CAN_DO_SUSPEND 0x00800000
204#define SDHCI_CAN_VDD_330 0x01000000
205#define SDHCI_CAN_VDD_300 0x02000000
206#define SDHCI_CAN_VDD_180 0x04000000
207#define SDHCI_CAN_64BIT 0x10000000
208
209#define SDHCI_SUPPORT_SDR50 0x00000001
210#define SDHCI_SUPPORT_SDR104 0x00000002
211#define SDHCI_SUPPORT_DDR50 0x00000004
212#define SDHCI_DRIVER_TYPE_A 0x00000010
213#define SDHCI_DRIVER_TYPE_C 0x00000020
214#define SDHCI_DRIVER_TYPE_D 0x00000040
215#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
216#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
217#define SDHCI_USE_SDR50_TUNING 0x00002000
218#define SDHCI_RETUNING_MODE_MASK 0x0000C000
219#define SDHCI_RETUNING_MODE_SHIFT 14
220#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
221#define SDHCI_CLOCK_MUL_SHIFT 16
222#define SDHCI_SUPPORT_HS400 0x80000000
223
224#define SDHCI_CAPABILITIES_1 0x44
225
226#define SDHCI_MAX_CURRENT 0x48
227#define SDHCI_MAX_CURRENT_LIMIT 0xFF
228#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
229#define SDHCI_MAX_CURRENT_330_SHIFT 0
230#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
231#define SDHCI_MAX_CURRENT_300_SHIFT 8
232#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
233#define SDHCI_MAX_CURRENT_180_SHIFT 16
234#define SDHCI_MAX_CURRENT_MULTIPLIER 4
235
236
237
238#define SDHCI_SET_ACMD12_ERROR 0x50
239#define SDHCI_SET_INT_ERROR 0x52
240
241#define SDHCI_ADMA_ERROR 0x54
242
243
244
245#define SDHCI_ADMA_ADDRESS 0x58
246#define SDHCI_ADMA_ADDRESS_HI 0x5C
247
248
249
250#define SDHCI_PRESET_FOR_SDR12 0x66
251#define SDHCI_PRESET_FOR_SDR25 0x68
252#define SDHCI_PRESET_FOR_SDR50 0x6A
253#define SDHCI_PRESET_FOR_SDR104 0x6C
254#define SDHCI_PRESET_FOR_DDR50 0x6E
255#define SDHCI_PRESET_FOR_HS400 0x74
256#define SDHCI_PRESET_DRV_MASK 0xC000
257#define SDHCI_PRESET_DRV_SHIFT 14
258#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
259#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
260#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
261#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
262
263#define SDHCI_SLOT_INT_STATUS 0xFC
264
265#define SDHCI_HOST_VERSION 0xFE
266#define SDHCI_VENDOR_VER_MASK 0xFF00
267#define SDHCI_VENDOR_VER_SHIFT 8
268#define SDHCI_SPEC_VER_MASK 0x00FF
269#define SDHCI_SPEC_VER_SHIFT 0
270#define SDHCI_SPEC_100 0
271#define SDHCI_SPEC_200 1
272#define SDHCI_SPEC_300 2
273
274
275
276
277
278#define SDHCI_MAX_DIV_SPEC_200 256
279#define SDHCI_MAX_DIV_SPEC_300 2046
280
281
282
283
284#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
285#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
286
287
288#define SDHCI_ADMA2_32_DESC_SZ 8
289
290
291struct sdhci_adma2_32_desc {
292 __le16 cmd;
293 __le16 len;
294 __le32 addr;
295} __packed __aligned(4);
296
297
298#define SDHCI_ADMA2_ALIGN 4
299#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
300
301
302
303
304
305
306#define SDHCI_ADMA2_DESC_ALIGN 8
307
308
309#define SDHCI_ADMA2_64_DESC_SZ 12
310
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313
314
315struct sdhci_adma2_64_desc {
316 __le16 cmd;
317 __le16 len;
318 __le32 addr_lo;
319 __le32 addr_hi;
320} __packed __aligned(4);
321
322#define ADMA2_TRAN_VALID 0x21
323#define ADMA2_NOP_END_VALID 0x3
324#define ADMA2_END 0x2
325
326
327
328
329
330#define SDHCI_MAX_SEGS 128
331
332
333#define SDHCI_MAX_MRQS 2
334
335enum sdhci_cookie {
336 COOKIE_UNMAPPED,
337 COOKIE_PRE_MAPPED,
338 COOKIE_MAPPED,
339};
340
341struct sdhci_host {
342
343 const char *hw_name;
344
345 unsigned int quirks;
346
347
348#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
349
350#define SDHCI_QUIRK_FORCE_DMA (1<<1)
351
352#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
353
354#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
355
356#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
357
358#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
359
360#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
361
362#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
363
364#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
365
366#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
367
368#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
369
370#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
371
372#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
373
374#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
375
376#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
377
378#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
379
380#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
381
382#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
383
384#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
385
386#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
387
388#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
389
390#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
391
392#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
393
394#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
395
396#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
397
398#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
399
400#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
401
402#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
403
404#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
405
406#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
407
408 unsigned int quirks2;
409
410#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
411#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
412
413#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
414#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
415#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
416
417#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
418
419#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
420
421#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
422
423#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
424
425#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
426
427#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
428
429#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
430
431#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
432
433#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
434
435#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
436
437#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
438
439#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
440
441#define SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN (1<<17)
442
443 int irq;
444 void __iomem *ioaddr;
445
446 const struct sdhci_ops *ops;
447
448
449 struct mmc_host *mmc;
450 struct mmc_host_ops mmc_host_ops;
451 u64 dma_mask;
452
453#if IS_ENABLED(CONFIG_LEDS_CLASS)
454 struct led_classdev led;
455 char led_name[32];
456#endif
457
458 spinlock_t lock;
459
460 int flags;
461#define SDHCI_USE_SDMA (1<<0)
462#define SDHCI_USE_ADMA (1<<1)
463#define SDHCI_REQ_USE_DMA (1<<2)
464#define SDHCI_DEVICE_DEAD (1<<3)
465#define SDHCI_SDR50_NEEDS_TUNING (1<<4)
466#define SDHCI_AUTO_CMD12 (1<<6)
467#define SDHCI_AUTO_CMD23 (1<<7)
468#define SDHCI_PV_ENABLED (1<<8)
469#define SDHCI_SDIO_IRQ_ENABLED (1<<9)
470#define SDHCI_USE_64_BIT_DMA (1<<12)
471#define SDHCI_HS400_TUNING (1<<13)
472#define SDHCI_SIGNALING_330 (1<<14)
473#define SDHCI_SIGNALING_180 (1<<15)
474#define SDHCI_SIGNALING_120 (1<<16)
475
476 unsigned int version;
477
478 unsigned int max_clk;
479 unsigned int timeout_clk;
480 unsigned int clk_mul;
481
482 unsigned int clock;
483 u8 pwr;
484
485 bool runtime_suspended;
486 bool bus_on;
487 bool preset_enabled;
488 bool pending_reset;
489
490 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];
491 struct mmc_command *cmd;
492 struct mmc_command *data_cmd;
493 struct mmc_data *data;
494 unsigned int data_early:1;
495
496 struct sg_mapping_iter sg_miter;
497 unsigned int blocks;
498
499 int sg_count;
500
501 void *adma_table;
502 void *align_buffer;
503
504 size_t adma_table_sz;
505 size_t align_buffer_sz;
506
507 dma_addr_t adma_addr;
508 dma_addr_t align_addr;
509
510 unsigned int desc_sz;
511
512 struct tasklet_struct finish_tasklet;
513
514 struct timer_list timer;
515 struct timer_list data_timer;
516
517 u32 caps;
518 u32 caps1;
519 bool read_caps;
520
521 unsigned int ocr_avail_sdio;
522 unsigned int ocr_avail_sd;
523 unsigned int ocr_avail_mmc;
524 u32 ocr_mask;
525
526 unsigned timing;
527
528 u32 thread_isr;
529
530
531 u32 ier;
532
533 bool cqe_on;
534 u32 cqe_ier;
535 u32 cqe_err_ier;
536
537 wait_queue_head_t buf_ready_int;
538 unsigned int tuning_done;
539
540 unsigned int tuning_count;
541 unsigned int tuning_mode;
542#define SDHCI_TUNING_MODE_1 0
543#define SDHCI_TUNING_MODE_2 1
544#define SDHCI_TUNING_MODE_3 2
545
546 int tuning_delay;
547
548
549 u32 sdma_boundary;
550
551 unsigned long private[0] ____cacheline_aligned;
552};
553
554struct sdhci_ops {
555#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
556 u32 (*read_l)(struct sdhci_host *host, int reg);
557 u16 (*read_w)(struct sdhci_host *host, int reg);
558 u8 (*read_b)(struct sdhci_host *host, int reg);
559 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
560 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
561 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
562#endif
563
564 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
565 void (*set_power)(struct sdhci_host *host, unsigned char mode,
566 unsigned short vdd);
567
568 u32 (*irq)(struct sdhci_host *host, u32 intmask);
569
570 int (*enable_dma)(struct sdhci_host *host);
571 unsigned int (*get_max_clock)(struct sdhci_host *host);
572 unsigned int (*get_min_clock)(struct sdhci_host *host);
573
574 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
575 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
576 void (*set_timeout)(struct sdhci_host *host,
577 struct mmc_command *cmd);
578 void (*set_bus_width)(struct sdhci_host *host, int width);
579 void (*platform_send_init_74_clocks)(struct sdhci_host *host,
580 u8 power_mode);
581 unsigned int (*get_ro)(struct sdhci_host *host);
582 void (*reset)(struct sdhci_host *host, u8 mask);
583 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
584 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
585 void (*hw_reset)(struct sdhci_host *host);
586 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
587 void (*card_event)(struct sdhci_host *host);
588 void (*voltage_switch)(struct sdhci_host *host);
589};
590
591#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
592
593static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
594{
595 if (unlikely(host->ops->write_l))
596 host->ops->write_l(host, val, reg);
597 else
598 writel(val, host->ioaddr + reg);
599}
600
601static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
602{
603 if (unlikely(host->ops->write_w))
604 host->ops->write_w(host, val, reg);
605 else
606 writew(val, host->ioaddr + reg);
607}
608
609static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
610{
611 if (unlikely(host->ops->write_b))
612 host->ops->write_b(host, val, reg);
613 else
614 writeb(val, host->ioaddr + reg);
615}
616
617static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
618{
619 if (unlikely(host->ops->read_l))
620 return host->ops->read_l(host, reg);
621 else
622 return readl(host->ioaddr + reg);
623}
624
625static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
626{
627 if (unlikely(host->ops->read_w))
628 return host->ops->read_w(host, reg);
629 else
630 return readw(host->ioaddr + reg);
631}
632
633static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
634{
635 if (unlikely(host->ops->read_b))
636 return host->ops->read_b(host, reg);
637 else
638 return readb(host->ioaddr + reg);
639}
640
641#else
642
643static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
644{
645 writel(val, host->ioaddr + reg);
646}
647
648static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
649{
650 writew(val, host->ioaddr + reg);
651}
652
653static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
654{
655 writeb(val, host->ioaddr + reg);
656}
657
658static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
659{
660 return readl(host->ioaddr + reg);
661}
662
663static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
664{
665 return readw(host->ioaddr + reg);
666}
667
668static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
669{
670 return readb(host->ioaddr + reg);
671}
672
673#endif
674
675struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
676void sdhci_free_host(struct sdhci_host *host);
677
678static inline void *sdhci_priv(struct sdhci_host *host)
679{
680 return host->private;
681}
682
683void sdhci_card_detect(struct sdhci_host *host);
684void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
685 u32 *caps1);
686int sdhci_setup_host(struct sdhci_host *host);
687void sdhci_cleanup_host(struct sdhci_host *host);
688int __sdhci_add_host(struct sdhci_host *host);
689int sdhci_add_host(struct sdhci_host *host);
690void sdhci_remove_host(struct sdhci_host *host, int dead);
691void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
692
693static inline void sdhci_read_caps(struct sdhci_host *host)
694{
695 __sdhci_read_caps(host, NULL, NULL, NULL);
696}
697
698static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
699{
700 return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
701}
702
703u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
704 unsigned int *actual_clock);
705void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
706void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
707void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
708 unsigned short vdd);
709void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
710 unsigned short vdd);
711void sdhci_set_bus_width(struct sdhci_host *host, int width);
712void sdhci_reset(struct sdhci_host *host, u8 mask);
713void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
714int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
715void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
716int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
717 struct mmc_ios *ios);
718void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
719
720#ifdef CONFIG_PM
721int sdhci_suspend_host(struct sdhci_host *host);
722int sdhci_resume_host(struct sdhci_host *host);
723void sdhci_enable_irq_wakeups(struct sdhci_host *host);
724int sdhci_runtime_suspend_host(struct sdhci_host *host);
725int sdhci_runtime_resume_host(struct sdhci_host *host);
726#endif
727
728void sdhci_cqe_enable(struct mmc_host *mmc);
729void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
730bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
731 int *data_error);
732
733void sdhci_dumpregs(struct sdhci_host *host);
734
735#endif
736