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16#ifndef HINIC_HW_DEV_H
17#define HINIC_HW_DEV_H
18
19#include <linux/pci.h>
20#include <linux/types.h>
21#include <linux/bitops.h>
22
23#include "hinic_hw_if.h"
24#include "hinic_hw_eqs.h"
25#include "hinic_hw_mgmt.h"
26#include "hinic_hw_qp.h"
27#include "hinic_hw_io.h"
28
29#define HINIC_MAX_QPS 32
30
31#define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \
32 HINIC_MGMT_MSG_CMD_BASE)
33
34struct hinic_cap {
35 u16 max_qps;
36 u16 num_qps;
37};
38
39enum hinic_port_cmd {
40 HINIC_PORT_CMD_CHANGE_MTU = 2,
41
42 HINIC_PORT_CMD_ADD_VLAN = 3,
43 HINIC_PORT_CMD_DEL_VLAN = 4,
44
45 HINIC_PORT_CMD_SET_MAC = 9,
46 HINIC_PORT_CMD_GET_MAC = 10,
47 HINIC_PORT_CMD_DEL_MAC = 11,
48
49 HINIC_PORT_CMD_SET_RX_MODE = 12,
50
51 HINIC_PORT_CMD_GET_LINK_STATE = 24,
52
53 HINIC_PORT_CMD_SET_PORT_STATE = 41,
54
55 HINIC_PORT_CMD_FWCTXT_INIT = 69,
56
57 HINIC_PORT_CMD_SET_FUNC_STATE = 93,
58
59 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102,
60
61 HINIC_PORT_CMD_GET_CAP = 170,
62};
63
64enum hinic_mgmt_msg_cmd {
65 HINIC_MGMT_MSG_CMD_BASE = 160,
66
67 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160,
68
69 HINIC_MGMT_MSG_CMD_MAX,
70};
71
72enum hinic_cb_state {
73 HINIC_CB_ENABLED = BIT(0),
74 HINIC_CB_RUNNING = BIT(1),
75};
76
77enum hinic_res_state {
78 HINIC_RES_CLEAN = 0,
79 HINIC_RES_ACTIVE = 1,
80};
81
82struct hinic_cmd_fw_ctxt {
83 u8 status;
84 u8 version;
85 u8 rsvd0[6];
86
87 u16 func_idx;
88 u16 rx_buf_sz;
89
90 u32 rsvd1;
91};
92
93struct hinic_cmd_hw_ioctxt {
94 u8 status;
95 u8 version;
96 u8 rsvd0[6];
97
98 u16 func_idx;
99
100 u16 rsvd1;
101
102 u8 set_cmdq_depth;
103 u8 cmdq_depth;
104
105 u8 rsvd2;
106 u8 rsvd3;
107 u8 rsvd4;
108 u8 rsvd5;
109
110 u16 rq_depth;
111 u16 rx_buf_sz_idx;
112 u16 sq_depth;
113};
114
115struct hinic_cmd_io_status {
116 u8 status;
117 u8 version;
118 u8 rsvd0[6];
119
120 u16 func_idx;
121 u8 rsvd1;
122 u8 rsvd2;
123 u32 io_status;
124};
125
126struct hinic_cmd_clear_io_res {
127 u8 status;
128 u8 version;
129 u8 rsvd0[6];
130
131 u16 func_idx;
132 u8 rsvd1;
133 u8 rsvd2;
134};
135
136struct hinic_cmd_set_res_state {
137 u8 status;
138 u8 version;
139 u8 rsvd0[6];
140
141 u16 func_idx;
142 u8 state;
143 u8 rsvd1;
144 u32 rsvd2;
145};
146
147struct hinic_cmd_base_qpn {
148 u8 status;
149 u8 version;
150 u8 rsvd0[6];
151
152 u16 func_idx;
153 u16 qpn;
154};
155
156struct hinic_cmd_hw_ci {
157 u8 status;
158 u8 version;
159 u8 rsvd0[6];
160
161 u16 func_idx;
162
163 u8 dma_attr_off;
164 u8 pending_limit;
165 u8 coalesc_timer;
166
167 u8 msix_en;
168 u16 msix_entry_idx;
169
170 u32 sq_id;
171 u32 rsvd1;
172 u64 ci_addr;
173};
174
175struct hinic_hwdev {
176 struct hinic_hwif *hwif;
177 struct msix_entry *msix_entries;
178
179 struct hinic_aeqs aeqs;
180 struct hinic_func_to_io func_to_io;
181
182 struct hinic_cap nic_cap;
183};
184
185struct hinic_nic_cb {
186 void (*handler)(void *handle, void *buf_in,
187 u16 in_size, void *buf_out,
188 u16 *out_size);
189
190 void *handle;
191 unsigned long cb_state;
192};
193
194struct hinic_pfhwdev {
195 struct hinic_hwdev hwdev;
196
197 struct hinic_pf_to_mgmt pf_to_mgmt;
198
199 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD];
200};
201
202void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
203 enum hinic_mgmt_msg_cmd cmd, void *handle,
204 void (*handler)(void *handle, void *buf_in,
205 u16 in_size, void *buf_out,
206 u16 *out_size));
207
208void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
209 enum hinic_mgmt_msg_cmd cmd);
210
211int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
212 void *buf_in, u16 in_size, void *buf_out,
213 u16 *out_size);
214
215int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
216
217void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
218
219struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);
220
221void hinic_free_hwdev(struct hinic_hwdev *hwdev);
222
223int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
224
225struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
226
227struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
228
229int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
230
231int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
232 u8 pending_limit, u8 coalesc_timer,
233 u8 lli_timer_cfg, u8 lli_credit_limit,
234 u8 resend_timer);
235
236int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
237 u8 pending_limit, u8 coalesc_timer);
238
239#endif
240
