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13#ifndef __STMMAC_PCS_H__
14#define __STMMAC_PCS_H__
15
16#include <linux/slab.h>
17#include <linux/io.h>
18#include "common.h"
19
20
21#define GMAC_AN_CTRL(x) (x)
22#define GMAC_AN_STATUS(x) (x + 0x4)
23#define GMAC_ANE_ADV(x) (x + 0x8)
24#define GMAC_ANE_LPA(x) (x + 0xc)
25#define GMAC_ANE_EXP(x) (x + 0x10)
26#define GMAC_TBI(x) (x + 0x14)
27
28
29#define GMAC_AN_CTRL_RAN BIT(9)
30#define GMAC_AN_CTRL_ANE BIT(12)
31#define GMAC_AN_CTRL_ELE BIT(14)
32#define GMAC_AN_CTRL_ECD BIT(16)
33#define GMAC_AN_CTRL_LR BIT(17)
34#define GMAC_AN_CTRL_SGMRAL BIT(18)
35
36
37#define GMAC_AN_STATUS_LS BIT(2)
38#define GMAC_AN_STATUS_ANA BIT(3)
39#define GMAC_AN_STATUS_ANC BIT(5)
40#define GMAC_AN_STATUS_ES BIT(8)
41
42
43#define GMAC_ANE_FD BIT(5)
44#define GMAC_ANE_HD BIT(6)
45#define GMAC_ANE_PSE GENMASK(8, 7)
46#define GMAC_ANE_PSE_SHIFT 7
47#define GMAC_ANE_RFE GENMASK(13, 12)
48#define GMAC_ANE_RFE_SHIFT 12
49#define GMAC_ANE_ACK BIT(14)
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60static inline void dwmac_pcs_isr(void __iomem *ioaddr, u32 reg,
61 unsigned int intr_status,
62 struct stmmac_extra_stats *x)
63{
64 u32 val = readl(ioaddr + GMAC_AN_STATUS(reg));
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66 if (intr_status & PCS_ANE_IRQ) {
67 x->irq_pcs_ane_n++;
68 if (val & GMAC_AN_STATUS_ANC)
69 pr_info("stmmac_pcs: ANE process completed\n");
70 }
71
72 if (intr_status & PCS_LINK_IRQ) {
73 x->irq_pcs_link_n++;
74 if (val & GMAC_AN_STATUS_LS)
75 pr_info("stmmac_pcs: Link Up\n");
76 else
77 pr_info("stmmac_pcs: Link Down\n");
78 }
79}
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88static inline void dwmac_rane(void __iomem *ioaddr, u32 reg, bool restart)
89{
90 u32 value = readl(ioaddr + GMAC_AN_CTRL(reg));
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92 if (restart)
93 value |= GMAC_AN_CTRL_RAN;
94
95 writel(value, ioaddr + GMAC_AN_CTRL(reg));
96}
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109static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
110 bool srgmi_ral, bool loopback)
111{
112 u32 value = readl(ioaddr + GMAC_AN_CTRL(reg));
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115 if (ane)
116 value |= GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_RAN;
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121 if (srgmi_ral)
122 value |= GMAC_AN_CTRL_SGMRAL;
123
124 if (loopback)
125 value |= GMAC_AN_CTRL_ELE;
126
127 writel(value, ioaddr + GMAC_AN_CTRL(reg));
128}
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138static inline void dwmac_get_adv_lp(void __iomem *ioaddr, u32 reg,
139 struct rgmii_adv *adv_lp)
140{
141 u32 value = readl(ioaddr + GMAC_ANE_ADV(reg));
142
143 if (value & GMAC_ANE_FD)
144 adv_lp->duplex = DUPLEX_FULL;
145 if (value & GMAC_ANE_HD)
146 adv_lp->duplex |= DUPLEX_HALF;
147
148 adv_lp->pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
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150 value = readl(ioaddr + GMAC_ANE_LPA(reg));
151
152 if (value & GMAC_ANE_FD)
153 adv_lp->lp_duplex = DUPLEX_FULL;
154 if (value & GMAC_ANE_HD)
155 adv_lp->lp_duplex = DUPLEX_HALF;
156
157 adv_lp->lp_pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
158}
159#endif
160