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26#ifndef __RTL88E_DM_H__
27#define __RTL88E_DM_H__
28
29#define MAIN_ANT 0
30#define AUX_ANT 1
31#define MAIN_ANT_CG_TRX 1
32#define AUX_ANT_CG_TRX 0
33#define MAIN_ANT_CGCS_RX 0
34#define AUX_ANT_CGCS_RX 1
35
36
37#define DM_REG_RF_MODE_11N 0x00
38#define DM_REG_RF_0B_11N 0x0B
39#define DM_REG_CHNBW_11N 0x18
40#define DM_REG_T_METER_11N 0x24
41#define DM_REG_RF_25_11N 0x25
42#define DM_REG_RF_26_11N 0x26
43#define DM_REG_RF_27_11N 0x27
44#define DM_REG_RF_2B_11N 0x2B
45#define DM_REG_RF_2C_11N 0x2C
46#define DM_REG_RXRF_A3_11N 0x3C
47#define DM_REG_T_METER_92D_11N 0x42
48#define DM_REG_T_METER_88E_11N 0x42
49
50
51
52#define DM_REG_BB_CTRL_11N 0x800
53#define DM_REG_RF_PIN_11N 0x804
54#define DM_REG_PSD_CTRL_11N 0x808
55#define DM_REG_TX_ANT_CTRL_11N 0x80C
56#define DM_REG_BB_PWR_SAV5_11N 0x818
57#define DM_REG_CCK_RPT_FORMAT_11N 0x824
58#define DM_REG_RX_DEFAULT_A_11N 0x858
59#define DM_REG_RX_DEFAULT_B_11N 0x85A
60#define DM_REG_BB_PWR_SAV3_11N 0x85C
61#define DM_REG_ANTSEL_CTRL_11N 0x860
62#define DM_REG_RX_ANT_CTRL_11N 0x864
63#define DM_REG_PIN_CTRL_11N 0x870
64#define DM_REG_BB_PWR_SAV1_11N 0x874
65#define DM_REG_ANTSEL_PATH_11N 0x878
66#define DM_REG_BB_3WIRE_11N 0x88C
67#define DM_REG_SC_CNT_11N 0x8C4
68#define DM_REG_PSD_DATA_11N 0x8B4
69
70#define DM_REG_ANT_MAPPING1_11N 0x914
71#define DM_REG_ANT_MAPPING2_11N 0x918
72
73#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
74#define DM_REG_CCK_CCA_11N 0xA0A
75#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
76#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
77#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
78#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
79#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
80#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
81#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
82#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
83#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
84#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
85#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
86#define DM_REG_CCK_FA_RST_11N 0xA2C
87#define DM_REG_CCK_FA_MSB_11N 0xA58
88#define DM_REG_CCK_FA_LSB_11N 0xA5C
89#define DM_REG_CCK_CCA_CNT_11N 0xA60
90#define DM_REG_BB_PWR_SAV4_11N 0xA74
91
92#define DM_REG_LNA_SWITCH_11N 0xB2C
93#define DM_REG_PATH_SWITCH_11N 0xB30
94#define DM_REG_RSSI_CTRL_11N 0xB38
95#define DM_REG_CONFIG_ANTA_11N 0xB68
96#define DM_REG_RSSI_BT_11N 0xB9C
97
98#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
99#define DM_REG_RX_PATH_11N 0xC04
100#define DM_REG_TRMUX_11N 0xC08
101#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
102#define DM_REG_RXIQI_MATRIX_11N 0xC14
103#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
104#define DM_REG_IGI_A_11N 0xC50
105#define DM_REG_ANTDIV_PARA2_11N 0xC54
106#define DM_REG_IGI_B_11N 0xC58
107#define DM_REG_ANTDIV_PARA3_11N 0xC5C
108#define DM_REG_BB_PWR_SAV2_11N 0xC70
109#define DM_REG_RX_OFF_11N 0xC7C
110#define DM_REG_TXIQK_MATRIXA_11N 0xC80
111#define DM_REG_TXIQK_MATRIXB_11N 0xC88
112#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
113#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
114#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
115#define DM_REG_ANTDIV_PARA1_11N 0xCA4
116#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
117
118#define DM_REG_OFDM_FA_RSTD_11N 0xD00
119#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
120#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
121#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
122
123#define DM_REG_TXAGC_A_6_18_11N 0xE00
124#define DM_REG_TXAGC_A_24_54_11N 0xE04
125#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
126#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
127#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
128#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
129#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
130#define DM_REG_FPGA0_IQK_11N 0xE28
131#define DM_REG_TXIQK_TONE_A_11N 0xE30
132#define DM_REG_RXIQK_TONE_A_11N 0xE34
133#define DM_REG_TXIQK_PI_A_11N 0xE38
134#define DM_REG_RXIQK_PI_A_11N 0xE3C
135#define DM_REG_TXIQK_11N 0xE40
136#define DM_REG_RXIQK_11N 0xE44
137#define DM_REG_IQK_AGC_PTS_11N 0xE48
138#define DM_REG_IQK_AGC_RSP_11N 0xE4C
139#define DM_REG_BLUETOOTH_11N 0xE6C
140#define DM_REG_RX_WAIT_CCA_11N 0xE70
141#define DM_REG_TX_CCK_RFON_11N 0xE74
142#define DM_REG_TX_CCK_BBON_11N 0xE78
143#define DM_REG_OFDM_RFON_11N 0xE7C
144#define DM_REG_OFDM_BBON_11N 0xE80
145#define DM_REG_TX2RX_11N 0xE84
146#define DM_REG_TX2TX_11N 0xE88
147#define DM_REG_RX_CCK_11N 0xE8C
148#define DM_REG_RX_OFDM_11N 0xED0
149#define DM_REG_RX_WAIT_RIFS_11N 0xED4
150#define DM_REG_RX2RX_11N 0xED8
151#define DM_REG_STANDBY_11N 0xEDC
152#define DM_REG_SLEEP_11N 0xEE0
153#define DM_REG_PMPD_ANAEN_11N 0xEEC
154
155
156#define DM_REG_BB_RST_11N 0x02
157#define DM_REG_ANTSEL_PIN_11N 0x4C
158#define DM_REG_EARLY_MODE_11N 0x4D0
159#define DM_REG_RSSI_MONITOR_11N 0x4FE
160#define DM_REG_EDCA_VO_11N 0x500
161#define DM_REG_EDCA_VI_11N 0x504
162#define DM_REG_EDCA_BE_11N 0x508
163#define DM_REG_EDCA_BK_11N 0x50C
164#define DM_REG_TXPAUSE_11N 0x522
165#define DM_REG_RESP_TX_11N 0x6D8
166#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
167#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
168
169
170
171#define DM_BIT_IGI_11N 0x0000007F
172
173#define HAL_DM_DIG_DISABLE BIT(0)
174#define HAL_DM_HIPWR_DISABLE BIT(1)
175
176#define OFDM_TABLE_LENGTH 43
177#define CCK_TABLE_LENGTH 33
178
179#define OFDM_TABLE_SIZE 43
180#define CCK_TABLE_SIZE 33
181
182#define BW_AUTO_SWITCH_HIGH_LOW 25
183#define BW_AUTO_SWITCH_LOW_HIGH 30
184
185#define DM_DIG_FA_UPPER 0x3e
186#define DM_DIG_FA_LOWER 0x1e
187#define DM_DIG_FA_TH0 0x200
188#define DM_DIG_FA_TH1 0x300
189#define DM_DIG_FA_TH2 0x400
190
191#define RXPATHSELECTION_SS_TH_W 30
192#define RXPATHSELECTION_DIFF_TH 18
193
194#define DM_RATR_STA_INIT 0
195#define DM_RATR_STA_HIGH 1
196#define DM_RATR_STA_MIDDLE 2
197#define DM_RATR_STA_LOW 3
198
199#define CTS2SELF_THVAL 30
200#define REGC38_TH 20
201
202#define WAIOTTHVAL 25
203
204#define TXHIGHPWRLEVEL_NORMAL 0
205#define TXHIGHPWRLEVEL_LEVEL1 1
206#define TXHIGHPWRLEVEL_LEVEL2 2
207#define TXHIGHPWRLEVEL_BT1 3
208#define TXHIGHPWRLEVEL_BT2 4
209
210#define DM_TYPE_BYFW 0
211#define DM_TYPE_BYDRIVER 1
212
213#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
214#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
215#define TXPWRTRACK_MAX_IDX 6
216
217struct swat_t {
218 u8 failure_cnt;
219 u8 try_flag;
220 u8 stop_trying;
221
222 long pre_rssi;
223 long trying_threshold;
224 u8 cur_antenna;
225 u8 pre_antenna;
226
227};
228
229enum FAT_STATE {
230 FAT_NORMAL_STATE = 0,
231 FAT_TRAINING_STATE = 1,
232};
233
234enum tag_dynamic_init_gain_operation_type_definition {
235 DIG_TYPE_THRESH_HIGH = 0,
236 DIG_TYPE_THRESH_LOW = 1,
237 DIG_TYPE_BACKOFF = 2,
238 DIG_TYPE_RX_GAIN_MIN = 3,
239 DIG_TYPE_RX_GAIN_MAX = 4,
240 DIG_TYPE_ENABLE = 5,
241 DIG_TYPE_DISABLE = 6,
242 DIG_OP_TYPE_MAX
243};
244
245enum dm_1r_cca_e {
246 CCA_1R = 0,
247 CCA_2R = 1,
248 CCA_MAX = 2,
249};
250
251enum dm_rf_e {
252 RF_SAVE = 0,
253 RF_NORMAL = 1,
254 RF_MAX = 2,
255};
256
257enum dm_sw_ant_switch_e {
258 ANS_ANTENNA_B = 1,
259 ANS_ANTENNA_A = 2,
260 ANS_ANTENNA_MAX = 3,
261};
262
263enum pwr_track_control_method {
264 BBSWING,
265 TXAGC
266};
267
268void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
269 u8 *pdesc, u32 mac_id);
270void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
271 u8 antsel_tr_mux, u32 mac_id,
272 u32 rx_pwdb_all);
273void rtl88e_dm_fast_antenna_training_callback(unsigned long data);
274void rtl88e_dm_init(struct ieee80211_hw *hw);
275void rtl88e_dm_watchdog(struct ieee80211_hw *hw);
276void rtl88e_dm_write_dig(struct ieee80211_hw *hw);
277void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw);
278void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
279void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
280void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
281 u8 type, u8 *pdirection, u32 *poutwrite_val);
282#endif
283