LXR linux/drivers/net/wireless/rsi/rsi_boot

   1/**
   2 * Copyright (c) 2014 Redpine Signals Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#ifndef __RSI_BOOTPARAMS_HEADER_H__
  18#define __RSI_BOOTPARAMS_HEADER_H__
  19
  20#define CRYSTAL_GOOD_TIME                BIT(0)
  21#define BOOTUP_MODE_INFO                 BIT(1)
  22#define WIFI_TAPLL_CONFIGS               BIT(5)
  23#define WIFI_PLL960_CONFIGS              BIT(6)
  24#define WIFI_AFEPLL_CONFIGS              BIT(7)
  25#define WIFI_SWITCH_CLK_CONFIGS          BIT(8)
  26
  27#define TA_PLL_M_VAL_20                  9
  28#define TA_PLL_N_VAL_20                  0
  29#define TA_PLL_P_VAL_20                  4
  30
  31#define PLL960_M_VAL_20                  0x14
  32#define PLL960_N_VAL_20                  0
  33#define PLL960_P_VAL_20                  5
  34
  35#define UMAC_CLK_40MHZ                   80
  36
  37#define TA_PLL_M_VAL_40                  9
  38#define TA_PLL_N_VAL_40                  0
  39#define TA_PLL_P_VAL_40                  4
  40
  41#define PLL960_M_VAL_40                  0x14
  42#define PLL960_N_VAL_40                  0
  43#define PLL960_P_VAL_40                  5
  44
  45#define UMAC_CLK_20BW \
  46        (((TA_PLL_M_VAL_20 + 1) * 40) / \
  47         ((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1)))
  48#define VALID_20 \
  49        (WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS)
  50#define UMAC_CLK_40BW   \
  51        (((TA_PLL_M_VAL_40 + 1) * 40) / \
  52         ((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1)))
  53#define VALID_40 \
  54        (WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
  55         WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
  56
  57/* structure to store configs related to TAPLL programming */
  58struct tapll_info {
  59        __le16 pll_reg_1;
  60        __le16 pll_reg_2;
  61} __packed;
  62
  63/* structure to store configs related to PLL960 programming */
  64struct pll960_info {
  65        __le16 pll_reg_1;
  66        __le16 pll_reg_2;
  67        __le16 pll_reg_3;
  68} __packed;
  69
  70/* structure to store configs related to AFEPLL programming */
  71struct afepll_info {
  72        __le16 pll_reg;
  73} __packed;
  74
  75/* structure to store configs related to pll configs */
  76struct pll_config {
  77        struct tapll_info tapll_info_g;
  78        struct pll960_info pll960_info_g;
  79        struct afepll_info afepll_info_g;
  80} __packed;
  81
  82/* structure to store configs related to UMAC clk programming */
  83struct switch_clk {
  84        __le16 switch_clk_info;
  85        /* If switch_bbp_lmac_clk_reg is set then this value will be programmed
  86         * into reg
  87         */
  88        __le16 bbp_lmac_clk_reg_val;
  89        /* if switch_umac_clk is set then this value will be programmed */
  90        __le16 umac_clock_reg_config;
  91        /* if switch_qspi_clk is set then this value will be programmed */
  92        __le16 qspi_uart_clock_reg_config;
  93} __packed;
  94
  95struct device_clk_info {
  96        struct pll_config pll_config_g;
  97        struct switch_clk switch_clk_g;
  98} __packed;
  99
 100struct bootup_params {
 101        __le16 magic_number;
 102        __le16 crystal_good_time;
 103        __le32 valid;
 104        __le32 reserved_for_valids;
 105        __le16 bootup_mode_info;
 106        /* configuration used for digital loop back */
 107        __le16 digital_loop_back_params;
 108        __le16 rtls_timestamp_en;
 109        __le16 host_spi_intr_cfg;
 110        struct device_clk_info device_clk_info[3];
 111        /* ulp buckboost wait time  */
 112        __le32 buckboost_wakeup_cnt;
 113        /* pmu wakeup wait time & WDT EN info */
 114        __le16 pmu_wakeup_wait;
 115        u8 shutdown_wait_time;
 116        /* Sleep clock source selection */
 117        u8 pmu_slp_clkout_sel;
 118        /* WDT programming values */
 119        __le32 wdt_prog_value;
 120        /* WDT soc reset delay */
 121        __le32 wdt_soc_rst_delay;
 122        /* dcdc modes configs */
 123        __le32 dcdc_operation_mode;
 124        __le32 soc_reset_wait_cnt;
 125        __le32 waiting_time_at_fresh_sleep;
 126        __le32 max_threshold_to_avoid_sleep;
 127        u8 beacon_resedue_alg_en;
 128} __packed;
 129#endif
 130