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33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/spinlock.h>
38#include <linux/slab.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/completion.h>
42#include <linux/time.h>
43#include <linux/interrupt.h>
44#include <scsi/scsi_host.h>
45
46#include "aacraid.h"
47
48static int aac_src_get_sync_status(struct aac_dev *dev);
49
50static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
51{
52 struct aac_msix_ctx *ctx;
53 struct aac_dev *dev;
54 unsigned long bellbits, bellbits_shifted;
55 int vector_no;
56 int isFastResponse, mode;
57 u32 index, handle;
58
59 ctx = (struct aac_msix_ctx *)dev_id;
60 dev = ctx->dev;
61 vector_no = ctx->vector_no;
62
63 if (dev->msi_enabled) {
64 mode = AAC_INT_MODE_MSI;
65 if (vector_no == 0) {
66 bellbits = src_readl(dev, MUnit.ODR_MSI);
67 if (bellbits & 0x40000)
68 mode |= AAC_INT_MODE_AIF;
69 if (bellbits & 0x1000)
70 mode |= AAC_INT_MODE_SYNC;
71 }
72 } else {
73 mode = AAC_INT_MODE_INTX;
74 bellbits = src_readl(dev, MUnit.ODR_R);
75 if (bellbits & PmDoorBellResponseSent) {
76 bellbits = PmDoorBellResponseSent;
77 src_writel(dev, MUnit.ODR_C, bellbits);
78 src_readl(dev, MUnit.ODR_C);
79 } else {
80 bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
81 src_writel(dev, MUnit.ODR_C, bellbits);
82 src_readl(dev, MUnit.ODR_C);
83
84 if (bellbits_shifted & DoorBellAifPending)
85 mode |= AAC_INT_MODE_AIF;
86 else if (bellbits_shifted & OUTBOUNDDOORBELL_0)
87 mode |= AAC_INT_MODE_SYNC;
88 }
89 }
90
91 if (mode & AAC_INT_MODE_SYNC) {
92 unsigned long sflags;
93 struct list_head *entry;
94 int send_it = 0;
95 extern int aac_sync_mode;
96
97 if (!aac_sync_mode && !dev->msi_enabled) {
98 src_writel(dev, MUnit.ODR_C, bellbits);
99 src_readl(dev, MUnit.ODR_C);
100 }
101
102 if (dev->sync_fib) {
103 if (dev->sync_fib->callback)
104 dev->sync_fib->callback(dev->sync_fib->callback_data,
105 dev->sync_fib);
106 spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
107 if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
108 dev->management_fib_count--;
109 up(&dev->sync_fib->event_wait);
110 }
111 spin_unlock_irqrestore(&dev->sync_fib->event_lock,
112 sflags);
113 spin_lock_irqsave(&dev->sync_lock, sflags);
114 if (!list_empty(&dev->sync_fib_list)) {
115 entry = dev->sync_fib_list.next;
116 dev->sync_fib = list_entry(entry,
117 struct fib,
118 fiblink);
119 list_del(entry);
120 send_it = 1;
121 } else {
122 dev->sync_fib = NULL;
123 }
124 spin_unlock_irqrestore(&dev->sync_lock, sflags);
125 if (send_it) {
126 aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
127 (u32)dev->sync_fib->hw_fib_pa,
128 0, 0, 0, 0, 0,
129 NULL, NULL, NULL, NULL, NULL);
130 }
131 }
132 if (!dev->msi_enabled)
133 mode = 0;
134
135 }
136
137 if (mode & AAC_INT_MODE_AIF) {
138
139 if (dev->sa_firmware) {
140 u32 events = src_readl(dev, MUnit.SCR0);
141
142 aac_intr_normal(dev, events, 1, 0, NULL);
143 writel(events, &dev->IndexRegs->Mailbox[0]);
144 src_writel(dev, MUnit.IDR, 1 << 23);
145 } else {
146 if (dev->aif_thread && dev->fsa_dev)
147 aac_intr_normal(dev, 0, 2, 0, NULL);
148 }
149 if (dev->msi_enabled)
150 aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT);
151 mode = 0;
152 }
153
154 if (mode) {
155 index = dev->host_rrq_idx[vector_no];
156
157 for (;;) {
158 isFastResponse = 0;
159
160 handle = le32_to_cpu((dev->host_rrq[index])
161 & 0x7fffffff);
162
163 if (handle & 0x40000000)
164 isFastResponse = 1;
165 handle &= 0x0000ffff;
166 if (handle == 0)
167 break;
168 handle >>= 2;
169 if (dev->msi_enabled && dev->max_msix > 1)
170 atomic_dec(&dev->rrq_outstanding[vector_no]);
171 aac_intr_normal(dev, handle, 0, isFastResponse, NULL);
172 dev->host_rrq[index++] = 0;
173 if (index == (vector_no + 1) * dev->vector_cap)
174 index = vector_no * dev->vector_cap;
175 dev->host_rrq_idx[vector_no] = index;
176 }
177 mode = 0;
178 }
179
180 return IRQ_HANDLED;
181}
182
183
184
185
186
187
188static void aac_src_disable_interrupt(struct aac_dev *dev)
189{
190 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
191}
192
193
194
195
196
197
198static void aac_src_enable_interrupt_message(struct aac_dev *dev)
199{
200 aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT);
201}
202
203
204
205
206
207
208
209
210
211
212
213
214static int src_sync_cmd(struct aac_dev *dev, u32 command,
215 u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
216 u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
217{
218 unsigned long start;
219 unsigned long delay;
220 int ok;
221
222
223
224
225 writel(command, &dev->IndexRegs->Mailbox[0]);
226
227
228
229 writel(p1, &dev->IndexRegs->Mailbox[1]);
230 writel(p2, &dev->IndexRegs->Mailbox[2]);
231 writel(p3, &dev->IndexRegs->Mailbox[3]);
232 writel(p4, &dev->IndexRegs->Mailbox[4]);
233
234
235
236
237 if (!dev->msi_enabled)
238 src_writel(dev,
239 MUnit.ODR_C,
240 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
241
242
243
244
245 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
246
247
248
249
250
251 src_readl(dev, MUnit.OIMR);
252
253
254
255
256 src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
257
258 if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) {
259 ok = 0;
260 start = jiffies;
261
262 if (command == IOP_RESET_ALWAYS) {
263
264 delay = 10*HZ;
265 } else {
266
267 delay = 300*HZ;
268 }
269 while (time_before(jiffies, start+delay)) {
270 udelay(5);
271
272
273
274 if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
275
276
277
278 if (dev->msi_enabled)
279 aac_src_access_devreg(dev,
280 AAC_CLEAR_SYNC_BIT);
281 else
282 src_writel(dev,
283 MUnit.ODR_C,
284 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
285 ok = 1;
286 break;
287 }
288
289
290
291 msleep(1);
292 }
293 if (unlikely(ok != 1)) {
294
295
296
297 aac_adapter_enable_int(dev);
298 return -ETIMEDOUT;
299 }
300
301
302
303 if (status)
304 *status = readl(&dev->IndexRegs->Mailbox[0]);
305 if (r1)
306 *r1 = readl(&dev->IndexRegs->Mailbox[1]);
307 if (r2)
308 *r2 = readl(&dev->IndexRegs->Mailbox[2]);
309 if (r3)
310 *r3 = readl(&dev->IndexRegs->Mailbox[3]);
311 if (r4)
312 *r4 = readl(&dev->IndexRegs->Mailbox[4]);
313 if (command == GET_COMM_PREFERRED_SETTINGS)
314 dev->max_msix =
315 readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF;
316
317
318
319 if (!dev->msi_enabled)
320 src_writel(dev,
321 MUnit.ODR_C,
322 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
323 }
324
325
326
327
328 aac_adapter_enable_int(dev);
329 return 0;
330}
331
332
333
334
335
336
337
338
339static void aac_src_interrupt_adapter(struct aac_dev *dev)
340{
341 src_sync_cmd(dev, BREAKPOINT_REQUEST,
342 0, 0, 0, 0, 0, 0,
343 NULL, NULL, NULL, NULL, NULL);
344}
345
346
347
348
349
350
351
352
353
354
355static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
356{
357 switch (event) {
358
359 case AdapNormCmdQue:
360 src_writel(dev, MUnit.ODR_C,
361 INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
362 break;
363 case HostNormRespNotFull:
364 src_writel(dev, MUnit.ODR_C,
365 INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
366 break;
367 case AdapNormRespQue:
368 src_writel(dev, MUnit.ODR_C,
369 INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
370 break;
371 case HostNormCmdNotFull:
372 src_writel(dev, MUnit.ODR_C,
373 INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
374 break;
375 case FastIo:
376 src_writel(dev, MUnit.ODR_C,
377 INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
378 break;
379 case AdapPrintfDone:
380 src_writel(dev, MUnit.ODR_C,
381 INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
382 break;
383 default:
384 BUG();
385 break;
386 }
387}
388
389
390
391
392
393
394
395
396static void aac_src_start_adapter(struct aac_dev *dev)
397{
398 union aac_init *init;
399 int i;
400
401
402 for (i = 0; i < dev->max_msix; i++) {
403 dev->host_rrq_idx[i] = i * dev->vector_cap;
404 atomic_set(&dev->rrq_outstanding[i], 0);
405 }
406 atomic_set(&dev->msix_counter, 0);
407 dev->fibs_pushed_no = 0;
408
409 init = dev->init;
410 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
411 init->r8.host_elapsed_seconds = cpu_to_le32(get_seconds());
412 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
413 lower_32_bits(dev->init_pa),
414 upper_32_bits(dev->init_pa),
415 sizeof(struct _r8) +
416 (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq),
417 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
418 } else {
419 init->r7.host_elapsed_seconds = cpu_to_le32(get_seconds());
420
421 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
422 (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
423 NULL, NULL, NULL, NULL, NULL);
424 }
425
426}
427
428
429
430
431
432
433
434
435static int aac_src_check_health(struct aac_dev *dev)
436{
437 u32 status = src_readl(dev, MUnit.OMR);
438
439
440
441
442 if (unlikely(status & KERNEL_PANIC))
443 goto err_blink;
444
445
446
447
448 if (unlikely(status & SELF_TEST_FAILED))
449 goto err_out;
450
451
452
453
454 if (unlikely(status & MONITOR_PANIC))
455 goto err_out;
456
457
458
459
460 if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
461 return -3;
462
463
464
465 return 0;
466
467err_out:
468 return -1;
469
470err_blink:
471 return (status >> 16) & 0xFF;
472}
473
474static inline u32 aac_get_vector(struct aac_dev *dev)
475{
476 return atomic_inc_return(&dev->msix_counter)%dev->max_msix;
477}
478
479
480
481
482
483
484
485static int aac_src_deliver_message(struct fib *fib)
486{
487 struct aac_dev *dev = fib->dev;
488 struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
489 u32 fibsize;
490 dma_addr_t address;
491 struct aac_fib_xporthdr *pFibX;
492 int native_hba;
493#if !defined(writeq)
494 unsigned long flags;
495#endif
496
497 u16 vector_no;
498
499 atomic_inc(&q->numpending);
500
501 native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0;
502
503
504 if (dev->msi_enabled && dev->max_msix > 1 &&
505 (native_hba || fib->hw_fib_va->header.Command != AifRequest)) {
506
507 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)
508 && dev->sa_firmware)
509 vector_no = aac_get_vector(dev);
510 else
511 vector_no = fib->vector_no;
512
513 if (native_hba) {
514 if (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA_TMF) {
515 struct aac_hba_tm_req *tm_req;
516
517 tm_req = (struct aac_hba_tm_req *)
518 fib->hw_fib_va;
519 if (tm_req->iu_type ==
520 HBA_IU_TYPE_SCSI_TM_REQ) {
521 ((struct aac_hba_tm_req *)
522 fib->hw_fib_va)->reply_qid
523 = vector_no;
524 ((struct aac_hba_tm_req *)
525 fib->hw_fib_va)->request_id
526 += (vector_no << 16);
527 } else {
528 ((struct aac_hba_reset_req *)
529 fib->hw_fib_va)->reply_qid
530 = vector_no;
531 ((struct aac_hba_reset_req *)
532 fib->hw_fib_va)->request_id
533 += (vector_no << 16);
534 }
535 } else {
536 ((struct aac_hba_cmd_req *)
537 fib->hw_fib_va)->reply_qid
538 = vector_no;
539 ((struct aac_hba_cmd_req *)
540 fib->hw_fib_va)->request_id
541 += (vector_no << 16);
542 }
543 } else {
544 fib->hw_fib_va->header.Handle += (vector_no << 16);
545 }
546 } else {
547 vector_no = 0;
548 }
549
550 atomic_inc(&dev->rrq_outstanding[vector_no]);
551
552 if (native_hba) {
553 address = fib->hw_fib_pa;
554 fibsize = (fib->hbacmd_size + 127) / 128 - 1;
555 if (fibsize > 31)
556 fibsize = 31;
557 address |= fibsize;
558#if defined(writeq)
559 src_writeq(dev, MUnit.IQN_L, (u64)address);
560#else
561 spin_lock_irqsave(&fib->dev->iq_lock, flags);
562 src_writel(dev, MUnit.IQN_H,
563 upper_32_bits(address) & 0xffffffff);
564 src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
565 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
566#endif
567 } else {
568 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 ||
569 dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
570
571 fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size)
572 + 127) / 128 - 1;
573
574 address = fib->hw_fib_pa;
575 fib->hw_fib_va->header.StructType = FIB_MAGIC2;
576 fib->hw_fib_va->header.SenderFibAddress =
577 cpu_to_le32((u32)address);
578 fib->hw_fib_va->header.u.TimeStamp = 0;
579 WARN_ON(upper_32_bits(address) != 0L);
580 } else {
581
582 fibsize = (sizeof(struct aac_fib_xporthdr) +
583 le16_to_cpu(fib->hw_fib_va->header.Size)
584 + 127) / 128 - 1;
585
586 pFibX = (struct aac_fib_xporthdr *)
587 ((unsigned char *)fib->hw_fib_va -
588 sizeof(struct aac_fib_xporthdr));
589 pFibX->Handle = fib->hw_fib_va->header.Handle;
590 pFibX->HostAddress =
591 cpu_to_le64((u64)fib->hw_fib_pa);
592 pFibX->Size = cpu_to_le32(
593 le16_to_cpu(fib->hw_fib_va->header.Size));
594 address = fib->hw_fib_pa -
595 (u64)sizeof(struct aac_fib_xporthdr);
596 }
597 if (fibsize > 31)
598 fibsize = 31;
599 address |= fibsize;
600
601#if defined(writeq)
602 src_writeq(dev, MUnit.IQ_L, (u64)address);
603#else
604 spin_lock_irqsave(&fib->dev->iq_lock, flags);
605 src_writel(dev, MUnit.IQ_H,
606 upper_32_bits(address) & 0xffffffff);
607 src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
608 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
609#endif
610 }
611 return 0;
612}
613
614
615
616
617
618
619static int aac_src_ioremap(struct aac_dev *dev, u32 size)
620{
621 if (!size) {
622 iounmap(dev->regs.src.bar1);
623 dev->regs.src.bar1 = NULL;
624 iounmap(dev->regs.src.bar0);
625 dev->base = dev->regs.src.bar0 = NULL;
626 return 0;
627 }
628 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
629 AAC_MIN_SRC_BAR1_SIZE);
630 dev->base = NULL;
631 if (dev->regs.src.bar1 == NULL)
632 return -1;
633 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
634 if (dev->base == NULL) {
635 iounmap(dev->regs.src.bar1);
636 dev->regs.src.bar1 = NULL;
637 return -1;
638 }
639 dev->IndexRegs = &((struct src_registers __iomem *)
640 dev->base)->u.tupelo.IndexRegs;
641 return 0;
642}
643
644
645
646
647
648
649static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
650{
651 if (!size) {
652 iounmap(dev->regs.src.bar0);
653 dev->base = dev->regs.src.bar0 = NULL;
654 return 0;
655 }
656
657 dev->regs.src.bar1 =
658 ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE);
659 dev->base = NULL;
660 if (dev->regs.src.bar1 == NULL)
661 return -1;
662 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
663 if (dev->base == NULL) {
664 iounmap(dev->regs.src.bar1);
665 dev->regs.src.bar1 = NULL;
666 return -1;
667 }
668 dev->IndexRegs = &((struct src_registers __iomem *)
669 dev->base)->u.denali.IndexRegs;
670 return 0;
671}
672
673void aac_set_intx_mode(struct aac_dev *dev)
674{
675 if (dev->msi_enabled) {
676 aac_src_access_devreg(dev, AAC_ENABLE_INTX);
677 dev->msi_enabled = 0;
678 msleep(5000);
679 }
680}
681
682static void aac_dump_fw_fib_iop_reset(struct aac_dev *dev)
683{
684 __le32 supported_options3;
685
686 if (!aac_fib_dump)
687 return;
688
689 supported_options3 = dev->supplement_adapter_info.supported_options3;
690 if (!(supported_options3 & AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP))
691 return;
692
693 aac_adapter_sync_cmd(dev, IOP_RESET_FW_FIB_DUMP,
694 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
695}
696
697static bool aac_is_ctrl_up_and_running(struct aac_dev *dev)
698{
699 bool ctrl_up = true;
700 unsigned long status, start;
701 bool is_up = false;
702
703 start = jiffies;
704 do {
705 schedule();
706 status = src_readl(dev, MUnit.OMR);
707
708 if (status == 0xffffffff)
709 status = 0;
710
711 if (status & KERNEL_BOOTING) {
712 start = jiffies;
713 continue;
714 }
715
716 if (time_after(jiffies, start+HZ*SOFT_RESET_TIME)) {
717 ctrl_up = false;
718 break;
719 }
720
721 is_up = status & KERNEL_UP_AND_RUNNING;
722
723 } while (!is_up);
724
725 return ctrl_up;
726}
727
728static void aac_notify_fw_of_iop_reset(struct aac_dev *dev)
729{
730 aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS, 0, 0, 0, 0, 0, 0, NULL,
731 NULL, NULL, NULL, NULL);
732}
733
734static void aac_send_iop_reset(struct aac_dev *dev)
735{
736 aac_dump_fw_fib_iop_reset(dev);
737
738 aac_notify_fw_of_iop_reset(dev);
739
740 aac_set_intx_mode(dev);
741
742 src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
743
744 msleep(5000);
745}
746
747static void aac_send_hardware_soft_reset(struct aac_dev *dev)
748{
749 u_int32_t val;
750
751 val = readl(((char *)(dev->base) + IBW_SWR_OFFSET));
752 val |= 0x01;
753 writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
754 msleep_interruptible(20000);
755}
756
757static int aac_src_restart_adapter(struct aac_dev *dev, int bled, u8 reset_type)
758{
759 bool is_ctrl_up;
760 int ret = 0;
761
762 if (bled < 0)
763 goto invalid_out;
764
765 if (bled)
766 dev_err(&dev->pdev->dev, "adapter kernel panic'd %x.\n", bled);
767
768
769
770
771 if (bled >= 2 && dev->sa_firmware && reset_type & HW_IOP_RESET)
772 reset_type &= ~HW_IOP_RESET;
773
774 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
775
776 dev_err(&dev->pdev->dev, "Controller reset type is %d\n", reset_type);
777
778 if (reset_type & HW_IOP_RESET) {
779 dev_info(&dev->pdev->dev, "Issuing IOP reset\n");
780 aac_send_iop_reset(dev);
781
782
783
784
785 is_ctrl_up = aac_is_ctrl_up_and_running(dev);
786 if (!is_ctrl_up)
787 dev_err(&dev->pdev->dev, "IOP reset failed\n");
788 else {
789 dev_info(&dev->pdev->dev, "IOP reset succeded\n");
790 goto set_startup;
791 }
792 }
793
794 if (!dev->sa_firmware) {
795 dev_err(&dev->pdev->dev, "ARC Reset attempt failed\n");
796 ret = -ENODEV;
797 goto out;
798 }
799
800 if (reset_type & HW_SOFT_RESET) {
801 dev_info(&dev->pdev->dev, "Issuing SOFT reset\n");
802 aac_send_hardware_soft_reset(dev);
803 dev->msi_enabled = 0;
804
805 is_ctrl_up = aac_is_ctrl_up_and_running(dev);
806 if (!is_ctrl_up) {
807 dev_err(&dev->pdev->dev, "SOFT reset failed\n");
808 ret = -ENODEV;
809 goto out;
810 } else
811 dev_info(&dev->pdev->dev, "SOFT reset succeded\n");
812 }
813
814set_startup:
815 if (startup_timeout < 300)
816 startup_timeout = 300;
817
818out:
819 return ret;
820
821invalid_out:
822 if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
823 ret = -ENODEV;
824goto out;
825}
826
827
828
829
830
831
832static int aac_src_select_comm(struct aac_dev *dev, int comm)
833{
834 switch (comm) {
835 case AAC_COMM_MESSAGE:
836 dev->a_ops.adapter_intr = aac_src_intr_message;
837 dev->a_ops.adapter_deliver = aac_src_deliver_message;
838 break;
839 default:
840 return 1;
841 }
842 return 0;
843}
844
845
846
847
848
849
850
851int aac_src_init(struct aac_dev *dev)
852{
853 unsigned long start;
854 unsigned long status;
855 int restart = 0;
856 int instance = dev->id;
857 const char *name = dev->name;
858
859 dev->a_ops.adapter_ioremap = aac_src_ioremap;
860 dev->a_ops.adapter_comm = aac_src_select_comm;
861
862 dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
863 if (aac_adapter_ioremap(dev, dev->base_size)) {
864 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
865 goto error_iounmap;
866 }
867
868
869 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
870 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
871 if ((aac_reset_devices || reset_devices) &&
872 !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
873 ++restart;
874
875
876
877 status = src_readl(dev, MUnit.OMR);
878 if (status & KERNEL_PANIC) {
879 if (aac_src_restart_adapter(dev,
880 aac_src_check_health(dev), IOP_HWSOFT_RESET))
881 goto error_iounmap;
882 ++restart;
883 }
884
885
886
887 status = src_readl(dev, MUnit.OMR);
888 if (status & SELF_TEST_FAILED) {
889 printk(KERN_ERR "%s%d: adapter self-test failed.\n",
890 dev->name, instance);
891 goto error_iounmap;
892 }
893
894
895
896 if (status & MONITOR_PANIC) {
897 printk(KERN_ERR "%s%d: adapter monitor panic.\n",
898 dev->name, instance);
899 goto error_iounmap;
900 }
901 start = jiffies;
902
903
904
905 while (!((status = src_readl(dev, MUnit.OMR)) &
906 KERNEL_UP_AND_RUNNING)) {
907 if ((restart &&
908 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
909 time_after(jiffies, start+HZ*startup_timeout)) {
910 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
911 dev->name, instance, status);
912 goto error_iounmap;
913 }
914 if (!restart &&
915 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
916 time_after(jiffies, start + HZ *
917 ((startup_timeout > 60)
918 ? (startup_timeout - 60)
919 : (startup_timeout / 2))))) {
920 if (likely(!aac_src_restart_adapter(dev,
921 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
922 start = jiffies;
923 ++restart;
924 }
925 msleep(1);
926 }
927 if (restart && aac_commit)
928 aac_commit = 1;
929
930
931
932 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
933 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
934 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
935 dev->a_ops.adapter_notify = aac_src_notify_adapter;
936 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
937 dev->a_ops.adapter_check_health = aac_src_check_health;
938 dev->a_ops.adapter_restart = aac_src_restart_adapter;
939 dev->a_ops.adapter_start = aac_src_start_adapter;
940
941
942
943
944
945 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
946 aac_adapter_disable_int(dev);
947 src_writel(dev, MUnit.ODR_C, 0xffffffff);
948 aac_adapter_enable_int(dev);
949
950 if (aac_init_adapter(dev) == NULL)
951 goto error_iounmap;
952 if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
953 goto error_iounmap;
954
955 dev->msi = !pci_enable_msi(dev->pdev);
956
957 dev->aac_msix[0].vector_no = 0;
958 dev->aac_msix[0].dev = dev;
959
960 if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
961 IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) {
962
963 if (dev->msi)
964 pci_disable_msi(dev->pdev);
965
966 printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
967 name, instance);
968 goto error_iounmap;
969 }
970 dev->dbg_base = pci_resource_start(dev->pdev, 2);
971 dev->dbg_base_mapped = dev->regs.src.bar1;
972 dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
973 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
974
975 aac_adapter_enable_int(dev);
976
977 if (!dev->sync_mode) {
978
979
980
981
982 aac_src_start_adapter(dev);
983 }
984 return 0;
985
986error_iounmap:
987
988 return -1;
989}
990
991
992
993
994
995
996
997int aac_srcv_init(struct aac_dev *dev)
998{
999 unsigned long start;
1000 unsigned long status;
1001 int restart = 0;
1002 int instance = dev->id;
1003 const char *name = dev->name;
1004
1005 dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
1006 dev->a_ops.adapter_comm = aac_src_select_comm;
1007
1008 dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
1009 if (aac_adapter_ioremap(dev, dev->base_size)) {
1010 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
1011 goto error_iounmap;
1012 }
1013
1014
1015 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
1016 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
1017 if ((aac_reset_devices || reset_devices) &&
1018 !aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
1019 ++restart;
1020
1021
1022
1023
1024 status = src_readl(dev, MUnit.OMR);
1025 if (status & FLASH_UPD_PENDING) {
1026 start = jiffies;
1027 do {
1028 status = src_readl(dev, MUnit.OMR);
1029 if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
1030 printk(KERN_ERR "%s%d: adapter flash update failed.\n",
1031 dev->name, instance);
1032 goto error_iounmap;
1033 }
1034 } while (!(status & FLASH_UPD_SUCCESS) &&
1035 !(status & FLASH_UPD_FAILED));
1036
1037
1038
1039
1040 ssleep(10);
1041 }
1042
1043
1044
1045 status = src_readl(dev, MUnit.OMR);
1046 if (status & KERNEL_PANIC) {
1047 if (aac_src_restart_adapter(dev,
1048 aac_src_check_health(dev), IOP_HWSOFT_RESET))
1049 goto error_iounmap;
1050 ++restart;
1051 }
1052
1053
1054
1055 status = src_readl(dev, MUnit.OMR);
1056 if (status & SELF_TEST_FAILED) {
1057 printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
1058 goto error_iounmap;
1059 }
1060
1061
1062
1063 if (status & MONITOR_PANIC) {
1064 printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
1065 goto error_iounmap;
1066 }
1067 start = jiffies;
1068
1069
1070
1071 while (!((status = src_readl(dev, MUnit.OMR)) &
1072 KERNEL_UP_AND_RUNNING) ||
1073 status == 0xffffffff) {
1074 if ((restart &&
1075 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
1076 time_after(jiffies, start+HZ*startup_timeout)) {
1077 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
1078 dev->name, instance, status);
1079 goto error_iounmap;
1080 }
1081 if (!restart &&
1082 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
1083 time_after(jiffies, start + HZ *
1084 ((startup_timeout > 60)
1085 ? (startup_timeout - 60)
1086 : (startup_timeout / 2))))) {
1087 if (likely(!aac_src_restart_adapter(dev,
1088 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
1089 start = jiffies;
1090 ++restart;
1091 }
1092 msleep(1);
1093 }
1094 if (restart && aac_commit)
1095 aac_commit = 1;
1096
1097
1098
1099 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
1100 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
1101 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
1102 dev->a_ops.adapter_notify = aac_src_notify_adapter;
1103 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
1104 dev->a_ops.adapter_check_health = aac_src_check_health;
1105 dev->a_ops.adapter_restart = aac_src_restart_adapter;
1106 dev->a_ops.adapter_start = aac_src_start_adapter;
1107
1108
1109
1110
1111
1112 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
1113 aac_adapter_disable_int(dev);
1114 src_writel(dev, MUnit.ODR_C, 0xffffffff);
1115 aac_adapter_enable_int(dev);
1116
1117 if (aac_init_adapter(dev) == NULL)
1118 goto error_iounmap;
1119 if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) &&
1120 (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3))
1121 goto error_iounmap;
1122 if (dev->msi_enabled)
1123 aac_src_access_devreg(dev, AAC_ENABLE_MSIX);
1124
1125 if (aac_acquire_irq(dev))
1126 goto error_iounmap;
1127
1128 dev->dbg_base = pci_resource_start(dev->pdev, 2);
1129 dev->dbg_base_mapped = dev->regs.src.bar1;
1130 dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE;
1131 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
1132
1133 aac_adapter_enable_int(dev);
1134
1135 if (!dev->sync_mode) {
1136
1137
1138
1139
1140 aac_src_start_adapter(dev);
1141 }
1142 return 0;
1143
1144error_iounmap:
1145
1146 return -1;
1147}
1148
1149void aac_src_access_devreg(struct aac_dev *dev, int mode)
1150{
1151 u_int32_t val;
1152
1153 switch (mode) {
1154 case AAC_ENABLE_INTERRUPT:
1155 src_writel(dev,
1156 MUnit.OIMR,
1157 dev->OIMR = (dev->msi_enabled ?
1158 AAC_INT_ENABLE_TYPE1_MSIX :
1159 AAC_INT_ENABLE_TYPE1_INTX));
1160 break;
1161
1162 case AAC_DISABLE_INTERRUPT:
1163 src_writel(dev,
1164 MUnit.OIMR,
1165 dev->OIMR = AAC_INT_DISABLE_ALL);
1166 break;
1167
1168 case AAC_ENABLE_MSIX:
1169
1170 val = src_readl(dev, MUnit.IDR);
1171 val |= 0x40;
1172 src_writel(dev, MUnit.IDR, val);
1173 src_readl(dev, MUnit.IDR);
1174
1175 val = PMC_ALL_INTERRUPT_BITS;
1176 src_writel(dev, MUnit.IOAR, val);
1177 val = src_readl(dev, MUnit.OIMR);
1178 src_writel(dev,
1179 MUnit.OIMR,
1180 val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0)));
1181 break;
1182
1183 case AAC_DISABLE_MSIX:
1184
1185 val = src_readl(dev, MUnit.IDR);
1186 val &= ~0x40;
1187 src_writel(dev, MUnit.IDR, val);
1188 src_readl(dev, MUnit.IDR);
1189 break;
1190
1191 case AAC_CLEAR_AIF_BIT:
1192
1193 val = src_readl(dev, MUnit.IDR);
1194 val |= 0x20;
1195 src_writel(dev, MUnit.IDR, val);
1196 src_readl(dev, MUnit.IDR);
1197 break;
1198
1199 case AAC_CLEAR_SYNC_BIT:
1200
1201 val = src_readl(dev, MUnit.IDR);
1202 val |= 0x10;
1203 src_writel(dev, MUnit.IDR, val);
1204 src_readl(dev, MUnit.IDR);
1205 break;
1206
1207 case AAC_ENABLE_INTX:
1208
1209 val = src_readl(dev, MUnit.IDR);
1210 val |= 0x80;
1211 src_writel(dev, MUnit.IDR, val);
1212 src_readl(dev, MUnit.IDR);
1213
1214 val = PMC_ALL_INTERRUPT_BITS;
1215 src_writel(dev, MUnit.IOAR, val);
1216 src_readl(dev, MUnit.IOAR);
1217 val = src_readl(dev, MUnit.OIMR);
1218 src_writel(dev, MUnit.OIMR,
1219 val & (~(PMC_GLOBAL_INT_BIT2)));
1220 break;
1221
1222 default:
1223 break;
1224 }
1225}
1226
1227static int aac_src_get_sync_status(struct aac_dev *dev)
1228{
1229
1230 int val;
1231
1232 if (dev->msi_enabled)
1233 val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0;
1234 else
1235 val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT;
1236
1237 return val;
1238}
1239
