linux/drivers/tty/serial/8250/8250_port.c
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   1/*
   2 *  Base port operations for 8250/16550-type serial ports
   3 *
   4 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5 *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * A note about mapbase / membase
  13 *
  14 *  mapbase is the physical address of the IO port.
  15 *  membase is an 'ioremapped' cookie.
  16 */
  17
  18#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  19#define SUPPORT_SYSRQ
  20#endif
  21
  22#include <linux/module.h>
  23#include <linux/moduleparam.h>
  24#include <linux/ioport.h>
  25#include <linux/init.h>
  26#include <linux/console.h>
  27#include <linux/sysrq.h>
  28#include <linux/delay.h>
  29#include <linux/platform_device.h>
  30#include <linux/tty.h>
  31#include <linux/ratelimit.h>
  32#include <linux/tty_flip.h>
  33#include <linux/serial.h>
  34#include <linux/serial_8250.h>
  35#include <linux/nmi.h>
  36#include <linux/mutex.h>
  37#include <linux/slab.h>
  38#include <linux/uaccess.h>
  39#include <linux/pm_runtime.h>
  40#include <linux/ktime.h>
  41
  42#include <asm/io.h>
  43#include <asm/irq.h>
  44
  45#include "8250.h"
  46
  47/*
  48 * These are definitions for the Exar XR17V35X and XR17(C|D)15X
  49 */
  50#define UART_EXAR_INT0          0x80
  51#define UART_EXAR_SLEEP         0x8b    /* Sleep mode */
  52#define UART_EXAR_DVID          0x8d    /* Device identification */
  53
  54/*
  55 * Debugging.
  56 */
  57#if 0
  58#define DEBUG_AUTOCONF(fmt...)  printk(fmt)
  59#else
  60#define DEBUG_AUTOCONF(fmt...)  do { } while (0)
  61#endif
  62
  63#define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
  64
  65/*
  66 * Here we define the default xmit fifo size used for each type of UART.
  67 */
  68static const struct serial8250_config uart_config[] = {
  69        [PORT_UNKNOWN] = {
  70                .name           = "unknown",
  71                .fifo_size      = 1,
  72                .tx_loadsz      = 1,
  73        },
  74        [PORT_8250] = {
  75                .name           = "8250",
  76                .fifo_size      = 1,
  77                .tx_loadsz      = 1,
  78        },
  79        [PORT_16450] = {
  80                .name           = "16450",
  81                .fifo_size      = 1,
  82                .tx_loadsz      = 1,
  83        },
  84        [PORT_16550] = {
  85                .name           = "16550",
  86                .fifo_size      = 1,
  87                .tx_loadsz      = 1,
  88        },
  89        [PORT_16550A] = {
  90                .name           = "16550A",
  91                .fifo_size      = 16,
  92                .tx_loadsz      = 16,
  93                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
  94                                  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
  95                .rxtrig_bytes   = {1, 4, 8, 14},
  96                .flags          = UART_CAP_FIFO,
  97        },
  98        [PORT_CIRRUS] = {
  99                .name           = "Cirrus",
 100                .fifo_size      = 1,
 101                .tx_loadsz      = 1,
 102        },
 103        [PORT_16650] = {
 104                .name           = "ST16650",
 105                .fifo_size      = 1,
 106                .tx_loadsz      = 1,
 107                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 108        },
 109        [PORT_16650V2] = {
 110                .name           = "ST16650V2",
 111                .fifo_size      = 32,
 112                .tx_loadsz      = 16,
 113                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 114                                  UART_FCR_T_TRIG_00,
 115                .rxtrig_bytes   = {8, 16, 24, 28},
 116                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 117        },
 118        [PORT_16750] = {
 119                .name           = "TI16750",
 120                .fifo_size      = 64,
 121                .tx_loadsz      = 64,
 122                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 123                                  UART_FCR7_64BYTE,
 124                .rxtrig_bytes   = {1, 16, 32, 56},
 125                .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
 126        },
 127        [PORT_STARTECH] = {
 128                .name           = "Startech",
 129                .fifo_size      = 1,
 130                .tx_loadsz      = 1,
 131        },
 132        [PORT_16C950] = {
 133                .name           = "16C950/954",
 134                .fifo_size      = 128,
 135                .tx_loadsz      = 128,
 136                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 137                /* UART_CAP_EFR breaks billionon CF bluetooth card. */
 138                .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
 139        },
 140        [PORT_16654] = {
 141                .name           = "ST16654",
 142                .fifo_size      = 64,
 143                .tx_loadsz      = 32,
 144                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 145                                  UART_FCR_T_TRIG_10,
 146                .rxtrig_bytes   = {8, 16, 56, 60},
 147                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 148        },
 149        [PORT_16850] = {
 150                .name           = "XR16850",
 151                .fifo_size      = 128,
 152                .tx_loadsz      = 128,
 153                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 154                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 155        },
 156        [PORT_RSA] = {
 157                .name           = "RSA",
 158                .fifo_size      = 2048,
 159                .tx_loadsz      = 2048,
 160                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
 161                .flags          = UART_CAP_FIFO,
 162        },
 163        [PORT_NS16550A] = {
 164                .name           = "NS16550A",
 165                .fifo_size      = 16,
 166                .tx_loadsz      = 16,
 167                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 168                .flags          = UART_CAP_FIFO | UART_NATSEMI,
 169        },
 170        [PORT_XSCALE] = {
 171                .name           = "XScale",
 172                .fifo_size      = 32,
 173                .tx_loadsz      = 32,
 174                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 175                .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
 176        },
 177        [PORT_OCTEON] = {
 178                .name           = "OCTEON",
 179                .fifo_size      = 64,
 180                .tx_loadsz      = 64,
 181                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 182                .flags          = UART_CAP_FIFO,
 183        },
 184        [PORT_AR7] = {
 185                .name           = "AR7",
 186                .fifo_size      = 16,
 187                .tx_loadsz      = 16,
 188                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
 189                .flags          = UART_CAP_FIFO /* | UART_CAP_AFE */,
 190        },
 191        [PORT_U6_16550A] = {
 192                .name           = "U6_16550A",
 193                .fifo_size      = 64,
 194                .tx_loadsz      = 64,
 195                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 196                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 197        },
 198        [PORT_TEGRA] = {
 199                .name           = "Tegra",
 200                .fifo_size      = 32,
 201                .tx_loadsz      = 8,
 202                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 203                                  UART_FCR_T_TRIG_01,
 204                .rxtrig_bytes   = {1, 4, 8, 14},
 205                .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
 206        },
 207        [PORT_XR17D15X] = {
 208                .name           = "XR17D15X",
 209                .fifo_size      = 64,
 210                .tx_loadsz      = 64,
 211                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 212                .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
 213                                  UART_CAP_SLEEP,
 214        },
 215        [PORT_XR17V35X] = {
 216                .name           = "XR17V35X",
 217                .fifo_size      = 256,
 218                .tx_loadsz      = 256,
 219                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
 220                                  UART_FCR_T_TRIG_11,
 221                .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
 222                                  UART_CAP_SLEEP,
 223        },
 224        [PORT_LPC3220] = {
 225                .name           = "LPC3220",
 226                .fifo_size      = 64,
 227                .tx_loadsz      = 32,
 228                .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
 229                                  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
 230                .flags          = UART_CAP_FIFO,
 231        },
 232        [PORT_BRCM_TRUMANAGE] = {
 233                .name           = "TruManage",
 234                .fifo_size      = 1,
 235                .tx_loadsz      = 1024,
 236                .flags          = UART_CAP_HFIFO,
 237        },
 238        [PORT_8250_CIR] = {
 239                .name           = "CIR port"
 240        },
 241        [PORT_ALTR_16550_F32] = {
 242                .name           = "Altera 16550 FIFO32",
 243                .fifo_size      = 32,
 244                .tx_loadsz      = 32,
 245                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 246                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 247        },
 248        [PORT_ALTR_16550_F64] = {
 249                .name           = "Altera 16550 FIFO64",
 250                .fifo_size      = 64,
 251                .tx_loadsz      = 64,
 252                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 253                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 254        },
 255        [PORT_ALTR_16550_F128] = {
 256                .name           = "Altera 16550 FIFO128",
 257                .fifo_size      = 128,
 258                .tx_loadsz      = 128,
 259                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 260                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 261        },
 262        /*
 263         * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
 264         * workaround of errata A-008006 which states that tx_loadsz should
 265         * be configured less than Maximum supported fifo bytes.
 266         */
 267        [PORT_16550A_FSL64] = {
 268                .name           = "16550A_FSL64",
 269                .fifo_size      = 64,
 270                .tx_loadsz      = 63,
 271                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 272                                  UART_FCR7_64BYTE,
 273                .flags          = UART_CAP_FIFO,
 274        },
 275        [PORT_RT2880] = {
 276                .name           = "Palmchip BK-3103",
 277                .fifo_size      = 16,
 278                .tx_loadsz      = 16,
 279                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 280                .rxtrig_bytes   = {1, 4, 8, 14},
 281                .flags          = UART_CAP_FIFO,
 282        },
 283        [PORT_DA830] = {
 284                .name           = "TI DA8xx/66AK2x",
 285                .fifo_size      = 16,
 286                .tx_loadsz      = 16,
 287                .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
 288                                  UART_FCR_R_TRIG_10,
 289                .rxtrig_bytes   = {1, 4, 8, 14},
 290                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 291        },
 292        [PORT_MTK_BTIF] = {
 293                .name           = "MediaTek BTIF",
 294                .fifo_size      = 16,
 295                .tx_loadsz      = 16,
 296                .fcr            = UART_FCR_ENABLE_FIFO |
 297                                  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 298                .flags          = UART_CAP_FIFO,
 299        },
 300};
 301
 302/* Uart divisor latch read */
 303static int default_serial_dl_read(struct uart_8250_port *up)
 304{
 305        return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
 306}
 307
 308/* Uart divisor latch write */
 309static void default_serial_dl_write(struct uart_8250_port *up, int value)
 310{
 311        serial_out(up, UART_DLL, value & 0xff);
 312        serial_out(up, UART_DLM, value >> 8 & 0xff);
 313}
 314
 315#ifdef CONFIG_SERIAL_8250_RT288X
 316
 317/* Au1x00/RT288x UART hardware has a weird register layout */
 318static const s8 au_io_in_map[8] = {
 319         0,     /* UART_RX  */
 320         2,     /* UART_IER */
 321         3,     /* UART_IIR */
 322         5,     /* UART_LCR */
 323         6,     /* UART_MCR */
 324         7,     /* UART_LSR */
 325         8,     /* UART_MSR */
 326        -1,     /* UART_SCR (unmapped) */
 327};
 328
 329static const s8 au_io_out_map[8] = {
 330         1,     /* UART_TX  */
 331         2,     /* UART_IER */
 332         4,     /* UART_FCR */
 333         5,     /* UART_LCR */
 334         6,     /* UART_MCR */
 335        -1,     /* UART_LSR (unmapped) */
 336        -1,     /* UART_MSR (unmapped) */
 337        -1,     /* UART_SCR (unmapped) */
 338};
 339
 340unsigned int au_serial_in(struct uart_port *p, int offset)
 341{
 342        if (offset >= ARRAY_SIZE(au_io_in_map))
 343                return UINT_MAX;
 344        offset = au_io_in_map[offset];
 345        if (offset < 0)
 346                return UINT_MAX;
 347        return __raw_readl(p->membase + (offset << p->regshift));
 348}
 349
 350void au_serial_out(struct uart_port *p, int offset, int value)
 351{
 352        if (offset >= ARRAY_SIZE(au_io_out_map))
 353                return;
 354        offset = au_io_out_map[offset];
 355        if (offset < 0)
 356                return;
 357        __raw_writel(value, p->membase + (offset << p->regshift));
 358}
 359
 360/* Au1x00 haven't got a standard divisor latch */
 361static int au_serial_dl_read(struct uart_8250_port *up)
 362{
 363        return __raw_readl(up->port.membase + 0x28);
 364}
 365
 366static void au_serial_dl_write(struct uart_8250_port *up, int value)
 367{
 368        __raw_writel(value, up->port.membase + 0x28);
 369}
 370
 371#endif
 372
 373static unsigned int hub6_serial_in(struct uart_port *p, int offset)
 374{
 375        offset = offset << p->regshift;
 376        outb(p->hub6 - 1 + offset, p->iobase);
 377        return inb(p->iobase + 1);
 378}
 379
 380static void hub6_serial_out(struct uart_port *p, int offset, int value)
 381{
 382        offset = offset << p->regshift;
 383        outb(p->hub6 - 1 + offset, p->iobase);
 384        outb(value, p->iobase + 1);
 385}
 386
 387static unsigned int mem_serial_in(struct uart_port *p, int offset)
 388{
 389        offset = offset << p->regshift;
 390        return readb(p->membase + offset);
 391}
 392
 393static void mem_serial_out(struct uart_port *p, int offset, int value)
 394{
 395        offset = offset << p->regshift;
 396        writeb(value, p->membase + offset);
 397}
 398
 399static void mem16_serial_out(struct uart_port *p, int offset, int value)
 400{
 401        offset = offset << p->regshift;
 402        writew(value, p->membase + offset);
 403}
 404
 405static unsigned int mem16_serial_in(struct uart_port *p, int offset)
 406{
 407        offset = offset << p->regshift;
 408        return readw(p->membase + offset);
 409}
 410
 411static void mem32_serial_out(struct uart_port *p, int offset, int value)
 412{
 413        offset = offset << p->regshift;
 414        writel(value, p->membase + offset);
 415}
 416
 417static unsigned int mem32_serial_in(struct uart_port *p, int offset)
 418{
 419        offset = offset << p->regshift;
 420        return readl(p->membase + offset);
 421}
 422
 423static void mem32be_serial_out(struct uart_port *p, int offset, int value)
 424{
 425        offset = offset << p->regshift;
 426        iowrite32be(value, p->membase + offset);
 427}
 428
 429static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
 430{
 431        offset = offset << p->regshift;
 432        return ioread32be(p->membase + offset);
 433}
 434
 435static unsigned int io_serial_in(struct uart_port *p, int offset)
 436{
 437        offset = offset << p->regshift;
 438        return inb(p->iobase + offset);
 439}
 440
 441static void io_serial_out(struct uart_port *p, int offset, int value)
 442{
 443        offset = offset << p->regshift;
 444        outb(value, p->iobase + offset);
 445}
 446
 447static int serial8250_default_handle_irq(struct uart_port *port);
 448static int exar_handle_irq(struct uart_port *port);
 449
 450static void set_io_from_upio(struct uart_port *p)
 451{
 452        struct uart_8250_port *up = up_to_u8250p(p);
 453
 454        up->dl_read = default_serial_dl_read;
 455        up->dl_write = default_serial_dl_write;
 456
 457        switch (p->iotype) {
 458        case UPIO_HUB6:
 459                p->serial_in = hub6_serial_in;
 460                p->serial_out = hub6_serial_out;
 461                break;
 462
 463        case UPIO_MEM:
 464                p->serial_in = mem_serial_in;
 465                p->serial_out = mem_serial_out;
 466                break;
 467
 468        case UPIO_MEM16:
 469                p->serial_in = mem16_serial_in;
 470                p->serial_out = mem16_serial_out;
 471                break;
 472
 473        case UPIO_MEM32:
 474                p->serial_in = mem32_serial_in;
 475                p->serial_out = mem32_serial_out;
 476                break;
 477
 478        case UPIO_MEM32BE:
 479                p->serial_in = mem32be_serial_in;
 480                p->serial_out = mem32be_serial_out;
 481                break;
 482
 483#ifdef CONFIG_SERIAL_8250_RT288X
 484        case UPIO_AU:
 485                p->serial_in = au_serial_in;
 486                p->serial_out = au_serial_out;
 487                up->dl_read = au_serial_dl_read;
 488                up->dl_write = au_serial_dl_write;
 489                break;
 490#endif
 491
 492        default:
 493                p->serial_in = io_serial_in;
 494                p->serial_out = io_serial_out;
 495                break;
 496        }
 497        /* Remember loaded iotype */
 498        up->cur_iotype = p->iotype;
 499        p->handle_irq = serial8250_default_handle_irq;
 500}
 501
 502static void
 503serial_port_out_sync(struct uart_port *p, int offset, int value)
 504{
 505        switch (p->iotype) {
 506        case UPIO_MEM:
 507        case UPIO_MEM16:
 508        case UPIO_MEM32:
 509        case UPIO_MEM32BE:
 510        case UPIO_AU:
 511                p->serial_out(p, offset, value);
 512                p->serial_in(p, UART_LCR);      /* safe, no side-effects */
 513                break;
 514        default:
 515                p->serial_out(p, offset, value);
 516        }
 517}
 518
 519/*
 520 * For the 16C950
 521 */
 522static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
 523{
 524        serial_out(up, UART_SCR, offset);
 525        serial_out(up, UART_ICR, value);
 526}
 527
 528static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
 529{
 530        unsigned int value;
 531
 532        serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
 533        serial_out(up, UART_SCR, offset);
 534        value = serial_in(up, UART_ICR);
 535        serial_icr_write(up, UART_ACR, up->acr);
 536
 537        return value;
 538}
 539
 540/*
 541 * FIFO support.
 542 */
 543static void serial8250_clear_fifos(struct uart_8250_port *p)
 544{
 545        if (p->capabilities & UART_CAP_FIFO) {
 546                serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
 547                serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
 548                               UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 549                serial_out(p, UART_FCR, 0);
 550        }
 551}
 552
 553static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
 554{
 555        unsigned char mcr = serial8250_in_MCR(p);
 556
 557        if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
 558                mcr |= UART_MCR_RTS;
 559        else
 560                mcr &= ~UART_MCR_RTS;
 561        serial8250_out_MCR(p, mcr);
 562}
 563
 564static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
 565static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
 566
 567void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
 568{
 569        serial8250_clear_fifos(p);
 570        serial_out(p, UART_FCR, p->fcr);
 571}
 572EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
 573
 574void serial8250_rpm_get(struct uart_8250_port *p)
 575{
 576        if (!(p->capabilities & UART_CAP_RPM))
 577                return;
 578        pm_runtime_get_sync(p->port.dev);
 579}
 580EXPORT_SYMBOL_GPL(serial8250_rpm_get);
 581
 582void serial8250_rpm_put(struct uart_8250_port *p)
 583{
 584        if (!(p->capabilities & UART_CAP_RPM))
 585                return;
 586        pm_runtime_mark_last_busy(p->port.dev);
 587        pm_runtime_put_autosuspend(p->port.dev);
 588}
 589EXPORT_SYMBOL_GPL(serial8250_rpm_put);
 590
 591/**
 592 *      serial8250_em485_init() - put uart_8250_port into rs485 emulating
 593 *      @p:     uart_8250_port port instance
 594 *
 595 *      The function is used to start rs485 software emulating on the
 596 *      &struct uart_8250_port* @p. Namely, RTS is switched before/after
 597 *      transmission. The function is idempotent, so it is safe to call it
 598 *      multiple times.
 599 *
 600 *      The caller MUST enable interrupt on empty shift register before
 601 *      calling serial8250_em485_init(). This interrupt is not a part of
 602 *      8250 standard, but implementation defined.
 603 *
 604 *      The function is supposed to be called from .rs485_config callback
 605 *      or from any other callback protected with p->port.lock spinlock.
 606 *
 607 *      See also serial8250_em485_destroy()
 608 *
 609 *      Return 0 - success, -errno - otherwise
 610 */
 611int serial8250_em485_init(struct uart_8250_port *p)
 612{
 613        if (p->em485)
 614                return 0;
 615
 616        p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
 617        if (!p->em485)
 618                return -ENOMEM;
 619
 620        hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
 621                     HRTIMER_MODE_REL);
 622        hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
 623                     HRTIMER_MODE_REL);
 624        p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
 625        p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
 626        p->em485->port = p;
 627        p->em485->active_timer = NULL;
 628        serial8250_em485_rts_after_send(p);
 629
 630        return 0;
 631}
 632EXPORT_SYMBOL_GPL(serial8250_em485_init);
 633
 634/**
 635 *      serial8250_em485_destroy() - put uart_8250_port into normal state
 636 *      @p:     uart_8250_port port instance
 637 *
 638 *      The function is used to stop rs485 software emulating on the
 639 *      &struct uart_8250_port* @p. The function is idempotent, so it is safe to
 640 *      call it multiple times.
 641 *
 642 *      The function is supposed to be called from .rs485_config callback
 643 *      or from any other callback protected with p->port.lock spinlock.
 644 *
 645 *      See also serial8250_em485_init()
 646 */
 647void serial8250_em485_destroy(struct uart_8250_port *p)
 648{
 649        if (!p->em485)
 650                return;
 651
 652        hrtimer_cancel(&p->em485->start_tx_timer);
 653        hrtimer_cancel(&p->em485->stop_tx_timer);
 654
 655        kfree(p->em485);
 656        p->em485 = NULL;
 657}
 658EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
 659
 660/*
 661 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
 662 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
 663 * empty and the HW can idle again.
 664 */
 665void serial8250_rpm_get_tx(struct uart_8250_port *p)
 666{
 667        unsigned char rpm_active;
 668
 669        if (!(p->capabilities & UART_CAP_RPM))
 670                return;
 671
 672        rpm_active = xchg(&p->rpm_tx_active, 1);
 673        if (rpm_active)
 674                return;
 675        pm_runtime_get_sync(p->port.dev);
 676}
 677EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
 678
 679void serial8250_rpm_put_tx(struct uart_8250_port *p)
 680{
 681        unsigned char rpm_active;
 682
 683        if (!(p->capabilities & UART_CAP_RPM))
 684                return;
 685
 686        rpm_active = xchg(&p->rpm_tx_active, 0);
 687        if (!rpm_active)
 688                return;
 689        pm_runtime_mark_last_busy(p->port.dev);
 690        pm_runtime_put_autosuspend(p->port.dev);
 691}
 692EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
 693
 694/*
 695 * IER sleep support.  UARTs which have EFRs need the "extended
 696 * capability" bit enabled.  Note that on XR16C850s, we need to
 697 * reset LCR to write to IER.
 698 */
 699static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
 700{
 701        unsigned char lcr = 0, efr = 0;
 702        /*
 703         * Exar UARTs have a SLEEP register that enables or disables
 704         * each UART to enter sleep mode separately.  On the XR17V35x the
 705         * register is accessible to each UART at the UART_EXAR_SLEEP
 706         * offset but the UART channel may only write to the corresponding
 707         * bit.
 708         */
 709        serial8250_rpm_get(p);
 710        if ((p->port.type == PORT_XR17V35X) ||
 711           (p->port.type == PORT_XR17D15X)) {
 712                serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
 713                goto out;
 714        }
 715
 716        if (p->capabilities & UART_CAP_SLEEP) {
 717                if (p->capabilities & UART_CAP_EFR) {
 718                        lcr = serial_in(p, UART_LCR);
 719                        efr = serial_in(p, UART_EFR);
 720                        serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
 721                        serial_out(p, UART_EFR, UART_EFR_ECB);
 722                        serial_out(p, UART_LCR, 0);
 723                }
 724                serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
 725                if (p->capabilities & UART_CAP_EFR) {
 726                        serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
 727                        serial_out(p, UART_EFR, efr);
 728                        serial_out(p, UART_LCR, lcr);
 729                }
 730        }
 731out:
 732        serial8250_rpm_put(p);
 733}
 734
 735#ifdef CONFIG_SERIAL_8250_RSA
 736/*
 737 * Attempts to turn on the RSA FIFO.  Returns zero on failure.
 738 * We set the port uart clock rate if we succeed.
 739 */
 740static int __enable_rsa(struct uart_8250_port *up)
 741{
 742        unsigned char mode;
 743        int result;
 744
 745        mode = serial_in(up, UART_RSA_MSR);
 746        result = mode & UART_RSA_MSR_FIFO;
 747
 748        if (!result) {
 749                serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
 750                mode = serial_in(up, UART_RSA_MSR);
 751                result = mode & UART_RSA_MSR_FIFO;
 752        }
 753
 754        if (result)
 755                up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
 756
 757        return result;
 758}
 759
 760static void enable_rsa(struct uart_8250_port *up)
 761{
 762        if (up->port.type == PORT_RSA) {
 763                if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
 764                        spin_lock_irq(&up->port.lock);
 765                        __enable_rsa(up);
 766                        spin_unlock_irq(&up->port.lock);
 767                }
 768                if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
 769                        serial_out(up, UART_RSA_FRR, 0);
 770        }
 771}
 772
 773/*
 774 * Attempts to turn off the RSA FIFO.  Returns zero on failure.
 775 * It is unknown why interrupts were disabled in here.  However,
 776 * the caller is expected to preserve this behaviour by grabbing
 777 * the spinlock before calling this function.
 778 */
 779static void disable_rsa(struct uart_8250_port *up)
 780{
 781        unsigned char mode;
 782        int result;
 783
 784        if (up->port.type == PORT_RSA &&
 785            up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
 786                spin_lock_irq(&up->port.lock);
 787
 788                mode = serial_in(up, UART_RSA_MSR);
 789                result = !(mode & UART_RSA_MSR_FIFO);
 790
 791                if (!result) {
 792                        serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
 793                        mode = serial_in(up, UART_RSA_MSR);
 794                        result = !(mode & UART_RSA_MSR_FIFO);
 795                }
 796
 797                if (result)
 798                        up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
 799                spin_unlock_irq(&up->port.lock);
 800        }
 801}
 802#endif /* CONFIG_SERIAL_8250_RSA */
 803
 804/*
 805 * This is a quickie test to see how big the FIFO is.
 806 * It doesn't work at all the time, more's the pity.
 807 */
 808static int size_fifo(struct uart_8250_port *up)
 809{
 810        unsigned char old_fcr, old_mcr, old_lcr;
 811        unsigned short old_dl;
 812        int count;
 813
 814        old_lcr = serial_in(up, UART_LCR);
 815        serial_out(up, UART_LCR, 0);
 816        old_fcr = serial_in(up, UART_FCR);
 817        old_mcr = serial8250_in_MCR(up);
 818        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 819                    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 820        serial8250_out_MCR(up, UART_MCR_LOOP);
 821        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 822        old_dl = serial_dl_read(up);
 823        serial_dl_write(up, 0x0001);
 824        serial_out(up, UART_LCR, 0x03);
 825        for (count = 0; count < 256; count++)
 826                serial_out(up, UART_TX, count);
 827        mdelay(20);/* FIXME - schedule_timeout */
 828        for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
 829             (count < 256); count++)
 830                serial_in(up, UART_RX);
 831        serial_out(up, UART_FCR, old_fcr);
 832        serial8250_out_MCR(up, old_mcr);
 833        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 834        serial_dl_write(up, old_dl);
 835        serial_out(up, UART_LCR, old_lcr);
 836
 837        return count;
 838}
 839
 840/*
 841 * Read UART ID using the divisor method - set DLL and DLM to zero
 842 * and the revision will be in DLL and device type in DLM.  We
 843 * preserve the device state across this.
 844 */
 845static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
 846{
 847        unsigned char old_lcr;
 848        unsigned int id, old_dl;
 849
 850        old_lcr = serial_in(p, UART_LCR);
 851        serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
 852        old_dl = serial_dl_read(p);
 853        serial_dl_write(p, 0);
 854        id = serial_dl_read(p);
 855        serial_dl_write(p, old_dl);
 856
 857        serial_out(p, UART_LCR, old_lcr);
 858
 859        return id;
 860}
 861
 862/*
 863 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
 864 * When this function is called we know it is at least a StarTech
 865 * 16650 V2, but it might be one of several StarTech UARTs, or one of
 866 * its clones.  (We treat the broken original StarTech 16650 V1 as a
 867 * 16550, and why not?  Startech doesn't seem to even acknowledge its
 868 * existence.)
 869 *
 870 * What evil have men's minds wrought...
 871 */
 872static void autoconfig_has_efr(struct uart_8250_port *up)
 873{
 874        unsigned int id1, id2, id3, rev;
 875
 876        /*
 877         * Everything with an EFR has SLEEP
 878         */
 879        up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
 880
 881        /*
 882         * First we check to see if it's an Oxford Semiconductor UART.
 883         *
 884         * If we have to do this here because some non-National
 885         * Semiconductor clone chips lock up if you try writing to the
 886         * LSR register (which serial_icr_read does)
 887         */
 888
 889        /*
 890         * Check for Oxford Semiconductor 16C950.
 891         *
 892         * EFR [4] must be set else this test fails.
 893         *
 894         * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
 895         * claims that it's needed for 952 dual UART's (which are not
 896         * recommended for new designs).
 897         */
 898        up->acr = 0;
 899        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 900        serial_out(up, UART_EFR, UART_EFR_ECB);
 901        serial_out(up, UART_LCR, 0x00);
 902        id1 = serial_icr_read(up, UART_ID1);
 903        id2 = serial_icr_read(up, UART_ID2);
 904        id3 = serial_icr_read(up, UART_ID3);
 905        rev = serial_icr_read(up, UART_REV);
 906
 907        DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
 908
 909        if (id1 == 0x16 && id2 == 0xC9 &&
 910            (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
 911                up->port.type = PORT_16C950;
 912
 913                /*
 914                 * Enable work around for the Oxford Semiconductor 952 rev B
 915                 * chip which causes it to seriously miscalculate baud rates
 916                 * when DLL is 0.
 917                 */
 918                if (id3 == 0x52 && rev == 0x01)
 919                        up->bugs |= UART_BUG_QUOT;
 920                return;
 921        }
 922
 923        /*
 924         * We check for a XR16C850 by setting DLL and DLM to 0, and then
 925         * reading back DLL and DLM.  The chip type depends on the DLM
 926         * value read back:
 927         *  0x10 - XR16C850 and the DLL contains the chip revision.
 928         *  0x12 - XR16C2850.
 929         *  0x14 - XR16C854.
 930         */
 931        id1 = autoconfig_read_divisor_id(up);
 932        DEBUG_AUTOCONF("850id=%04x ", id1);
 933
 934        id2 = id1 >> 8;
 935        if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
 936                up->port.type = PORT_16850;
 937                return;
 938        }
 939
 940        /*
 941         * It wasn't an XR16C850.
 942         *
 943         * We distinguish between the '654 and the '650 by counting
 944         * how many bytes are in the FIFO.  I'm using this for now,
 945         * since that's the technique that was sent to me in the
 946         * serial driver update, but I'm not convinced this works.
 947         * I've had problems doing this in the past.  -TYT
 948         */
 949        if (size_fifo(up) == 64)
 950                up->port.type = PORT_16654;
 951        else
 952                up->port.type = PORT_16650V2;
 953}
 954
 955/*
 956 * We detected a chip without a FIFO.  Only two fall into
 957 * this category - the original 8250 and the 16450.  The
 958 * 16450 has a scratch register (accessible with LCR=0)
 959 */
 960static void autoconfig_8250(struct uart_8250_port *up)
 961{
 962        unsigned char scratch, status1, status2;
 963
 964        up->port.type = PORT_8250;
 965
 966        scratch = serial_in(up, UART_SCR);
 967        serial_out(up, UART_SCR, 0xa5);
 968        status1 = serial_in(up, UART_SCR);
 969        serial_out(up, UART_SCR, 0x5a);
 970        status2 = serial_in(up, UART_SCR);
 971        serial_out(up, UART_SCR, scratch);
 972
 973        if (status1 == 0xa5 && status2 == 0x5a)
 974                up->port.type = PORT_16450;
 975}
 976
 977static int broken_efr(struct uart_8250_port *up)
 978{
 979        /*
 980         * Exar ST16C2550 "A2" devices incorrectly detect as
 981         * having an EFR, and report an ID of 0x0201.  See
 982         * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
 983         */
 984        if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
 985                return 1;
 986
 987        return 0;
 988}
 989
 990/*
 991 * We know that the chip has FIFOs.  Does it have an EFR?  The
 992 * EFR is located in the same register position as the IIR and
 993 * we know the top two bits of the IIR are currently set.  The
 994 * EFR should contain zero.  Try to read the EFR.
 995 */
 996static void autoconfig_16550a(struct uart_8250_port *up)
 997{
 998        unsigned char status1, status2;
 999        unsigned int iersave;
1000
1001        up->port.type = PORT_16550A;
1002        up->capabilities |= UART_CAP_FIFO;
1003
1004        /*
1005         * XR17V35x UARTs have an extra divisor register, DLD
1006         * that gets enabled with when DLAB is set which will
1007         * cause the device to incorrectly match and assign
1008         * port type to PORT_16650.  The EFR for this UART is
1009         * found at offset 0x09. Instead check the Deice ID (DVID)
1010         * register for a 2, 4 or 8 port UART.
1011         */
1012        if (up->port.flags & UPF_EXAR_EFR) {
1013                status1 = serial_in(up, UART_EXAR_DVID);
1014                if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1015                        DEBUG_AUTOCONF("Exar XR17V35x ");
1016                        up->port.type = PORT_XR17V35X;
1017                        up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1018                                                UART_CAP_SLEEP;
1019
1020                        return;
1021                }
1022
1023        }
1024
1025        /*
1026         * Check for presence of the EFR when DLAB is set.
1027         * Only ST16C650V1 UARTs pass this test.
1028         */
1029        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1030        if (serial_in(up, UART_EFR) == 0) {
1031                serial_out(up, UART_EFR, 0xA8);
1032                if (serial_in(up, UART_EFR) != 0) {
1033                        DEBUG_AUTOCONF("EFRv1 ");
1034                        up->port.type = PORT_16650;
1035                        up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1036                } else {
1037                        serial_out(up, UART_LCR, 0);
1038                        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1039                                   UART_FCR7_64BYTE);
1040                        status1 = serial_in(up, UART_IIR) >> 5;
1041                        serial_out(up, UART_FCR, 0);
1042                        serial_out(up, UART_LCR, 0);
1043
1044                        if (status1 == 7)
1045                                up->port.type = PORT_16550A_FSL64;
1046                        else
1047                                DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1048                }
1049                serial_out(up, UART_EFR, 0);
1050                return;
1051        }
1052
1053        /*
1054         * Maybe it requires 0xbf to be written to the LCR.
1055         * (other ST16C650V2 UARTs, TI16C752A, etc)
1056         */
1057        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1058        if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1059                DEBUG_AUTOCONF("EFRv2 ");
1060                autoconfig_has_efr(up);
1061                return;
1062        }
1063
1064        /*
1065         * Check for a National Semiconductor SuperIO chip.
1066         * Attempt to switch to bank 2, read the value of the LOOP bit
1067         * from EXCR1. Switch back to bank 0, change it in MCR. Then
1068         * switch back to bank 2, read it from EXCR1 again and check
1069         * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1070         */
1071        serial_out(up, UART_LCR, 0);
1072        status1 = serial8250_in_MCR(up);
1073        serial_out(up, UART_LCR, 0xE0);
1074        status2 = serial_in(up, 0x02); /* EXCR1 */
1075
1076        if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1077                serial_out(up, UART_LCR, 0);
1078                serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1079                serial_out(up, UART_LCR, 0xE0);
1080                status2 = serial_in(up, 0x02); /* EXCR1 */
1081                serial_out(up, UART_LCR, 0);
1082                serial8250_out_MCR(up, status1);
1083
1084                if ((status2 ^ status1) & UART_MCR_LOOP) {
1085                        unsigned short quot;
1086
1087                        serial_out(up, UART_LCR, 0xE0);
1088
1089                        quot = serial_dl_read(up);
1090                        quot <<= 3;
1091
1092                        if (ns16550a_goto_highspeed(up))
1093                                serial_dl_write(up, quot);
1094
1095                        serial_out(up, UART_LCR, 0);
1096
1097                        up->port.uartclk = 921600*16;
1098                        up->port.type = PORT_NS16550A;
1099                        up->capabilities |= UART_NATSEMI;
1100                        return;
1101                }
1102        }
1103
1104        /*
1105         * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1106         * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1107         * Try setting it with and without DLAB set.  Cheap clones
1108         * set bit 5 without DLAB set.
1109         */
1110        serial_out(up, UART_LCR, 0);
1111        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1112        status1 = serial_in(up, UART_IIR) >> 5;
1113        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1114        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1115        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1116        status2 = serial_in(up, UART_IIR) >> 5;
1117        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1118        serial_out(up, UART_LCR, 0);
1119
1120        DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1121
1122        if (status1 == 6 && status2 == 7) {
1123                up->port.type = PORT_16750;
1124                up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1125                return;
1126        }
1127
1128        /*
1129         * Try writing and reading the UART_IER_UUE bit (b6).
1130         * If it works, this is probably one of the Xscale platform's
1131         * internal UARTs.
1132         * We're going to explicitly set the UUE bit to 0 before
1133         * trying to write and read a 1 just to make sure it's not
1134         * already a 1 and maybe locked there before we even start start.
1135         */
1136        iersave = serial_in(up, UART_IER);
1137        serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1138        if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1139                /*
1140                 * OK it's in a known zero state, try writing and reading
1141                 * without disturbing the current state of the other bits.
1142                 */
1143                serial_out(up, UART_IER, iersave | UART_IER_UUE);
1144                if (serial_in(up, UART_IER) & UART_IER_UUE) {
1145                        /*
1146                         * It's an Xscale.
1147                         * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1148                         */
1149                        DEBUG_AUTOCONF("Xscale ");
1150                        up->port.type = PORT_XSCALE;
1151                        up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1152                        return;
1153                }
1154        } else {
1155                /*
1156                 * If we got here we couldn't force the IER_UUE bit to 0.
1157                 * Log it and continue.
1158                 */
1159                DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1160        }
1161        serial_out(up, UART_IER, iersave);
1162
1163        /*
1164         * Exar uarts have EFR in a weird location
1165         */
1166        if (up->port.flags & UPF_EXAR_EFR) {
1167                DEBUG_AUTOCONF("Exar XR17D15x ");
1168                up->port.type = PORT_XR17D15X;
1169                up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1170                                    UART_CAP_SLEEP;
1171
1172                return;
1173        }
1174
1175        /*
1176         * We distinguish between 16550A and U6 16550A by counting
1177         * how many bytes are in the FIFO.
1178         */
1179        if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1180                up->port.type = PORT_U6_16550A;
1181                up->capabilities |= UART_CAP_AFE;
1182        }
1183}
1184
1185/*
1186 * This routine is called by rs_init() to initialize a specific serial
1187 * port.  It determines what type of UART chip this serial port is
1188 * using: 8250, 16450, 16550, 16550A.  The important question is
1189 * whether or not this UART is a 16550A or not, since this will
1190 * determine whether or not we can use its FIFO features or not.
1191 */
1192static void autoconfig(struct uart_8250_port *up)
1193{
1194        unsigned char status1, scratch, scratch2, scratch3;
1195        unsigned char save_lcr, save_mcr;
1196        struct uart_port *port = &up->port;
1197        unsigned long flags;
1198        unsigned int old_capabilities;
1199
1200        if (!port->iobase && !port->mapbase && !port->membase)
1201                return;
1202
1203        DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1204                       serial_index(port), port->iobase, port->membase);
1205
1206        /*
1207         * We really do need global IRQs disabled here - we're going to
1208         * be frobbing the chips IRQ enable register to see if it exists.
1209         */
1210        spin_lock_irqsave(&port->lock, flags);
1211
1212        up->capabilities = 0;
1213        up->bugs = 0;
1214
1215        if (!(port->flags & UPF_BUGGY_UART)) {
1216                /*
1217                 * Do a simple existence test first; if we fail this,
1218                 * there's no point trying anything else.
1219                 *
1220                 * 0x80 is used as a nonsense port to prevent against
1221                 * false positives due to ISA bus float.  The
1222                 * assumption is that 0x80 is a non-existent port;
1223                 * which should be safe since include/asm/io.h also
1224                 * makes this assumption.
1225                 *
1226                 * Note: this is safe as long as MCR bit 4 is clear
1227                 * and the device is in "PC" mode.
1228                 */
1229                scratch = serial_in(up, UART_IER);
1230                serial_out(up, UART_IER, 0);
1231#ifdef __i386__
1232                outb(0xff, 0x080);
1233#endif
1234                /*
1235                 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1236                 * 16C754B) allow only to modify them if an EFR bit is set.
1237                 */
1238                scratch2 = serial_in(up, UART_IER) & 0x0f;
1239                serial_out(up, UART_IER, 0x0F);
1240#ifdef __i386__
1241                outb(0, 0x080);
1242#endif
1243                scratch3 = serial_in(up, UART_IER) & 0x0f;
1244                serial_out(up, UART_IER, scratch);
1245                if (scratch2 != 0 || scratch3 != 0x0F) {
1246                        /*
1247                         * We failed; there's nothing here
1248                         */
1249                        spin_unlock_irqrestore(&port->lock, flags);
1250                        DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1251                                       scratch2, scratch3);
1252                        goto out;
1253                }
1254        }
1255
1256        save_mcr = serial8250_in_MCR(up);
1257        save_lcr = serial_in(up, UART_LCR);
1258
1259        /*
1260         * Check to see if a UART is really there.  Certain broken
1261         * internal modems based on the Rockwell chipset fail this
1262         * test, because they apparently don't implement the loopback
1263         * test mode.  So this test is skipped on the COM 1 through
1264         * COM 4 ports.  This *should* be safe, since no board
1265         * manufacturer would be stupid enough to design a board
1266         * that conflicts with COM 1-4 --- we hope!
1267         */
1268        if (!(port->flags & UPF_SKIP_TEST)) {
1269                serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1270                status1 = serial_in(up, UART_MSR) & 0xF0;
1271                serial8250_out_MCR(up, save_mcr);
1272                if (status1 != 0x90) {
1273                        spin_unlock_irqrestore(&port->lock, flags);
1274                        DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1275                                       status1);
1276                        goto out;
1277                }
1278        }
1279
1280        /*
1281         * We're pretty sure there's a port here.  Lets find out what
1282         * type of port it is.  The IIR top two bits allows us to find
1283         * out if it's 8250 or 16450, 16550, 16550A or later.  This
1284         * determines what we test for next.
1285         *
1286         * We also initialise the EFR (if any) to zero for later.  The
1287         * EFR occupies the same register location as the FCR and IIR.
1288         */
1289        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1290        serial_out(up, UART_EFR, 0);
1291        serial_out(up, UART_LCR, 0);
1292
1293        serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1294        scratch = serial_in(up, UART_IIR) >> 6;
1295
1296        switch (scratch) {
1297        case 0:
1298                autoconfig_8250(up);
1299                break;
1300        case 1:
1301                port->type = PORT_UNKNOWN;
1302                break;
1303        case 2:
1304                port->type = PORT_16550;
1305                break;
1306        case 3:
1307                autoconfig_16550a(up);
1308                break;
1309        }
1310
1311#ifdef CONFIG_SERIAL_8250_RSA
1312        /*
1313         * Only probe for RSA ports if we got the region.
1314         */
1315        if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1316            __enable_rsa(up))
1317                port->type = PORT_RSA;
1318#endif
1319
1320        serial_out(up, UART_LCR, save_lcr);
1321
1322        port->fifosize = uart_config[up->port.type].fifo_size;
1323        old_capabilities = up->capabilities;
1324        up->capabilities = uart_config[port->type].flags;
1325        up->tx_loadsz = uart_config[port->type].tx_loadsz;
1326
1327        if (port->type == PORT_UNKNOWN)
1328                goto out_lock;
1329
1330        /*
1331         * Reset the UART.
1332         */
1333#ifdef CONFIG_SERIAL_8250_RSA
1334        if (port->type == PORT_RSA)
1335                serial_out(up, UART_RSA_FRR, 0);
1336#endif
1337        serial8250_out_MCR(up, save_mcr);
1338        serial8250_clear_fifos(up);
1339        serial_in(up, UART_RX);
1340        if (up->capabilities & UART_CAP_UUE)
1341                serial_out(up, UART_IER, UART_IER_UUE);
1342        else
1343                serial_out(up, UART_IER, 0);
1344
1345out_lock:
1346        spin_unlock_irqrestore(&port->lock, flags);
1347
1348        /*
1349         * Check if the device is a Fintek F81216A
1350         */
1351        if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1352                fintek_8250_probe(up);
1353
1354        if (up->capabilities != old_capabilities) {
1355                pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1356                       serial_index(port), old_capabilities,
1357                       up->capabilities);
1358        }
1359out:
1360        DEBUG_AUTOCONF("iir=%d ", scratch);
1361        DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1362}
1363
1364static void autoconfig_irq(struct uart_8250_port *up)
1365{
1366        struct uart_port *port = &up->port;
1367        unsigned char save_mcr, save_ier;
1368        unsigned char save_ICP = 0;
1369        unsigned int ICP = 0;
1370        unsigned long irqs;
1371        int irq;
1372
1373        if (port->flags & UPF_FOURPORT) {
1374                ICP = (port->iobase & 0xfe0) | 0x1f;
1375                save_ICP = inb_p(ICP);
1376                outb_p(0x80, ICP);
1377                inb_p(ICP);
1378        }
1379
1380        if (uart_console(port))
1381                console_lock();
1382
1383        /* forget possible initially masked and pending IRQ */
1384        probe_irq_off(probe_irq_on());
1385        save_mcr = serial8250_in_MCR(up);
1386        save_ier = serial_in(up, UART_IER);
1387        serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1388
1389        irqs = probe_irq_on();
1390        serial8250_out_MCR(up, 0);
1391        udelay(10);
1392        if (port->flags & UPF_FOURPORT) {
1393                serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1394        } else {
1395                serial8250_out_MCR(up,
1396                        UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1397        }
1398        serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1399        serial_in(up, UART_LSR);
1400        serial_in(up, UART_RX);
1401        serial_in(up, UART_IIR);
1402        serial_in(up, UART_MSR);
1403        serial_out(up, UART_TX, 0xFF);
1404        udelay(20);
1405        irq = probe_irq_off(irqs);
1406
1407        serial8250_out_MCR(up, save_mcr);
1408        serial_out(up, UART_IER, save_ier);
1409
1410        if (port->flags & UPF_FOURPORT)
1411                outb_p(save_ICP, ICP);
1412
1413        if (uart_console(port))
1414                console_unlock();
1415
1416        port->irq = (irq > 0) ? irq : 0;
1417}
1418
1419static void serial8250_stop_rx(struct uart_port *port)
1420{
1421        struct uart_8250_port *up = up_to_u8250p(port);
1422
1423        serial8250_rpm_get(up);
1424
1425        up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1426        up->port.read_status_mask &= ~UART_LSR_DR;
1427        serial_port_out(port, UART_IER, up->ier);
1428
1429        serial8250_rpm_put(up);
1430}
1431
1432static void __do_stop_tx_rs485(struct uart_8250_port *p)
1433{
1434        serial8250_em485_rts_after_send(p);
1435
1436        /*
1437         * Empty the RX FIFO, we are not interested in anything
1438         * received during the half-duplex transmission.
1439         * Enable previously disabled RX interrupts.
1440         */
1441        if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1442                serial8250_clear_and_reinit_fifos(p);
1443
1444                p->ier |= UART_IER_RLSI | UART_IER_RDI;
1445                serial_port_out(&p->port, UART_IER, p->ier);
1446        }
1447}
1448static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1449{
1450        struct uart_8250_em485 *em485;
1451        struct uart_8250_port *p;
1452        unsigned long flags;
1453
1454        em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1455        p = em485->port;
1456
1457        serial8250_rpm_get(p);
1458        spin_lock_irqsave(&p->port.lock, flags);
1459        if (em485->active_timer == &em485->stop_tx_timer) {
1460                __do_stop_tx_rs485(p);
1461                em485->active_timer = NULL;
1462        }
1463        spin_unlock_irqrestore(&p->port.lock, flags);
1464        serial8250_rpm_put(p);
1465        return HRTIMER_NORESTART;
1466}
1467
1468static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1469{
1470        long sec = msec / 1000;
1471        long nsec = (msec % 1000) * 1000000;
1472        ktime_t t = ktime_set(sec, nsec);
1473
1474        hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1475}
1476
1477static void __stop_tx_rs485(struct uart_8250_port *p)
1478{
1479        struct uart_8250_em485 *em485 = p->em485;
1480
1481        /*
1482         * __do_stop_tx_rs485 is going to set RTS according to config
1483         * AND flush RX FIFO if required.
1484         */
1485        if (p->port.rs485.delay_rts_after_send > 0) {
1486                em485->active_timer = &em485->stop_tx_timer;
1487                start_hrtimer_ms(&em485->stop_tx_timer,
1488                                   p->port.rs485.delay_rts_after_send);
1489        } else {
1490                __do_stop_tx_rs485(p);
1491        }
1492}
1493
1494static inline void __do_stop_tx(struct uart_8250_port *p)
1495{
1496        if (p->ier & UART_IER_THRI) {
1497                p->ier &= ~UART_IER_THRI;
1498                serial_out(p, UART_IER, p->ier);
1499                serial8250_rpm_put_tx(p);
1500        }
1501}
1502
1503static inline void __stop_tx(struct uart_8250_port *p)
1504{
1505        struct uart_8250_em485 *em485 = p->em485;
1506
1507        if (em485) {
1508                unsigned char lsr = serial_in(p, UART_LSR);
1509                /*
1510                 * To provide required timeing and allow FIFO transfer,
1511                 * __stop_tx_rs485() must be called only when both FIFO and
1512                 * shift register are empty. It is for device driver to enable
1513                 * interrupt on TEMT.
1514                 */
1515                if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1516                        return;
1517
1518                em485->active_timer = NULL;
1519                hrtimer_cancel(&em485->start_tx_timer);
1520
1521                __stop_tx_rs485(p);
1522        }
1523        __do_stop_tx(p);
1524}
1525
1526static void serial8250_stop_tx(struct uart_port *port)
1527{
1528        struct uart_8250_port *up = up_to_u8250p(port);
1529
1530        serial8250_rpm_get(up);
1531        __stop_tx(up);
1532
1533        /*
1534         * We really want to stop the transmitter from sending.
1535         */
1536        if (port->type == PORT_16C950) {
1537                up->acr |= UART_ACR_TXDIS;
1538                serial_icr_write(up, UART_ACR, up->acr);
1539        }
1540        serial8250_rpm_put(up);
1541}
1542
1543static inline void __start_tx(struct uart_port *port)
1544{
1545        struct uart_8250_port *up = up_to_u8250p(port);
1546
1547        if (up->dma && !up->dma->tx_dma(up))
1548                return;
1549
1550        if (!(up->ier & UART_IER_THRI)) {
1551                up->ier |= UART_IER_THRI;
1552                serial_port_out(port, UART_IER, up->ier);
1553
1554                if (up->bugs & UART_BUG_TXEN) {
1555                        unsigned char lsr;
1556
1557                        lsr = serial_in(up, UART_LSR);
1558                        up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1559                        if (lsr & UART_LSR_THRE)
1560                                serial8250_tx_chars(up);
1561                }
1562        }
1563
1564        /*
1565         * Re-enable the transmitter if we disabled it.
1566         */
1567        if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1568                up->acr &= ~UART_ACR_TXDIS;
1569                serial_icr_write(up, UART_ACR, up->acr);
1570        }
1571}
1572
1573static inline void start_tx_rs485(struct uart_port *port)
1574{
1575        struct uart_8250_port *up = up_to_u8250p(port);
1576        struct uart_8250_em485 *em485 = up->em485;
1577        unsigned char mcr;
1578
1579        if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1580                serial8250_stop_rx(&up->port);
1581
1582        em485->active_timer = NULL;
1583        if (hrtimer_is_queued(&em485->stop_tx_timer))
1584                hrtimer_cancel(&em485->stop_tx_timer);
1585
1586        mcr = serial8250_in_MCR(up);
1587        if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1588            !!(mcr & UART_MCR_RTS)) {
1589                if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1590                        mcr |= UART_MCR_RTS;
1591                else
1592                        mcr &= ~UART_MCR_RTS;
1593                serial8250_out_MCR(up, mcr);
1594
1595                if (up->port.rs485.delay_rts_before_send > 0) {
1596                        em485->active_timer = &em485->start_tx_timer;
1597                        start_hrtimer_ms(&em485->start_tx_timer,
1598                                         up->port.rs485.delay_rts_before_send);
1599                        return;
1600                }
1601        }
1602
1603        __start_tx(port);
1604}
1605
1606static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1607{
1608        struct uart_8250_em485 *em485;
1609        struct uart_8250_port *p;
1610        unsigned long flags;
1611
1612        em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1613        p = em485->port;
1614
1615        spin_lock_irqsave(&p->port.lock, flags);
1616        if (em485->active_timer == &em485->start_tx_timer) {
1617                __start_tx(&p->port);
1618                em485->active_timer = NULL;
1619        }
1620        spin_unlock_irqrestore(&p->port.lock, flags);
1621        return HRTIMER_NORESTART;
1622}
1623
1624static void serial8250_start_tx(struct uart_port *port)
1625{
1626        struct uart_8250_port *up = up_to_u8250p(port);
1627        struct uart_8250_em485 *em485 = up->em485;
1628
1629        serial8250_rpm_get_tx(up);
1630
1631        if (em485 &&
1632            em485->active_timer == &em485->start_tx_timer)
1633                return;
1634
1635        if (em485)
1636                start_tx_rs485(port);
1637        else
1638                __start_tx(port);
1639}
1640
1641static void serial8250_throttle(struct uart_port *port)
1642{
1643        port->throttle(port);
1644}
1645
1646static void serial8250_unthrottle(struct uart_port *port)
1647{
1648        port->unthrottle(port);
1649}
1650
1651static void serial8250_disable_ms(struct uart_port *port)
1652{
1653        struct uart_8250_port *up = up_to_u8250p(port);
1654
1655        /* no MSR capabilities */
1656        if (up->bugs & UART_BUG_NOMSR)
1657                return;
1658
1659        up->ier &= ~UART_IER_MSI;
1660        serial_port_out(port, UART_IER, up->ier);
1661}
1662
1663static void serial8250_enable_ms(struct uart_port *port)
1664{
1665        struct uart_8250_port *up = up_to_u8250p(port);
1666
1667        /* no MSR capabilities */
1668        if (up->bugs & UART_BUG_NOMSR)
1669                return;
1670
1671        up->ier |= UART_IER_MSI;
1672
1673        serial8250_rpm_get(up);
1674        serial_port_out(port, UART_IER, up->ier);
1675        serial8250_rpm_put(up);
1676}
1677
1678static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1679{
1680        struct uart_port *port = &up->port;
1681        unsigned char ch;
1682        char flag = TTY_NORMAL;
1683
1684        if (likely(lsr & UART_LSR_DR))
1685                ch = serial_in(up, UART_RX);
1686        else
1687                /*
1688                 * Intel 82571 has a Serial Over Lan device that will
1689                 * set UART_LSR_BI without setting UART_LSR_DR when
1690                 * it receives a break. To avoid reading from the
1691                 * receive buffer without UART_LSR_DR bit set, we
1692                 * just force the read character to be 0
1693                 */
1694                ch = 0;
1695
1696        port->icount.rx++;
1697
1698        lsr |= up->lsr_saved_flags;
1699        up->lsr_saved_flags = 0;
1700
1701        if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1702                if (lsr & UART_LSR_BI) {
1703                        lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1704                        port->icount.brk++;
1705                        /*
1706                         * We do the SysRQ and SAK checking
1707                         * here because otherwise the break
1708                         * may get masked by ignore_status_mask
1709                         * or read_status_mask.
1710                         */
1711                        if (uart_handle_break(port))
1712                                return;
1713                } else if (lsr & UART_LSR_PE)
1714                        port->icount.parity++;
1715                else if (lsr & UART_LSR_FE)
1716                        port->icount.frame++;
1717                if (lsr & UART_LSR_OE)
1718                        port->icount.overrun++;
1719
1720                /*
1721                 * Mask off conditions which should be ignored.
1722                 */
1723                lsr &= port->read_status_mask;
1724
1725                if (lsr & UART_LSR_BI) {
1726                        pr_debug("%s: handling break\n", __func__);
1727                        flag = TTY_BREAK;
1728                } else if (lsr & UART_LSR_PE)
1729                        flag = TTY_PARITY;
1730                else if (lsr & UART_LSR_FE)
1731                        flag = TTY_FRAME;
1732        }
1733        if (uart_handle_sysrq_char(port, ch))
1734                return;
1735
1736        uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1737}
1738
1739/*
1740 * serial8250_rx_chars: processes according to the passed in LSR
1741 * value, and returns the remaining LSR bits not handled
1742 * by this Rx routine.
1743 */
1744unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1745{
1746        struct uart_port *port = &up->port;
1747        int max_count = 256;
1748
1749        do {
1750                serial8250_read_char(up, lsr);
1751                if (--max_count == 0)
1752                        break;
1753                lsr = serial_in(up, UART_LSR);
1754        } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1755
1756        tty_flip_buffer_push(&port->state->port);
1757        return lsr;
1758}
1759EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1760
1761void serial8250_tx_chars(struct uart_8250_port *up)
1762{
1763        struct uart_port *port = &up->port;
1764        struct circ_buf *xmit = &port->state->xmit;
1765        int count;
1766
1767        if (port->x_char) {
1768                serial_out(up, UART_TX, port->x_char);
1769                port->icount.tx++;
1770                port->x_char = 0;
1771                return;
1772        }
1773        if (uart_tx_stopped(port)) {
1774                serial8250_stop_tx(port);
1775                return;
1776        }
1777        if (uart_circ_empty(xmit)) {
1778                __stop_tx(up);
1779                return;
1780        }
1781
1782        count = up->tx_loadsz;
1783        do {
1784                serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1785                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1786                port->icount.tx++;
1787                if (uart_circ_empty(xmit))
1788                        break;
1789                if ((up->capabilities & UART_CAP_HFIFO) &&
1790                    (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1791                        break;
1792                /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1793                if ((up->capabilities & UART_CAP_MINI) &&
1794                    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1795                        break;
1796        } while (--count > 0);
1797
1798        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1799                uart_write_wakeup(port);
1800
1801        /*
1802         * With RPM enabled, we have to wait until the FIFO is empty before the
1803         * HW can go idle. So we get here once again with empty FIFO and disable
1804         * the interrupt and RPM in __stop_tx()
1805         */
1806        if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1807                __stop_tx(up);
1808}
1809EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1810
1811/* Caller holds uart port lock */
1812unsigned int serial8250_modem_status(struct uart_8250_port *up)
1813{
1814        struct uart_port *port = &up->port;
1815        unsigned int status = serial_in(up, UART_MSR);
1816
1817        status |= up->msr_saved_flags;
1818        up->msr_saved_flags = 0;
1819        if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1820            port->state != NULL) {
1821                if (status & UART_MSR_TERI)
1822                        port->icount.rng++;
1823                if (status & UART_MSR_DDSR)
1824                        port->icount.dsr++;
1825                if (status & UART_MSR_DDCD)
1826                        uart_handle_dcd_change(port, status & UART_MSR_DCD);
1827                if (status & UART_MSR_DCTS)
1828                        uart_handle_cts_change(port, status & UART_MSR_CTS);
1829
1830                wake_up_interruptible(&port->state->port.delta_msr_wait);
1831        }
1832
1833        return status;
1834}
1835EXPORT_SYMBOL_GPL(serial8250_modem_status);
1836
1837static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1838{
1839        switch (iir & 0x3f) {
1840        case UART_IIR_RX_TIMEOUT:
1841                serial8250_rx_dma_flush(up);
1842                /* fall-through */
1843        case UART_IIR_RLSI:
1844                return true;
1845        }
1846        return up->dma->rx_dma(up);
1847}
1848
1849/*
1850 * This handles the interrupt from one port.
1851 */
1852int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1853{
1854        unsigned char status;
1855        unsigned long flags;
1856        struct uart_8250_port *up = up_to_u8250p(port);
1857
1858        if (iir & UART_IIR_NO_INT)
1859                return 0;
1860
1861        spin_lock_irqsave(&port->lock, flags);
1862
1863        status = serial_port_in(port, UART_LSR);
1864
1865        if (status & (UART_LSR_DR | UART_LSR_BI)) {
1866                if (!up->dma || handle_rx_dma(up, iir))
1867                        status = serial8250_rx_chars(up, status);
1868        }
1869        serial8250_modem_status(up);
1870        if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1871                serial8250_tx_chars(up);
1872
1873        spin_unlock_irqrestore(&port->lock, flags);
1874        return 1;
1875}
1876EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1877
1878static int serial8250_default_handle_irq(struct uart_port *port)
1879{
1880        struct uart_8250_port *up = up_to_u8250p(port);
1881        unsigned int iir;
1882        int ret;
1883
1884        serial8250_rpm_get(up);
1885
1886        iir = serial_port_in(port, UART_IIR);
1887        ret = serial8250_handle_irq(port, iir);
1888
1889        serial8250_rpm_put(up);
1890        return ret;
1891}
1892
1893/*
1894 * These Exar UARTs have an extra interrupt indicator that could
1895 * fire for a few unimplemented interrupts.  One of which is a
1896 * wakeup event when coming out of sleep.  Put this here just
1897 * to be on the safe side that these interrupts don't go unhandled.
1898 */
1899static int exar_handle_irq(struct uart_port *port)
1900{
1901        unsigned int iir = serial_port_in(port, UART_IIR);
1902        int ret = 0;
1903
1904        if (((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X)) &&
1905            serial_port_in(port, UART_EXAR_INT0) != 0)
1906                ret = 1;
1907
1908        ret |= serial8250_handle_irq(port, iir);
1909
1910        return ret;
1911}
1912
1913/*
1914 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1915 * have a programmable TX threshold that triggers the THRE interrupt in
1916 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1917 * has space available. Load it up with tx_loadsz bytes.
1918 */
1919static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1920{
1921        unsigned long flags;
1922        unsigned int iir = serial_port_in(port, UART_IIR);
1923
1924        /* TX Threshold IRQ triggered so load up FIFO */
1925        if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1926                struct uart_8250_port *up = up_to_u8250p(port);
1927
1928                spin_lock_irqsave(&port->lock, flags);
1929                serial8250_tx_chars(up);
1930                spin_unlock_irqrestore(&port->lock, flags);
1931        }
1932
1933        iir = serial_port_in(port, UART_IIR);
1934        return serial8250_handle_irq(port, iir);
1935}
1936
1937static unsigned int serial8250_tx_empty(struct uart_port *port)
1938{
1939        struct uart_8250_port *up = up_to_u8250p(port);
1940        unsigned long flags;
1941        unsigned int lsr;
1942
1943        serial8250_rpm_get(up);
1944
1945        spin_lock_irqsave(&port->lock, flags);
1946        lsr = serial_port_in(port, UART_LSR);
1947        up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1948        spin_unlock_irqrestore(&port->lock, flags);
1949
1950        serial8250_rpm_put(up);
1951
1952        return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1953}
1954
1955unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1956{
1957        struct uart_8250_port *up = up_to_u8250p(port);
1958        unsigned int status;
1959        unsigned int ret;
1960
1961        serial8250_rpm_get(up);
1962        status = serial8250_modem_status(up);
1963        serial8250_rpm_put(up);
1964
1965        ret = 0;
1966        if (status & UART_MSR_DCD)
1967                ret |= TIOCM_CAR;
1968        if (status & UART_MSR_RI)
1969                ret |= TIOCM_RNG;
1970        if (status & UART_MSR_DSR)
1971                ret |= TIOCM_DSR;
1972        if (status & UART_MSR_CTS)
1973                ret |= TIOCM_CTS;
1974        return ret;
1975}
1976EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1977
1978static unsigned int serial8250_get_mctrl(struct uart_port *port)
1979{
1980        if (port->get_mctrl)
1981                return port->get_mctrl(port);
1982        return serial8250_do_get_mctrl(port);
1983}
1984
1985void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1986{
1987        struct uart_8250_port *up = up_to_u8250p(port);
1988        unsigned char mcr = 0;
1989
1990        if (mctrl & TIOCM_RTS)
1991                mcr |= UART_MCR_RTS;
1992        if (mctrl & TIOCM_DTR)
1993                mcr |= UART_MCR_DTR;
1994        if (mctrl & TIOCM_OUT1)
1995                mcr |= UART_MCR_OUT1;
1996        if (mctrl & TIOCM_OUT2)
1997                mcr |= UART_MCR_OUT2;
1998        if (mctrl & TIOCM_LOOP)
1999                mcr |= UART_MCR_LOOP;
2000
2001        mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2002
2003        serial8250_out_MCR(up, mcr);
2004}
2005EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2006
2007static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2008{
2009        if (port->set_mctrl)
2010                port->set_mctrl(port, mctrl);
2011        else
2012                serial8250_do_set_mctrl(port, mctrl);
2013}
2014
2015static void serial8250_break_ctl(struct uart_port *port, int break_state)
2016{
2017        struct uart_8250_port *up = up_to_u8250p(port);
2018        unsigned long flags;
2019
2020        serial8250_rpm_get(up);
2021        spin_lock_irqsave(&port->lock, flags);
2022        if (break_state == -1)
2023                up->lcr |= UART_LCR_SBC;
2024        else
2025                up->lcr &= ~UART_LCR_SBC;
2026        serial_port_out(port, UART_LCR, up->lcr);
2027        spin_unlock_irqrestore(&port->lock, flags);
2028        serial8250_rpm_put(up);
2029}
2030
2031/*
2032 *      Wait for transmitter & holding register to empty
2033 */
2034static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2035{
2036        unsigned int status, tmout = 10000;
2037
2038        /* Wait up to 10ms for the character(s) to be sent. */
2039        for (;;) {
2040                status = serial_in(up, UART_LSR);
2041
2042                up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2043
2044                if ((status & bits) == bits)
2045                        break;
2046                if (--tmout == 0)
2047                        break;
2048                udelay(1);
2049                touch_nmi_watchdog();
2050        }
2051
2052        /* Wait up to 1s for flow control if necessary */
2053        if (up->port.flags & UPF_CONS_FLOW) {
2054                for (tmout = 1000000; tmout; tmout--) {
2055                        unsigned int msr = serial_in(up, UART_MSR);
2056                        up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2057                        if (msr & UART_MSR_CTS)
2058                                break;
2059                        udelay(1);
2060                        touch_nmi_watchdog();
2061                }
2062        }
2063}
2064
2065#ifdef CONFIG_CONSOLE_POLL
2066/*
2067 * Console polling routines for writing and reading from the uart while
2068 * in an interrupt or debug context.
2069 */
2070
2071static int serial8250_get_poll_char(struct uart_port *port)
2072{
2073        struct uart_8250_port *up = up_to_u8250p(port);
2074        unsigned char lsr;
2075        int status;
2076
2077        serial8250_rpm_get(up);
2078
2079        lsr = serial_port_in(port, UART_LSR);
2080
2081        if (!(lsr & UART_LSR_DR)) {
2082                status = NO_POLL_CHAR;
2083                goto out;
2084        }
2085
2086        status = serial_port_in(port, UART_RX);
2087out:
2088        serial8250_rpm_put(up);
2089        return status;
2090}
2091
2092
2093static void serial8250_put_poll_char(struct uart_port *port,
2094                         unsigned char c)
2095{
2096        unsigned int ier;
2097        struct uart_8250_port *up = up_to_u8250p(port);
2098
2099        serial8250_rpm_get(up);
2100        /*
2101         *      First save the IER then disable the interrupts
2102         */
2103        ier = serial_port_in(port, UART_IER);
2104        if (up->capabilities & UART_CAP_UUE)
2105                serial_port_out(port, UART_IER, UART_IER_UUE);
2106        else
2107                serial_port_out(port, UART_IER, 0);
2108
2109        wait_for_xmitr(up, BOTH_EMPTY);
2110        /*
2111         *      Send the character out.
2112         */
2113        serial_port_out(port, UART_TX, c);
2114
2115        /*
2116         *      Finally, wait for transmitter to become empty
2117         *      and restore the IER
2118         */
2119        wait_for_xmitr(up, BOTH_EMPTY);
2120        serial_port_out(port, UART_IER, ier);
2121        serial8250_rpm_put(up);
2122}
2123
2124#endif /* CONFIG_CONSOLE_POLL */
2125
2126int serial8250_do_startup(struct uart_port *port)
2127{
2128        struct uart_8250_port *up = up_to_u8250p(port);
2129        unsigned long flags;
2130        unsigned char lsr, iir;
2131        int retval;
2132
2133        if (!port->fifosize)
2134                port->fifosize = uart_config[port->type].fifo_size;
2135        if (!up->tx_loadsz)
2136                up->tx_loadsz = uart_config[port->type].tx_loadsz;
2137        if (!up->capabilities)
2138                up->capabilities = uart_config[port->type].flags;
2139        up->mcr = 0;
2140
2141        if (port->iotype != up->cur_iotype)
2142                set_io_from_upio(port);
2143
2144        serial8250_rpm_get(up);
2145        if (port->type == PORT_16C950) {
2146                /* Wake up and initialize UART */
2147                up->acr = 0;
2148                serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2149                serial_port_out(port, UART_EFR, UART_EFR_ECB);
2150                serial_port_out(port, UART_IER, 0);
2151                serial_port_out(port, UART_LCR, 0);
2152                serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2153                serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2154                serial_port_out(port, UART_EFR, UART_EFR_ECB);
2155                serial_port_out(port, UART_LCR, 0);
2156        }
2157
2158        if (port->type == PORT_DA830) {
2159                /* Reset the port */
2160                serial_port_out(port, UART_IER, 0);
2161                serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2162                mdelay(10);
2163
2164                /* Enable Tx, Rx and free run mode */
2165                serial_port_out(port, UART_DA830_PWREMU_MGMT,
2166                                UART_DA830_PWREMU_MGMT_UTRST |
2167                                UART_DA830_PWREMU_MGMT_URRST |
2168                                UART_DA830_PWREMU_MGMT_FREE);
2169        }
2170
2171#ifdef CONFIG_SERIAL_8250_RSA
2172        /*
2173         * If this is an RSA port, see if we can kick it up to the
2174         * higher speed clock.
2175         */
2176        enable_rsa(up);
2177#endif
2178
2179        if (port->type == PORT_XR17V35X) {
2180                /*
2181                 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2182                 * MCR [7:5] and MSR [7:0]
2183                 */
2184                serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2185
2186                /*
2187                 * Make sure all interrups are masked until initialization is
2188                 * complete and the FIFOs are cleared
2189                 */
2190                serial_port_out(port, UART_IER, 0);
2191        }
2192
2193        /*
2194         * Clear the FIFO buffers and disable them.
2195         * (they will be reenabled in set_termios())
2196         */
2197        serial8250_clear_fifos(up);
2198
2199        /*
2200         * Clear the interrupt registers.
2201         */
2202        serial_port_in(port, UART_LSR);
2203        serial_port_in(port, UART_RX);
2204        serial_port_in(port, UART_IIR);
2205        serial_port_in(port, UART_MSR);
2206        if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2207                serial_port_in(port, UART_EXAR_INT0);
2208
2209        /*
2210         * At this point, there's no way the LSR could still be 0xff;
2211         * if it is, then bail out, because there's likely no UART
2212         * here.
2213         */
2214        if (!(port->flags & UPF_BUGGY_UART) &&
2215            (serial_port_in(port, UART_LSR) == 0xff)) {
2216                printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2217                                   serial_index(port));
2218                retval = -ENODEV;
2219                goto out;
2220        }
2221
2222        /*
2223         * For a XR16C850, we need to set the trigger levels
2224         */
2225        if (port->type == PORT_16850) {
2226                unsigned char fctr;
2227
2228                serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2229
2230                fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2231                serial_port_out(port, UART_FCTR,
2232                                fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2233                serial_port_out(port, UART_TRG, UART_TRG_96);
2234                serial_port_out(port, UART_FCTR,
2235                                fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2236                serial_port_out(port, UART_TRG, UART_TRG_96);
2237
2238                serial_port_out(port, UART_LCR, 0);
2239        }
2240
2241        /*
2242         * For the Altera 16550 variants, set TX threshold trigger level.
2243         */
2244        if (((port->type == PORT_ALTR_16550_F32) ||
2245             (port->type == PORT_ALTR_16550_F64) ||
2246             (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2247                /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2248                if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2249                        pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2250                               serial_index(port));
2251                } else {
2252                        serial_port_out(port, UART_ALTR_AFR,
2253                                        UART_ALTR_EN_TXFIFO_LW);
2254                        serial_port_out(port, UART_ALTR_TX_LOW,
2255                                        port->fifosize - up->tx_loadsz);
2256                        port->handle_irq = serial8250_tx_threshold_handle_irq;
2257                }
2258        }
2259
2260        if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2261                unsigned char iir1;
2262                /*
2263                 * Test for UARTs that do not reassert THRE when the
2264                 * transmitter is idle and the interrupt has already
2265                 * been cleared.  Real 16550s should always reassert
2266                 * this interrupt whenever the transmitter is idle and
2267                 * the interrupt is enabled.  Delays are necessary to
2268                 * allow register changes to become visible.
2269                 */
2270                spin_lock_irqsave(&port->lock, flags);
2271                if (up->port.irqflags & IRQF_SHARED)
2272                        disable_irq_nosync(port->irq);
2273
2274                wait_for_xmitr(up, UART_LSR_THRE);
2275                serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2276                udelay(1); /* allow THRE to set */
2277                iir1 = serial_port_in(port, UART_IIR);
2278                serial_port_out(port, UART_IER, 0);
2279                serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2280                udelay(1); /* allow a working UART time to re-assert THRE */
2281                iir = serial_port_in(port, UART_IIR);
2282                serial_port_out(port, UART_IER, 0);
2283
2284                if (port->irqflags & IRQF_SHARED)
2285                        enable_irq(port->irq);
2286                spin_unlock_irqrestore(&port->lock, flags);
2287
2288                /*
2289                 * If the interrupt is not reasserted, or we otherwise
2290                 * don't trust the iir, setup a timer to kick the UART
2291                 * on a regular basis.
2292                 */
2293                if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2294                    up->port.flags & UPF_BUG_THRE) {
2295                        up->bugs |= UART_BUG_THRE;
2296                }
2297        }
2298
2299        retval = up->ops->setup_irq(up);
2300        if (retval)
2301                goto out;
2302
2303        /*
2304         * Now, initialize the UART
2305         */
2306        serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2307
2308        spin_lock_irqsave(&port->lock, flags);
2309        if (up->port.flags & UPF_FOURPORT) {
2310                if (!up->port.irq)
2311                        up->port.mctrl |= TIOCM_OUT1;
2312        } else
2313                /*
2314                 * Most PC uarts need OUT2 raised to enable interrupts.
2315                 */
2316                if (port->irq)
2317                        up->port.mctrl |= TIOCM_OUT2;
2318
2319        serial8250_set_mctrl(port, port->mctrl);
2320
2321        /*
2322         * Serial over Lan (SoL) hack:
2323         * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2324         * used for Serial Over Lan.  Those chips take a longer time than a
2325         * normal serial device to signalize that a transmission data was
2326         * queued. Due to that, the above test generally fails. One solution
2327         * would be to delay the reading of iir. However, this is not
2328         * reliable, since the timeout is variable. So, let's just don't
2329         * test if we receive TX irq.  This way, we'll never enable
2330         * UART_BUG_TXEN.
2331         */
2332        if (up->port.quirks & UPQ_NO_TXEN_TEST)
2333                goto dont_test_tx_en;
2334
2335        /*
2336         * Do a quick test to see if we receive an interrupt when we enable
2337         * the TX irq.
2338         */
2339        serial_port_out(port, UART_IER, UART_IER_THRI);
2340        lsr = serial_port_in(port, UART_LSR);
2341        iir = serial_port_in(port, UART_IIR);
2342        serial_port_out(port, UART_IER, 0);
2343
2344        if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2345                if (!(up->bugs & UART_BUG_TXEN)) {
2346                        up->bugs |= UART_BUG_TXEN;
2347                        pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2348                                 serial_index(port));
2349                }
2350        } else {
2351                up->bugs &= ~UART_BUG_TXEN;
2352        }
2353
2354dont_test_tx_en:
2355        spin_unlock_irqrestore(&port->lock, flags);
2356
2357        /*
2358         * Clear the interrupt registers again for luck, and clear the
2359         * saved flags to avoid getting false values from polling
2360         * routines or the previous session.
2361         */
2362        serial_port_in(port, UART_LSR);
2363        serial_port_in(port, UART_RX);
2364        serial_port_in(port, UART_IIR);
2365        serial_port_in(port, UART_MSR);
2366        if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2367                serial_port_in(port, UART_EXAR_INT0);
2368        up->lsr_saved_flags = 0;
2369        up->msr_saved_flags = 0;
2370
2371        /*
2372         * Request DMA channels for both RX and TX.
2373         */
2374        if (up->dma) {
2375                retval = serial8250_request_dma(up);
2376                if (retval) {
2377                        pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2378                                            serial_index(port));
2379                        up->dma = NULL;
2380                }
2381        }
2382
2383        /*
2384         * Set the IER shadow for rx interrupts but defer actual interrupt
2385         * enable until after the FIFOs are enabled; otherwise, an already-
2386         * active sender can swamp the interrupt handler with "too much work".
2387         */
2388        up->ier = UART_IER_RLSI | UART_IER_RDI;
2389
2390        if (port->flags & UPF_FOURPORT) {
2391                unsigned int icp;
2392                /*
2393                 * Enable interrupts on the AST Fourport board
2394                 */
2395                icp = (port->iobase & 0xfe0) | 0x01f;
2396                outb_p(0x80, icp);
2397                inb_p(icp);
2398        }
2399        retval = 0;
2400out:
2401        serial8250_rpm_put(up);
2402        return retval;
2403}
2404EXPORT_SYMBOL_GPL(serial8250_do_startup);
2405
2406static int serial8250_startup(struct uart_port *port)
2407{
2408        if (port->startup)
2409                return port->startup(port);
2410        return serial8250_do_startup(port);
2411}
2412
2413void serial8250_do_shutdown(struct uart_port *port)
2414{
2415        struct uart_8250_port *up = up_to_u8250p(port);
2416        unsigned long flags;
2417
2418        serial8250_rpm_get(up);
2419        /*
2420         * Disable interrupts from this port
2421         */
2422        spin_lock_irqsave(&port->lock, flags);
2423        up->ier = 0;
2424        serial_port_out(port, UART_IER, 0);
2425        spin_unlock_irqrestore(&port->lock, flags);
2426
2427        synchronize_irq(port->irq);
2428
2429        if (up->dma)
2430                serial8250_release_dma(up);
2431
2432        spin_lock_irqsave(&port->lock, flags);
2433        if (port->flags & UPF_FOURPORT) {
2434                /* reset interrupts on the AST Fourport board */
2435                inb((port->iobase & 0xfe0) | 0x1f);
2436                port->mctrl |= TIOCM_OUT1;
2437        } else
2438                port->mctrl &= ~TIOCM_OUT2;
2439
2440        serial8250_set_mctrl(port, port->mctrl);
2441        spin_unlock_irqrestore(&port->lock, flags);
2442
2443        /*
2444         * Disable break condition and FIFOs
2445         */
2446        serial_port_out(port, UART_LCR,
2447                        serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2448        serial8250_clear_fifos(up);
2449
2450#ifdef CONFIG_SERIAL_8250_RSA
2451        /*
2452         * Reset the RSA board back to 115kbps compat mode.
2453         */
2454        disable_rsa(up);
2455#endif
2456
2457        /*
2458         * Read data port to reset things, and then unlink from
2459         * the IRQ chain.
2460         */
2461        serial_port_in(port, UART_RX);
2462        serial8250_rpm_put(up);
2463
2464        up->ops->release_irq(up);
2465}
2466EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2467
2468static void serial8250_shutdown(struct uart_port *port)
2469{
2470        if (port->shutdown)
2471                port->shutdown(port);
2472        else
2473                serial8250_do_shutdown(port);
2474}
2475
2476/*
2477 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2478 * Calculate divisor with extra 4-bit fractional portion
2479 */
2480static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2481                                         unsigned int baud,
2482                                         unsigned int *frac)
2483{
2484        struct uart_port *port = &up->port;
2485        unsigned int quot_16;
2486
2487        quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2488        *frac = quot_16 & 0x0f;
2489
2490        return quot_16 >> 4;
2491}
2492
2493static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2494                                           unsigned int baud,
2495                                           unsigned int *frac)
2496{
2497        struct uart_port *port = &up->port;
2498        unsigned int quot;
2499
2500        /*
2501         * Handle magic divisors for baud rates above baud_base on
2502         * SMSC SuperIO chips.
2503         *
2504         */
2505        if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2506            baud == (port->uartclk/4))
2507                quot = 0x8001;
2508        else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2509                 baud == (port->uartclk/8))
2510                quot = 0x8002;
2511        else if (up->port.type == PORT_XR17V35X)
2512                quot = xr17v35x_get_divisor(up, baud, frac);
2513        else
2514                quot = uart_get_divisor(port, baud);
2515
2516        /*
2517         * Oxford Semi 952 rev B workaround
2518         */
2519        if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2520                quot++;
2521
2522        return quot;
2523}
2524
2525static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2526                                            tcflag_t c_cflag)
2527{
2528        unsigned char cval;
2529
2530        switch (c_cflag & CSIZE) {
2531        case CS5:
2532                cval = UART_LCR_WLEN5;
2533                break;
2534        case CS6:
2535                cval = UART_LCR_WLEN6;
2536                break;
2537        case CS7:
2538                cval = UART_LCR_WLEN7;
2539                break;
2540        default:
2541        case CS8:
2542                cval = UART_LCR_WLEN8;
2543                break;
2544        }
2545
2546        if (c_cflag & CSTOPB)
2547                cval |= UART_LCR_STOP;
2548        if (c_cflag & PARENB) {
2549                cval |= UART_LCR_PARITY;
2550                if (up->bugs & UART_BUG_PARITY)
2551                        up->fifo_bug = true;
2552        }
2553        if (!(c_cflag & PARODD))
2554                cval |= UART_LCR_EPAR;
2555#ifdef CMSPAR
2556        if (c_cflag & CMSPAR)
2557                cval |= UART_LCR_SPAR;
2558#endif
2559
2560        return cval;
2561}
2562
2563static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2564                            unsigned int quot, unsigned int quot_frac)
2565{
2566        struct uart_8250_port *up = up_to_u8250p(port);
2567
2568        /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2569        if (is_omap1510_8250(up)) {
2570                if (baud == 115200) {
2571                        quot = 1;
2572                        serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2573                } else
2574                        serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2575        }
2576
2577        /*
2578         * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2579         * otherwise just set DLAB
2580         */
2581        if (up->capabilities & UART_NATSEMI)
2582                serial_port_out(port, UART_LCR, 0xe0);
2583        else
2584                serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2585
2586        serial_dl_write(up, quot);
2587
2588        /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2589        if (up->port.type == PORT_XR17V35X)
2590                serial_port_out(port, 0x2, quot_frac);
2591}
2592
2593static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2594                                             struct ktermios *termios,
2595                                             struct ktermios *old)
2596{
2597        /*
2598         * Ask the core to calculate the divisor for us.
2599         * Allow 1% tolerance at the upper limit so uart clks marginally
2600         * slower than nominal still match standard baud rates without
2601         * causing transmission errors.
2602         */
2603        return uart_get_baud_rate(port, termios, old,
2604                                  port->uartclk / 16 / 0xffff,
2605                                  port->uartclk);
2606}
2607
2608void
2609serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2610                          struct ktermios *old)
2611{
2612        struct uart_8250_port *up = up_to_u8250p(port);
2613        unsigned char cval;
2614        unsigned long flags;
2615        unsigned int baud, quot, frac = 0;
2616
2617        if (up->capabilities & UART_CAP_MINI) {
2618                termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2619                if ((termios->c_cflag & CSIZE) == CS5 ||
2620                    (termios->c_cflag & CSIZE) == CS6)
2621                        termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2622        }
2623        cval = serial8250_compute_lcr(up, termios->c_cflag);
2624
2625        baud = serial8250_get_baud_rate(port, termios, old);
2626        quot = serial8250_get_divisor(up, baud, &frac);
2627
2628        /*
2629         * Ok, we're now changing the port state.  Do it with
2630         * interrupts disabled.
2631         */
2632        serial8250_rpm_get(up);
2633        spin_lock_irqsave(&port->lock, flags);
2634
2635        up->lcr = cval;                                 /* Save computed LCR */
2636
2637        if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2638                /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2639                if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2640                        up->fcr &= ~UART_FCR_TRIGGER_MASK;
2641                        up->fcr |= UART_FCR_TRIGGER_1;
2642                }
2643        }
2644
2645        /*
2646         * MCR-based auto flow control.  When AFE is enabled, RTS will be
2647         * deasserted when the receive FIFO contains more characters than
2648         * the trigger, or the MCR RTS bit is cleared.
2649         */
2650        if (up->capabilities & UART_CAP_AFE) {
2651                up->mcr &= ~UART_MCR_AFE;
2652                if (termios->c_cflag & CRTSCTS)
2653                        up->mcr |= UART_MCR_AFE;
2654        }
2655
2656        /*
2657         * Update the per-port timeout.
2658         */
2659        uart_update_timeout(port, termios->c_cflag, baud);
2660
2661        port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2662        if (termios->c_iflag & INPCK)
2663                port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2664        if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2665                port->read_status_mask |= UART_LSR_BI;
2666
2667        /*
2668         * Characteres to ignore
2669         */
2670        port->ignore_status_mask = 0;
2671        if (termios->c_iflag & IGNPAR)
2672                port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2673        if (termios->c_iflag & IGNBRK) {
2674                port->ignore_status_mask |= UART_LSR_BI;
2675                /*
2676                 * If we're ignoring parity and break indicators,
2677                 * ignore overruns too (for real raw support).
2678                 */
2679                if (termios->c_iflag & IGNPAR)
2680                        port->ignore_status_mask |= UART_LSR_OE;
2681        }
2682
2683        /*
2684         * ignore all characters if CREAD is not set
2685         */
2686        if ((termios->c_cflag & CREAD) == 0)
2687                port->ignore_status_mask |= UART_LSR_DR;
2688
2689        /*
2690         * CTS flow control flag and modem status interrupts
2691         */
2692        up->ier &= ~UART_IER_MSI;
2693        if (!(up->bugs & UART_BUG_NOMSR) &&
2694                        UART_ENABLE_MS(&up->port, termios->c_cflag))
2695                up->ier |= UART_IER_MSI;
2696        if (up->capabilities & UART_CAP_UUE)
2697                up->ier |= UART_IER_UUE;
2698        if (up->capabilities & UART_CAP_RTOIE)
2699                up->ier |= UART_IER_RTOIE;
2700
2701        serial_port_out(port, UART_IER, up->ier);
2702
2703        if (up->capabilities & UART_CAP_EFR) {
2704                unsigned char efr = 0;
2705                /*
2706                 * TI16C752/Startech hardware flow control.  FIXME:
2707                 * - TI16C752 requires control thresholds to be set.
2708                 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2709                 */
2710                if (termios->c_cflag & CRTSCTS)
2711                        efr |= UART_EFR_CTS;
2712
2713                serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2714                if (port->flags & UPF_EXAR_EFR)
2715                        serial_port_out(port, UART_XR_EFR, efr);
2716                else
2717                        serial_port_out(port, UART_EFR, efr);
2718        }
2719
2720        serial8250_set_divisor(port, baud, quot, frac);
2721
2722        /*
2723         * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2724         * is written without DLAB set, this mode will be disabled.
2725         */
2726        if (port->type == PORT_16750)
2727                serial_port_out(port, UART_FCR, up->fcr);
2728
2729        serial_port_out(port, UART_LCR, up->lcr);       /* reset DLAB */
2730        if (port->type != PORT_16750) {
2731                /* emulated UARTs (Lucent Venus 167x) need two steps */
2732                if (up->fcr & UART_FCR_ENABLE_FIFO)
2733                        serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2734                serial_port_out(port, UART_FCR, up->fcr);       /* set fcr */
2735        }
2736        serial8250_set_mctrl(port, port->mctrl);
2737        spin_unlock_irqrestore(&port->lock, flags);
2738        serial8250_rpm_put(up);
2739
2740        /* Don't rewrite B0 */
2741        if (tty_termios_baud_rate(termios))
2742                tty_termios_encode_baud_rate(termios, baud, baud);
2743}
2744EXPORT_SYMBOL(serial8250_do_set_termios);
2745
2746static void
2747serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2748                       struct ktermios *old)
2749{
2750        if (port->set_termios)
2751                port->set_termios(port, termios, old);
2752        else
2753                serial8250_do_set_termios(port, termios, old);
2754}
2755
2756void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2757{
2758        if (termios->c_line == N_PPS) {
2759                port->flags |= UPF_HARDPPS_CD;
2760                spin_lock_irq(&port->lock);
2761                serial8250_enable_ms(port);
2762                spin_unlock_irq(&port->lock);
2763        } else {
2764                port->flags &= ~UPF_HARDPPS_CD;
2765                if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2766                        spin_lock_irq(&port->lock);
2767                        serial8250_disable_ms(port);
2768                        spin_unlock_irq(&port->lock);
2769                }
2770        }
2771}
2772EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2773
2774static void
2775serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2776{
2777        if (port->set_ldisc)
2778                port->set_ldisc(port, termios);
2779        else
2780                serial8250_do_set_ldisc(port, termios);
2781}
2782
2783void serial8250_do_pm(struct uart_port *port, unsigned int state,
2784                      unsigned int oldstate)
2785{
2786        struct uart_8250_port *p = up_to_u8250p(port);
2787
2788        serial8250_set_sleep(p, state != 0);
2789}
2790EXPORT_SYMBOL(serial8250_do_pm);
2791
2792static void
2793serial8250_pm(struct uart_port *port, unsigned int state,
2794              unsigned int oldstate)
2795{
2796        if (port->pm)
2797                port->pm(port, state, oldstate);
2798        else
2799                serial8250_do_pm(port, state, oldstate);
2800}
2801
2802static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2803{
2804        if (pt->port.mapsize)
2805                return pt->port.mapsize;
2806        if (pt->port.iotype == UPIO_AU) {
2807                if (pt->port.type == PORT_RT2880)
2808                        return 0x100;
2809                return 0x1000;
2810        }
2811        if (is_omap1_8250(pt))
2812                return 0x16 << pt->port.regshift;
2813
2814        return 8 << pt->port.regshift;
2815}
2816
2817/*
2818 * Resource handling.
2819 */
2820static int serial8250_request_std_resource(struct uart_8250_port *up)
2821{
2822        unsigned int size = serial8250_port_size(up);
2823        struct uart_port *port = &up->port;
2824        int ret = 0;
2825
2826        switch (port->iotype) {
2827        case UPIO_AU:
2828        case UPIO_TSI:
2829        case UPIO_MEM32:
2830        case UPIO_MEM32BE:
2831        case UPIO_MEM16:
2832        case UPIO_MEM:
2833                if (!port->mapbase)
2834                        break;
2835
2836                if (!request_mem_region(port->mapbase, size, "serial")) {
2837                        ret = -EBUSY;
2838                        break;
2839                }
2840
2841                if (port->flags & UPF_IOREMAP) {
2842                        port->membase = ioremap_nocache(port->mapbase, size);
2843                        if (!port->membase) {
2844                                release_mem_region(port->mapbase, size);
2845                                ret = -ENOMEM;
2846                        }
2847                }
2848                break;
2849
2850        case UPIO_HUB6:
2851        case UPIO_PORT:
2852                if (!request_region(port->iobase, size, "serial"))
2853                        ret = -EBUSY;
2854                break;
2855        }
2856        return ret;
2857}
2858
2859static void serial8250_release_std_resource(struct uart_8250_port *up)
2860{
2861        unsigned int size = serial8250_port_size(up);
2862        struct uart_port *port = &up->port;
2863
2864        switch (port->iotype) {
2865        case UPIO_AU:
2866        case UPIO_TSI:
2867        case UPIO_MEM32:
2868        case UPIO_MEM32BE:
2869        case UPIO_MEM16:
2870        case UPIO_MEM:
2871                if (!port->mapbase)
2872                        break;
2873
2874                if (port->flags & UPF_IOREMAP) {
2875                        iounmap(port->membase);
2876                        port->membase = NULL;
2877                }
2878
2879                release_mem_region(port->mapbase, size);
2880                break;
2881
2882        case UPIO_HUB6:
2883        case UPIO_PORT:
2884                release_region(port->iobase, size);
2885                break;
2886        }
2887}
2888
2889static void serial8250_release_port(struct uart_port *port)
2890{
2891        struct uart_8250_port *up = up_to_u8250p(port);
2892
2893        serial8250_release_std_resource(up);
2894}
2895
2896static int serial8250_request_port(struct uart_port *port)
2897{
2898        struct uart_8250_port *up = up_to_u8250p(port);
2899
2900        return serial8250_request_std_resource(up);
2901}
2902
2903static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2904{
2905        const struct serial8250_config *conf_type = &uart_config[up->port.type];
2906        unsigned char bytes;
2907
2908        bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2909
2910        return bytes ? bytes : -EOPNOTSUPP;
2911}
2912
2913static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2914{
2915        const struct serial8250_config *conf_type = &uart_config[up->port.type];
2916        int i;
2917
2918        if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2919                return -EOPNOTSUPP;
2920
2921        for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2922                if (bytes < conf_type->rxtrig_bytes[i])
2923                        /* Use the nearest lower value */
2924                        return (--i) << UART_FCR_R_TRIG_SHIFT;
2925        }
2926
2927        return UART_FCR_R_TRIG_11;
2928}
2929
2930static int do_get_rxtrig(struct tty_port *port)
2931{
2932        struct uart_state *state = container_of(port, struct uart_state, port);
2933        struct uart_port *uport = state->uart_port;
2934        struct uart_8250_port *up = up_to_u8250p(uport);
2935
2936        if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2937                return -EINVAL;
2938
2939        return fcr_get_rxtrig_bytes(up);
2940}
2941
2942static int do_serial8250_get_rxtrig(struct tty_port *port)
2943{
2944        int rxtrig_bytes;
2945
2946        mutex_lock(&port->mutex);
2947        rxtrig_bytes = do_get_rxtrig(port);
2948        mutex_unlock(&port->mutex);
2949
2950        return rxtrig_bytes;
2951}
2952
2953static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2954        struct device_attribute *attr, char *buf)
2955{
2956        struct tty_port *port = dev_get_drvdata(dev);
2957        int rxtrig_bytes;
2958
2959        rxtrig_bytes = do_serial8250_get_rxtrig(port);
2960        if (rxtrig_bytes < 0)
2961                return rxtrig_bytes;
2962
2963        return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2964}
2965
2966static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2967{
2968        struct uart_state *state = container_of(port, struct uart_state, port);
2969        struct uart_port *uport = state->uart_port;
2970        struct uart_8250_port *up = up_to_u8250p(uport);
2971        int rxtrig;
2972
2973        if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2974            up->fifo_bug)
2975                return -EINVAL;
2976
2977        rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2978        if (rxtrig < 0)
2979                return rxtrig;
2980
2981        serial8250_clear_fifos(up);
2982        up->fcr &= ~UART_FCR_TRIGGER_MASK;
2983        up->fcr |= (unsigned char)rxtrig;
2984        serial_out(up, UART_FCR, up->fcr);
2985        return 0;
2986}
2987
2988static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2989{
2990        int ret;
2991
2992        mutex_lock(&port->mutex);
2993        ret = do_set_rxtrig(port, bytes);
2994        mutex_unlock(&port->mutex);
2995
2996        return ret;
2997}
2998
2999static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3000        struct device_attribute *attr, const char *buf, size_t count)
3001{
3002        struct tty_port *port = dev_get_drvdata(dev);
3003        unsigned char bytes;
3004        int ret;
3005
3006        if (!count)
3007                return -EINVAL;
3008
3009        ret = kstrtou8(buf, 10, &bytes);
3010        if (ret < 0)
3011                return ret;
3012
3013        ret = do_serial8250_set_rxtrig(port, bytes);
3014        if (ret < 0)
3015                return ret;
3016
3017        return count;
3018}
3019
3020static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3021                   serial8250_get_attr_rx_trig_bytes,
3022                   serial8250_set_attr_rx_trig_bytes);
3023
3024static struct attribute *serial8250_dev_attrs[] = {
3025        &dev_attr_rx_trig_bytes.attr,
3026        NULL,
3027        };
3028
3029static struct attribute_group serial8250_dev_attr_group = {
3030        .attrs = serial8250_dev_attrs,
3031        };
3032
3033static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3034{
3035        const struct serial8250_config *conf_type = &uart_config[up->port.type];
3036
3037        if (conf_type->rxtrig_bytes[0])
3038                up->port.attr_group = &serial8250_dev_attr_group;
3039}
3040
3041static void serial8250_config_port(struct uart_port *port, int flags)
3042{
3043        struct uart_8250_port *up = up_to_u8250p(port);
3044        int ret;
3045
3046        /*
3047         * Find the region that we can probe for.  This in turn
3048         * tells us whether we can probe for the type of port.
3049         */
3050        ret = serial8250_request_std_resource(up);
3051        if (ret < 0)
3052                return;
3053
3054        if (port->iotype != up->cur_iotype)
3055                set_io_from_upio(port);
3056
3057        if (flags & UART_CONFIG_TYPE)
3058                autoconfig(up);
3059
3060        /* if access method is AU, it is a 16550 with a quirk */
3061        if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3062                up->bugs |= UART_BUG_NOMSR;
3063
3064        /* HW bugs may trigger IRQ while IIR == NO_INT */
3065        if (port->type == PORT_TEGRA)
3066                up->bugs |= UART_BUG_NOMSR;
3067
3068        if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3069                autoconfig_irq(up);
3070
3071        if (port->type == PORT_UNKNOWN)
3072                serial8250_release_std_resource(up);
3073
3074        /* Fixme: probably not the best place for this */
3075        if ((port->type == PORT_XR17V35X) ||
3076           (port->type == PORT_XR17D15X))
3077                port->handle_irq = exar_handle_irq;
3078
3079        register_dev_spec_attr_grp(up);
3080        up->fcr = uart_config[up->port.type].fcr;
3081}
3082
3083static int
3084serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3085{
3086        if (ser->irq >= nr_irqs || ser->irq < 0 ||
3087            ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3088            ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3089            ser->type == PORT_STARTECH)
3090                return -EINVAL;
3091        return 0;
3092}
3093
3094static const char *serial8250_type(struct uart_port *port)
3095{
3096        int type = port->type;
3097
3098        if (type >= ARRAY_SIZE(uart_config))
3099                type = 0;
3100        return uart_config[type].name;
3101}
3102
3103static const struct uart_ops serial8250_pops = {
3104        .tx_empty       = serial8250_tx_empty,
3105        .set_mctrl      = serial8250_set_mctrl,
3106        .get_mctrl      = serial8250_get_mctrl,
3107        .stop_tx        = serial8250_stop_tx,
3108        .start_tx       = serial8250_start_tx,
3109        .throttle       = serial8250_throttle,
3110        .unthrottle     = serial8250_unthrottle,
3111        .stop_rx        = serial8250_stop_rx,
3112        .enable_ms      = serial8250_enable_ms,
3113        .break_ctl      = serial8250_break_ctl,
3114        .startup        = serial8250_startup,
3115        .shutdown       = serial8250_shutdown,
3116        .set_termios    = serial8250_set_termios,
3117        .set_ldisc      = serial8250_set_ldisc,
3118        .pm             = serial8250_pm,
3119        .type           = serial8250_type,
3120        .release_port   = serial8250_release_port,
3121        .request_port   = serial8250_request_port,
3122        .config_port    = serial8250_config_port,
3123        .verify_port    = serial8250_verify_port,
3124#ifdef CONFIG_CONSOLE_POLL
3125        .poll_get_char = serial8250_get_poll_char,
3126        .poll_put_char = serial8250_put_poll_char,
3127#endif
3128};
3129
3130void serial8250_init_port(struct uart_8250_port *up)
3131{
3132        struct uart_port *port = &up->port;
3133
3134        spin_lock_init(&port->lock);
3135        port->ops = &serial8250_pops;
3136
3137        up->cur_iotype = 0xFF;
3138}
3139EXPORT_SYMBOL_GPL(serial8250_init_port);
3140
3141void serial8250_set_defaults(struct uart_8250_port *up)
3142{
3143        struct uart_port *port = &up->port;
3144
3145        if (up->port.flags & UPF_FIXED_TYPE) {
3146                unsigned int type = up->port.type;
3147
3148                if (!up->port.fifosize)
3149                        up->port.fifosize = uart_config[type].fifo_size;
3150                if (!up->tx_loadsz)
3151                        up->tx_loadsz = uart_config[type].tx_loadsz;
3152                if (!up->capabilities)
3153                        up->capabilities = uart_config[type].flags;
3154        }
3155
3156        set_io_from_upio(port);
3157
3158        /* default dma handlers */
3159        if (up->dma) {
3160                if (!up->dma->tx_dma)
3161                        up->dma->tx_dma = serial8250_tx_dma;
3162                if (!up->dma->rx_dma)
3163                        up->dma->rx_dma = serial8250_rx_dma;
3164        }
3165}
3166EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3167
3168#ifdef CONFIG_SERIAL_8250_CONSOLE
3169
3170static void serial8250_console_putchar(struct uart_port *port, int ch)
3171{
3172        struct uart_8250_port *up = up_to_u8250p(port);
3173
3174        wait_for_xmitr(up, UART_LSR_THRE);
3175        serial_port_out(port, UART_TX, ch);
3176}
3177
3178/*
3179 *      Restore serial console when h/w power-off detected
3180 */
3181static void serial8250_console_restore(struct uart_8250_port *up)
3182{
3183        struct uart_port *port = &up->port;
3184        struct ktermios termios;
3185        unsigned int baud, quot, frac = 0;
3186
3187        termios.c_cflag = port->cons->cflag;
3188        if (port->state->port.tty && termios.c_cflag == 0)
3189                termios.c_cflag = port->state->port.tty->termios.c_cflag;
3190
3191        baud = serial8250_get_baud_rate(port, &termios, NULL);
3192        quot = serial8250_get_divisor(up, baud, &frac);
3193
3194        serial8250_set_divisor(port, baud, quot, frac);
3195        serial_port_out(port, UART_LCR, up->lcr);
3196        serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3197}
3198
3199/*
3200 *      Print a string to the serial port trying not to disturb
3201 *      any possible real use of the port...
3202 *
3203 *      The console_lock must be held when we get here.
3204 */
3205void serial8250_console_write(struct uart_8250_port *up, const char *s,
3206                              unsigned int count)
3207{
3208        struct uart_port *port = &up->port;
3209        unsigned long flags;
3210        unsigned int ier;
3211        int locked = 1;
3212
3213        touch_nmi_watchdog();
3214
3215        serial8250_rpm_get(up);
3216
3217        if (port->sysrq)
3218                locked = 0;
3219        else if (oops_in_progress)
3220                locked = spin_trylock_irqsave(&port->lock, flags);
3221        else
3222                spin_lock_irqsave(&port->lock, flags);
3223
3224        /*
3225         *      First save the IER then disable the interrupts
3226         */
3227        ier = serial_port_in(port, UART_IER);
3228
3229        if (up->capabilities & UART_CAP_UUE)
3230                serial_port_out(port, UART_IER, UART_IER_UUE);
3231        else
3232                serial_port_out(port, UART_IER, 0);
3233
3234        /* check scratch reg to see if port powered off during system sleep */
3235        if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3236                serial8250_console_restore(up);
3237                up->canary = 0;
3238        }
3239
3240        uart_console_write(port, s, count, serial8250_console_putchar);
3241
3242        /*
3243         *      Finally, wait for transmitter to become empty
3244         *      and restore the IER
3245         */
3246        wait_for_xmitr(up, BOTH_EMPTY);
3247        serial_port_out(port, UART_IER, ier);
3248
3249        /*
3250         *      The receive handling will happen properly because the
3251         *      receive ready bit will still be set; it is not cleared
3252         *      on read.  However, modem control will not, we must
3253         *      call it if we have saved something in the saved flags
3254         *      while processing with interrupts off.
3255         */
3256        if (up->msr_saved_flags)
3257                serial8250_modem_status(up);
3258
3259        if (locked)
3260                spin_unlock_irqrestore(&port->lock, flags);
3261        serial8250_rpm_put(up);
3262}
3263
3264static unsigned int probe_baud(struct uart_port *port)
3265{
3266        unsigned char lcr, dll, dlm;
3267        unsigned int quot;
3268
3269        lcr = serial_port_in(port, UART_LCR);
3270        serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3271        dll = serial_port_in(port, UART_DLL);
3272        dlm = serial_port_in(port, UART_DLM);
3273        serial_port_out(port, UART_LCR, lcr);
3274
3275        quot = (dlm << 8) | dll;
3276        return (port->uartclk / 16) / quot;
3277}
3278
3279int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3280{
3281        int baud = 9600;
3282        int bits = 8;
3283        int parity = 'n';
3284        int flow = 'n';
3285
3286        if (!port->iobase && !port->membase)
3287                return -ENODEV;
3288
3289        if (options)
3290                uart_parse_options(options, &baud, &parity, &bits, &flow);
3291        else if (probe)
3292                baud = probe_baud(port);
3293
3294        return uart_set_options(port, port->cons, baud, parity, bits, flow);
3295}
3296
3297#endif /* CONFIG_SERIAL_8250_CONSOLE */
3298
3299MODULE_LICENSE("GPL");
3300