linux/drivers/usb/gadget/udc/net2272.h
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   1/*
   2 * PLX NET2272 high/full speed USB device controller
   3 *
   4 * Copyright (C) 2005-2006 PLX Technology, Inc.
   5 * Copyright (C) 2006-2011 Analog Devices, Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20 */
  21
  22#ifndef __NET2272_H__
  23#define __NET2272_H__
  24
  25/* Main Registers */
  26#define REGADDRPTR                      0x00
  27#define REGDATA                         0x01
  28#define IRQSTAT0                        0x02
  29#define         ENDPOINT_0_INTERRUPT                    0
  30#define         ENDPOINT_A_INTERRUPT                    1
  31#define         ENDPOINT_B_INTERRUPT                    2
  32#define         ENDPOINT_C_INTERRUPT                    3
  33#define         VIRTUALIZED_ENDPOINT_INTERRUPT          4
  34#define         SETUP_PACKET_INTERRUPT                  5
  35#define         DMA_DONE_INTERRUPT                      6
  36#define         SOF_INTERRUPT                           7
  37#define IRQSTAT1                        0x03
  38#define         CONTROL_STATUS_INTERRUPT                1
  39#define         VBUS_INTERRUPT                          2
  40#define         SUSPEND_REQUEST_INTERRUPT               3
  41#define         SUSPEND_REQUEST_CHANGE_INTERRUPT        4
  42#define         RESUME_INTERRUPT                        5
  43#define         ROOT_PORT_RESET_INTERRUPT               6
  44#define         RESET_STATUS                            7
  45#define PAGESEL                         0x04
  46#define DMAREQ                          0x1c
  47#define         DMA_ENDPOINT_SELECT                     0
  48#define         DREQ_POLARITY                           1
  49#define         DACK_POLARITY                           2
  50#define         EOT_POLARITY                            3
  51#define         DMA_CONTROL_DACK                        4
  52#define         DMA_REQUEST_ENABLE                      5
  53#define         DMA_REQUEST                             6
  54#define         DMA_BUFFER_VALID                        7
  55#define SCRATCH                         0x1d
  56#define IRQENB0                         0x20
  57#define         ENDPOINT_0_INTERRUPT_ENABLE             0
  58#define         ENDPOINT_A_INTERRUPT_ENABLE             1
  59#define         ENDPOINT_B_INTERRUPT_ENABLE             2
  60#define         ENDPOINT_C_INTERRUPT_ENABLE             3
  61#define         VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE   4
  62#define         SETUP_PACKET_INTERRUPT_ENABLE           5
  63#define         DMA_DONE_INTERRUPT_ENABLE               6
  64#define         SOF_INTERRUPT_ENABLE                    7
  65#define IRQENB1                         0x21
  66#define         VBUS_INTERRUPT_ENABLE                   2
  67#define         SUSPEND_REQUEST_INTERRUPT_ENABLE        3
  68#define         SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4
  69#define         RESUME_INTERRUPT_ENABLE                 5
  70#define         ROOT_PORT_RESET_INTERRUPT_ENABLE        6
  71#define LOCCTL                          0x22
  72#define         DATA_WIDTH                              0
  73#define         LOCAL_CLOCK_OUTPUT                      1
  74#define                 LOCAL_CLOCK_OUTPUT_OFF                  0
  75#define                 LOCAL_CLOCK_OUTPUT_3_75MHZ              1
  76#define                 LOCAL_CLOCK_OUTPUT_7_5MHZ               2
  77#define                 LOCAL_CLOCK_OUTPUT_15MHZ                3
  78#define                 LOCAL_CLOCK_OUTPUT_30MHZ                4
  79#define                 LOCAL_CLOCK_OUTPUT_60MHZ                5
  80#define         DMA_SPLIT_BUS_MODE                      4
  81#define         BYTE_SWAP                               5
  82#define         BUFFER_CONFIGURATION                    6
  83#define                 BUFFER_CONFIGURATION_EPA512_EPB512      0
  84#define                 BUFFER_CONFIGURATION_EPA1024_EPB512     1
  85#define                 BUFFER_CONFIGURATION_EPA1024_EPB1024    2
  86#define                 BUFFER_CONFIGURATION_EPA1024DB          3
  87#define CHIPREV_LEGACY                  0x23
  88#define                 NET2270_LEGACY_REV                      0x40
  89#define LOCCTL1                         0x24
  90#define         DMA_MODE                                0
  91#define                 SLOW_DREQ                               0
  92#define                 FAST_DREQ                               1
  93#define                 BURST_MODE                              2
  94#define         DMA_DACK_ENABLE                         2
  95#define CHIPREV_2272                    0x25
  96#define                 CHIPREV_NET2272_R1                      0x10
  97#define                 CHIPREV_NET2272_R1A                     0x11
  98/* USB Registers */
  99#define USBCTL0                         0x18
 100#define         IO_WAKEUP_ENABLE                        1
 101#define         USB_DETECT_ENABLE                       3
 102#define         USB_ROOT_PORT_WAKEUP_ENABLE             5
 103#define USBCTL1                         0x19
 104#define         VBUS_PIN                                0
 105#define                 USB_FULL_SPEED                          1
 106#define                 USB_HIGH_SPEED                          2
 107#define         GENERATE_RESUME                         3
 108#define         VIRTUAL_ENDPOINT_ENABLE                 4
 109#define FRAME0                          0x1a
 110#define FRAME1                          0x1b
 111#define OURADDR                         0x30
 112#define         FORCE_IMMEDIATE                         7
 113#define USBDIAG                         0x31
 114#define         FORCE_TRANSMIT_CRC_ERROR                0
 115#define         PREVENT_TRANSMIT_BIT_STUFF              1
 116#define         FORCE_RECEIVE_ERROR                     2
 117#define         FAST_TIMES                              4
 118#define USBTEST                         0x32
 119#define         TEST_MODE_SELECT                        0
 120#define                 NORMAL_OPERATION                        0
 121#define                 TEST_J                                  1
 122#define                 TEST_K                                  2
 123#define                 TEST_SE0_NAK                            3
 124#define                 TEST_PACKET                             4
 125#define                 TEST_FORCE_ENABLE                       5
 126#define XCVRDIAG                        0x33
 127#define         FORCE_FULL_SPEED                        2
 128#define         FORCE_HIGH_SPEED                        3
 129#define         OPMODE                                  4
 130#define                 NORMAL_OPERATION                        0
 131#define                 NON_DRIVING                             1
 132#define                 DISABLE_BITSTUFF_AND_NRZI_ENCODE        2
 133#define         LINESTATE                               6
 134#define                 SE0_STATE                               0
 135#define                 J_STATE                                 1
 136#define                 K_STATE                                 2
 137#define                 SE1_STATE                               3
 138#define VIRTOUT0                        0x34
 139#define VIRTOUT1                        0x35
 140#define VIRTIN0                         0x36
 141#define VIRTIN1                         0x37
 142#define SETUP0                          0x40
 143#define SETUP1                          0x41
 144#define SETUP2                          0x42
 145#define SETUP3                          0x43
 146#define SETUP4                          0x44
 147#define SETUP5                          0x45
 148#define SETUP6                          0x46
 149#define SETUP7                          0x47
 150/* Endpoint Registers (Paged via PAGESEL) */
 151#define EP_DATA                         0x05
 152#define EP_STAT0                        0x06
 153#define         DATA_IN_TOKEN_INTERRUPT                 0
 154#define         DATA_OUT_TOKEN_INTERRUPT                1
 155#define         DATA_PACKET_TRANSMITTED_INTERRUPT       2
 156#define         DATA_PACKET_RECEIVED_INTERRUPT          3
 157#define         SHORT_PACKET_TRANSFERRED_INTERRUPT      4
 158#define         NAK_OUT_PACKETS                         5
 159#define         BUFFER_EMPTY                            6
 160#define         BUFFER_FULL                             7
 161#define EP_STAT1                        0x07
 162#define         TIMEOUT                                 0
 163#define         USB_OUT_ACK_SENT                        1
 164#define         USB_OUT_NAK_SENT                        2
 165#define         USB_IN_ACK_RCVD                         3
 166#define         USB_IN_NAK_SENT                         4
 167#define         USB_STALL_SENT                          5
 168#define         LOCAL_OUT_ZLP                           6
 169#define         BUFFER_FLUSH                            7
 170#define EP_TRANSFER0                    0x08
 171#define EP_TRANSFER1                    0x09
 172#define EP_TRANSFER2                    0x0a
 173#define EP_IRQENB                       0x0b
 174#define         DATA_IN_TOKEN_INTERRUPT_ENABLE          0
 175#define         DATA_OUT_TOKEN_INTERRUPT_ENABLE         1
 176#define         DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE        2
 177#define         DATA_PACKET_RECEIVED_INTERRUPT_ENABLE   3
 178#define         SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE       4
 179#define EP_AVAIL0                       0x0c
 180#define EP_AVAIL1                       0x0d
 181#define EP_RSPCLR                       0x0e
 182#define EP_RSPSET                       0x0f
 183#define         ENDPOINT_HALT                           0
 184#define         ENDPOINT_TOGGLE                         1
 185#define         NAK_OUT_PACKETS_MODE                    2
 186#define         CONTROL_STATUS_PHASE_HANDSHAKE          3
 187#define         INTERRUPT_MODE                          4
 188#define         AUTOVALIDATE                            5
 189#define         HIDE_STATUS_PHASE                       6
 190#define         ALT_NAK_OUT_PACKETS                     7
 191#define EP_MAXPKT0                      0x28
 192#define EP_MAXPKT1                      0x29
 193#define         ADDITIONAL_TRANSACTION_OPPORTUNITIES    3
 194#define                 NONE_ADDITIONAL_TRANSACTION             0
 195#define                 ONE_ADDITIONAL_TRANSACTION              1
 196#define                 TWO_ADDITIONAL_TRANSACTION              2
 197#define EP_CFG                          0x2a
 198#define         ENDPOINT_NUMBER                         0
 199#define         ENDPOINT_DIRECTION                      4
 200#define         ENDPOINT_TYPE                           5
 201#define         ENDPOINT_ENABLE                         7
 202#define EP_HBW                          0x2b
 203#define         HIGH_BANDWIDTH_OUT_TRANSACTION_PID      0
 204#define                 DATA0_PID                               0
 205#define                 DATA1_PID                               1
 206#define                 DATA2_PID                               2
 207#define                 MDATA_PID                               3
 208#define EP_BUFF_STATES                  0x2c
 209#define         BUFFER_A_STATE                          0
 210#define         BUFFER_B_STATE                          2
 211#define                 BUFF_FREE                               0
 212#define                 BUFF_VALID                              1
 213#define                 BUFF_LCL                                2
 214#define                 BUFF_USB                                3
 215
 216/*---------------------------------------------------------------------------*/
 217
 218#define PCI_DEVICE_ID_RDK1      0x9054
 219
 220/* PCI-RDK EPLD Registers */
 221#define RDK_EPLD_IO_REGISTER1           0x00000000
 222#define         RDK_EPLD_USB_RESET                              0
 223#define         RDK_EPLD_USB_POWERDOWN                          1
 224#define         RDK_EPLD_USB_WAKEUP                             2
 225#define         RDK_EPLD_USB_EOT                                3
 226#define         RDK_EPLD_DPPULL                                 4
 227#define RDK_EPLD_IO_REGISTER2           0x00000004
 228#define         RDK_EPLD_BUSWIDTH                               0
 229#define         RDK_EPLD_USER                                   2
 230#define         RDK_EPLD_RESET_INTERRUPT_ENABLE                 3
 231#define         RDK_EPLD_DMA_TIMEOUT_ENABLE                     4
 232#define RDK_EPLD_STATUS_REGISTER        0x00000008
 233#define         RDK_EPLD_USB_LRESET                             0
 234#define RDK_EPLD_REVISION_REGISTER      0x0000000c
 235
 236/* PCI-RDK PLX 9054 Registers */
 237#define INTCSR                          0x68
 238#define         PCI_INTERRUPT_ENABLE                            8
 239#define         LOCAL_INTERRUPT_INPUT_ENABLE                    11
 240#define         LOCAL_INPUT_INTERRUPT_ACTIVE                    15
 241#define         LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE            18
 242#define         LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE            19
 243#define         DMA_CHANNEL_0_INTERRUPT_ACTIVE                  21
 244#define         DMA_CHANNEL_1_INTERRUPT_ACTIVE                  22
 245#define CNTRL                           0x6C
 246#define         RELOAD_CONFIGURATION_REGISTERS                  29
 247#define         PCI_ADAPTER_SOFTWARE_RESET                      30
 248#define DMAMODE0                        0x80
 249#define         LOCAL_BUS_WIDTH                                 0
 250#define         INTERNAL_WAIT_STATES                            2
 251#define         TA_READY_INPUT_ENABLE                           6
 252#define         LOCAL_BURST_ENABLE                              8
 253#define         SCATTER_GATHER_MODE                             9
 254#define         DONE_INTERRUPT_ENABLE                           10
 255#define         LOCAL_ADDRESSING_MODE                           11
 256#define         DEMAND_MODE                                     12
 257#define         DMA_EOT_ENABLE                                  14
 258#define         FAST_SLOW_TERMINATE_MODE_SELECT                 15
 259#define         DMA_CHANNEL_INTERRUPT_SELECT                    17
 260#define DMAPADR0                        0x84
 261#define DMALADR0                        0x88
 262#define DMASIZ0                         0x8c
 263#define DMADPR0                         0x90
 264#define         DESCRIPTOR_LOCATION                             0
 265#define         END_OF_CHAIN                                    1
 266#define         INTERRUPT_AFTER_TERMINAL_COUNT                  2
 267#define         DIRECTION_OF_TRANSFER                           3
 268#define DMACSR0                         0xa8
 269#define         CHANNEL_ENABLE                                  0
 270#define         CHANNEL_START                                   1
 271#define         CHANNEL_ABORT                                   2
 272#define         CHANNEL_CLEAR_INTERRUPT                         3
 273#define         CHANNEL_DONE                                    4
 274#define DMATHR                          0xb0
 275#define LBRD1                           0xf8
 276#define         MEMORY_SPACE_LOCAL_BUS_WIDTH                    0
 277#define         W8_BIT                                          0
 278#define         W16_BIT                                         1
 279
 280/* Special OR'ing of INTCSR bits */
 281#define LOCAL_INTERRUPT_TEST \
 282        ((1 << LOCAL_INPUT_INTERRUPT_ACTIVE) | \
 283         (1 << LOCAL_INTERRUPT_INPUT_ENABLE))
 284
 285#define DMA_CHANNEL_0_TEST \
 286        ((1 << DMA_CHANNEL_0_INTERRUPT_ACTIVE) | \
 287         (1 << LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE))
 288
 289#define DMA_CHANNEL_1_TEST \
 290        ((1 << DMA_CHANNEL_1_INTERRUPT_ACTIVE) | \
 291         (1 << LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE))
 292
 293/* EPLD Registers */
 294#define RDK_EPLD_IO_REGISTER1                   0x00000000
 295#define         RDK_EPLD_USB_RESET                      0
 296#define         RDK_EPLD_USB_POWERDOWN                  1
 297#define         RDK_EPLD_USB_WAKEUP                     2
 298#define         RDK_EPLD_USB_EOT                        3
 299#define         RDK_EPLD_DPPULL                         4
 300#define RDK_EPLD_IO_REGISTER2                   0x00000004
 301#define         RDK_EPLD_BUSWIDTH                       0
 302#define         RDK_EPLD_USER                           2
 303#define         RDK_EPLD_RESET_INTERRUPT_ENABLE         3
 304#define         RDK_EPLD_DMA_TIMEOUT_ENABLE             4
 305#define RDK_EPLD_STATUS_REGISTER                0x00000008
 306#define RDK_EPLD_USB_LRESET                             0
 307#define RDK_EPLD_REVISION_REGISTER              0x0000000c
 308
 309#define EPLD_IO_CONTROL_REGISTER                0x400
 310#define         NET2272_RESET                           0
 311#define         BUSWIDTH                                1
 312#define         MPX_MODE                                3
 313#define         USER                                    4
 314#define         DMA_TIMEOUT_ENABLE                      5
 315#define         DMA_CTL_DACK                            6
 316#define         EPLD_DMA_ENABLE                         7
 317#define EPLD_DMA_CONTROL_REGISTER               0x800
 318#define         SPLIT_DMA_MODE                          0
 319#define         SPLIT_DMA_DIRECTION                     1
 320#define         SPLIT_DMA_ENABLE                        2
 321#define         SPLIT_DMA_INTERRUPT_ENABLE              3
 322#define         SPLIT_DMA_INTERRUPT                     4
 323#define         EPLD_DMA_MODE                           5
 324#define         EPLD_DMA_CONTROLLER_ENABLE              7
 325#define SPLIT_DMA_ADDRESS_LOW                   0xc00
 326#define SPLIT_DMA_ADDRESS_HIGH                  0x1000
 327#define SPLIT_DMA_BYTE_COUNT_LOW                0x1400
 328#define SPLIT_DMA_BYTE_COUNT_HIGH               0x1800
 329#define EPLD_REVISION_REGISTER                  0x1c00
 330#define SPLIT_DMA_RAM                           0x4000
 331#define DMA_RAM_SIZE                            0x1000
 332
 333/*---------------------------------------------------------------------------*/
 334
 335#define PCI_DEVICE_ID_RDK2      0x3272
 336
 337/* PCI-RDK version 2 registers */
 338
 339/* Main Control Registers */
 340
 341#define RDK2_IRQENB                     0x00
 342#define RDK2_IRQSTAT                    0x04
 343#define         PB7                             23
 344#define         PB6                             22
 345#define         PB5                             21
 346#define         PB4                             20
 347#define         PB3                             19
 348#define         PB2                             18
 349#define         PB1                             17
 350#define         PB0                             16
 351#define         GP3                             23
 352#define         GP2                             23
 353#define         GP1                             23
 354#define         GP0                             23
 355#define         DMA_RETRY_ABORT                 6
 356#define         DMA_PAUSE_DONE                  5
 357#define         DMA_ABORT_DONE                  4
 358#define         DMA_OUT_FIFO_TRANSFER_DONE      3
 359#define         DMA_LOCAL_DONE                  2
 360#define         DMA_PCI_DONE                    1
 361#define         NET2272_PCI_IRQ                 0
 362
 363#define RDK2_LOCCTLRDK                  0x08
 364#define         CHIP_RESET                      3
 365#define         SPLIT_DMA                       2
 366#define         MULTIPLEX_MODE                  1
 367#define         BUS_WIDTH                       0
 368
 369#define RDK2_GPIOCTL                    0x10
 370#define         GP3_OUT_ENABLE                                  7
 371#define         GP2_OUT_ENABLE                                  6
 372#define         GP1_OUT_ENABLE                                  5
 373#define         GP0_OUT_ENABLE                                  4
 374#define         GP3_DATA                                        3
 375#define         GP2_DATA                                        2
 376#define         GP1_DATA                                        1
 377#define         GP0_DATA                                        0
 378
 379#define RDK2_LEDSW                      0x14
 380#define         LED3                            27
 381#define         LED2                            26
 382#define         LED1                            25
 383#define         LED0                            24
 384#define         PBUTTON                         16
 385#define         DIPSW                           0
 386
 387#define RDK2_DIAG                       0x18
 388#define         RDK2_FAST_TIMES                         2
 389#define         FORCE_PCI_SERR                          1
 390#define         FORCE_PCI_INT                           0
 391#define RDK2_FPGAREV                    0x1C
 392
 393/* Dma Control registers */
 394#define RDK2_DMACTL                     0x80
 395#define         ADDR_HOLD                               24
 396#define         RETRY_COUNT                             16      /* 23:16 */
 397#define         FIFO_THRESHOLD                          11      /* 15:11 */
 398#define         MEM_WRITE_INVALIDATE                    10
 399#define         READ_MULTIPLE                           9
 400#define         READ_LINE                               8
 401#define         RDK2_DMA_MODE                           6       /* 7:6 */
 402#define         CONTROL_DACK                            5
 403#define         EOT_ENABLE                              4
 404#define         EOT_POLARITY                            3
 405#define         DACK_POLARITY                           2
 406#define         DREQ_POLARITY                           1
 407#define         DMA_ENABLE                              0
 408
 409#define RDK2_DMASTAT                    0x84
 410#define         GATHER_COUNT                            12      /* 14:12 */
 411#define         FIFO_COUNT                              6       /* 11:6 */
 412#define         FIFO_FLUSH                              5
 413#define         FIFO_TRANSFER                           4
 414#define         PAUSE_DONE                              3
 415#define         ABORT_DONE                              2
 416#define         DMA_ABORT                               1
 417#define         DMA_START                               0
 418
 419#define RDK2_DMAPCICOUNT                0x88
 420#define         DMA_DIRECTION                           31
 421#define         DMA_PCI_BYTE_COUNT                      0       /* 0:23 */
 422
 423#define RDK2_DMALOCCOUNT                0x8C    /* 0:23 dma local byte count */
 424
 425#define RDK2_DMAADDR                    0x90    /* 2:31 PCI bus starting address */
 426
 427/*---------------------------------------------------------------------------*/
 428
 429#define REG_INDEXED_THRESHOLD   (1 << 5)
 430
 431/* DRIVER DATA STRUCTURES and UTILITIES */
 432struct net2272_ep {
 433        struct usb_ep ep;
 434        struct net2272 *dev;
 435        unsigned long irqs;
 436
 437        /* analogous to a host-side qh */
 438        struct list_head queue;
 439        const struct usb_endpoint_descriptor *desc;
 440        unsigned num:8,
 441                 fifo_size:12,
 442                 stopped:1,
 443                 wedged:1,
 444                 is_in:1,
 445                 is_iso:1,
 446                 dma:1,
 447                 not_empty:1;
 448};
 449
 450struct net2272 {
 451        /* each device provides one gadget, several endpoints */
 452        struct usb_gadget gadget;
 453        struct device *dev;
 454        unsigned short dev_id;
 455
 456        spinlock_t lock;
 457        struct net2272_ep ep[4];
 458        struct usb_gadget_driver *driver;
 459        unsigned protocol_stall:1,
 460                 softconnect:1,
 461                 wakeup:1,
 462                 dma_eot_polarity:1,
 463                 dma_dack_polarity:1,
 464                 dma_dreq_polarity:1,
 465                 dma_busy:1;
 466        u16 chiprev;
 467        u8 pagesel;
 468
 469        unsigned int irq;
 470        unsigned short fifo_mode;
 471
 472        unsigned int base_shift;
 473        u16 __iomem *base_addr;
 474        union {
 475#ifdef CONFIG_USB_PCI
 476                struct {
 477                        void __iomem *plx9054_base_addr;
 478                        void __iomem *epld_base_addr;
 479                } rdk1;
 480                struct {
 481                        /* Bar0, Bar1 is base_addr both mem-mapped */
 482                        void __iomem *fpga_base_addr;
 483                } rdk2;
 484#endif
 485        };
 486};
 487
 488static void __iomem *
 489net2272_reg_addr(struct net2272 *dev, unsigned int reg)
 490{
 491        return dev->base_addr + (reg << dev->base_shift);
 492}
 493
 494static void
 495net2272_write(struct net2272 *dev, unsigned int reg, u8 value)
 496{
 497        if (reg >= REG_INDEXED_THRESHOLD) {
 498                /*
 499                 * Indexed register; use REGADDRPTR/REGDATA
 500                 *  - Save and restore REGADDRPTR. This prevents REGADDRPTR from
 501                 *    changes between other code sections, but it is time consuming.
 502                 *  - Performance tips: either do not save and restore REGADDRPTR (if it
 503                 *    is safe) or do save/restore operations only in critical sections.
 504                u8 tmp = readb(dev->base_addr + REGADDRPTR);
 505                 */
 506                writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
 507                writeb(value, net2272_reg_addr(dev, REGDATA));
 508                /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
 509        } else
 510                writeb(value, net2272_reg_addr(dev, reg));
 511}
 512
 513static u8
 514net2272_read(struct net2272 *dev, unsigned int reg)
 515{
 516        u8 ret;
 517
 518        if (reg >= REG_INDEXED_THRESHOLD) {
 519                /*
 520                 * Indexed register; use REGADDRPTR/REGDATA
 521                 *  - Save and restore REGADDRPTR. This prevents REGADDRPTR from
 522                 *    changes between other code sections, but it is time consuming.
 523                 *  - Performance tips: either do not save and restore REGADDRPTR (if it
 524                 *    is safe) or do save/restore operations only in critical sections.
 525                u8 tmp = readb(dev->base_addr + REGADDRPTR);
 526                 */
 527                writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
 528                ret = readb(net2272_reg_addr(dev, REGDATA));
 529                /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
 530        } else
 531                ret = readb(net2272_reg_addr(dev, reg));
 532
 533        return ret;
 534}
 535
 536static void
 537net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value)
 538{
 539        struct net2272 *dev = ep->dev;
 540
 541        if (dev->pagesel != ep->num) {
 542                net2272_write(dev, PAGESEL, ep->num);
 543                dev->pagesel = ep->num;
 544        }
 545        net2272_write(dev, reg, value);
 546}
 547
 548static u8
 549net2272_ep_read(struct net2272_ep *ep, unsigned int reg)
 550{
 551        struct net2272 *dev = ep->dev;
 552
 553        if (dev->pagesel != ep->num) {
 554                net2272_write(dev, PAGESEL, ep->num);
 555                dev->pagesel = ep->num;
 556        }
 557        return net2272_read(dev, reg);
 558}
 559
 560static void allow_status(struct net2272_ep *ep)
 561{
 562        /* ep0 only */
 563        net2272_ep_write(ep, EP_RSPCLR,
 564                (1 << CONTROL_STATUS_PHASE_HANDSHAKE) |
 565                (1 << ALT_NAK_OUT_PACKETS) |
 566                (1 << NAK_OUT_PACKETS_MODE));
 567        ep->stopped = 1;
 568}
 569
 570static void set_halt(struct net2272_ep *ep)
 571{
 572        /* ep0 and bulk/intr endpoints */
 573        net2272_ep_write(ep, EP_RSPCLR, 1 << CONTROL_STATUS_PHASE_HANDSHAKE);
 574        net2272_ep_write(ep, EP_RSPSET, 1 << ENDPOINT_HALT);
 575}
 576
 577static void clear_halt(struct net2272_ep *ep)
 578{
 579        /* ep0 and bulk/intr endpoints */
 580        net2272_ep_write(ep, EP_RSPCLR,
 581                (1 << ENDPOINT_HALT) | (1 << ENDPOINT_TOGGLE));
 582}
 583
 584/* count (<= 4) bytes in the next fifo write will be valid */
 585static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count)
 586{
 587        /* net2272_ep_write will truncate to u8 for us */
 588        net2272_ep_write(ep, EP_TRANSFER2, count >> 16);
 589        net2272_ep_write(ep, EP_TRANSFER1, count >> 8);
 590        net2272_ep_write(ep, EP_TRANSFER0, count);
 591}
 592
 593struct net2272_request {
 594        struct usb_request req;
 595        struct list_head queue;
 596        unsigned mapped:1,
 597                 valid:1;
 598};
 599
 600#endif
 601