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27#include <linux/device.h>
28#include <linux/interrupt.h>
29#include <linux/platform_device.h>
30#include <linux/dma-mapping.h>
31#include <linux/dmaengine.h>
32#include <linux/pfn.h>
33#include <linux/sizes.h>
34#include <linux/platform_data/usb-musb-ux500.h>
35#include "musb_core.h"
36
37static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
38 "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
39static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
40 "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
41
42struct ux500_dma_channel {
43 struct dma_channel channel;
44 struct ux500_dma_controller *controller;
45 struct musb_hw_ep *hw_ep;
46 struct dma_chan *dma_chan;
47 unsigned int cur_len;
48 dma_cookie_t cookie;
49 u8 ch_num;
50 u8 is_tx;
51 u8 is_allocated;
52};
53
54struct ux500_dma_controller {
55 struct dma_controller controller;
56 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
57 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
58 void *private_data;
59 dma_addr_t phy_base;
60};
61
62
63static void ux500_dma_callback(void *private_data)
64{
65 struct dma_channel *channel = private_data;
66 struct ux500_dma_channel *ux500_channel = channel->private_data;
67 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
68 struct musb *musb = hw_ep->musb;
69 unsigned long flags;
70
71 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n",
72 hw_ep->epnum);
73
74 spin_lock_irqsave(&musb->lock, flags);
75 ux500_channel->channel.actual_len = ux500_channel->cur_len;
76 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
77 musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx);
78 spin_unlock_irqrestore(&musb->lock, flags);
79
80}
81
82static bool ux500_configure_channel(struct dma_channel *channel,
83 u16 packet_sz, u8 mode,
84 dma_addr_t dma_addr, u32 len)
85{
86 struct ux500_dma_channel *ux500_channel = channel->private_data;
87 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
88 struct dma_chan *dma_chan = ux500_channel->dma_chan;
89 struct dma_async_tx_descriptor *dma_desc;
90 enum dma_transfer_direction direction;
91 struct scatterlist sg;
92 struct dma_slave_config slave_conf;
93 enum dma_slave_buswidth addr_width;
94 struct musb *musb = ux500_channel->controller->private_data;
95 dma_addr_t usb_fifo_addr = (musb->io.fifo_offset(hw_ep->epnum) +
96 ux500_channel->controller->phy_base);
97
98 dev_dbg(musb->controller,
99 "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
100 packet_sz, mode, (unsigned long long) dma_addr,
101 len, ux500_channel->is_tx);
102
103 ux500_channel->cur_len = len;
104
105 sg_init_table(&sg, 1);
106 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
107 offset_in_page(dma_addr));
108 sg_dma_address(&sg) = dma_addr;
109 sg_dma_len(&sg) = len;
110
111 direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
112 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
113 DMA_SLAVE_BUSWIDTH_4_BYTES;
114
115 slave_conf.direction = direction;
116 slave_conf.src_addr = usb_fifo_addr;
117 slave_conf.src_addr_width = addr_width;
118 slave_conf.src_maxburst = 16;
119 slave_conf.dst_addr = usb_fifo_addr;
120 slave_conf.dst_addr_width = addr_width;
121 slave_conf.dst_maxburst = 16;
122 slave_conf.device_fc = false;
123
124 dmaengine_slave_config(dma_chan, &slave_conf);
125
126 dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction,
127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
128 if (!dma_desc)
129 return false;
130
131 dma_desc->callback = ux500_dma_callback;
132 dma_desc->callback_param = channel;
133 ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
134
135 dma_async_issue_pending(dma_chan);
136
137 return true;
138}
139
140static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
141 struct musb_hw_ep *hw_ep, u8 is_tx)
142{
143 struct ux500_dma_controller *controller = container_of(c,
144 struct ux500_dma_controller, controller);
145 struct ux500_dma_channel *ux500_channel = NULL;
146 struct musb *musb = controller->private_data;
147 u8 ch_num = hw_ep->epnum - 1;
148
149
150
151
152
153 if (ch_num > 7)
154 ch_num -= 8;
155
156 if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
157 return NULL;
158
159 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
160 &(controller->rx_channel[ch_num]) ;
161
162
163 if (ux500_channel->is_allocated)
164 return NULL;
165
166 ux500_channel->hw_ep = hw_ep;
167 ux500_channel->is_allocated = 1;
168
169 dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
170 hw_ep->epnum, is_tx, ch_num);
171
172 return &(ux500_channel->channel);
173}
174
175static void ux500_dma_channel_release(struct dma_channel *channel)
176{
177 struct ux500_dma_channel *ux500_channel = channel->private_data;
178 struct musb *musb = ux500_channel->controller->private_data;
179
180 dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num);
181
182 if (ux500_channel->is_allocated) {
183 ux500_channel->is_allocated = 0;
184 channel->status = MUSB_DMA_STATUS_FREE;
185 channel->actual_len = 0;
186 }
187}
188
189static int ux500_dma_is_compatible(struct dma_channel *channel,
190 u16 maxpacket, void *buf, u32 length)
191{
192 if ((maxpacket & 0x3) ||
193 ((unsigned long int) buf & 0x3) ||
194 (length < 512) ||
195 (length & 0x3))
196 return false;
197 else
198 return true;
199}
200
201static int ux500_dma_channel_program(struct dma_channel *channel,
202 u16 packet_sz, u8 mode,
203 dma_addr_t dma_addr, u32 len)
204{
205 int ret;
206
207 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
208 channel->status == MUSB_DMA_STATUS_BUSY);
209
210 channel->status = MUSB_DMA_STATUS_BUSY;
211 channel->actual_len = 0;
212 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
213 if (!ret)
214 channel->status = MUSB_DMA_STATUS_FREE;
215
216 return ret;
217}
218
219static int ux500_dma_channel_abort(struct dma_channel *channel)
220{
221 struct ux500_dma_channel *ux500_channel = channel->private_data;
222 struct ux500_dma_controller *controller = ux500_channel->controller;
223 struct musb *musb = controller->private_data;
224 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
225 u16 csr;
226
227 dev_dbg(musb->controller, "channel=%d, is_tx=%d\n",
228 ux500_channel->ch_num, ux500_channel->is_tx);
229
230 if (channel->status == MUSB_DMA_STATUS_BUSY) {
231 if (ux500_channel->is_tx) {
232 csr = musb_readw(epio, MUSB_TXCSR);
233 csr &= ~(MUSB_TXCSR_AUTOSET |
234 MUSB_TXCSR_DMAENAB |
235 MUSB_TXCSR_DMAMODE);
236 musb_writew(epio, MUSB_TXCSR, csr);
237 } else {
238 csr = musb_readw(epio, MUSB_RXCSR);
239 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
240 MUSB_RXCSR_DMAENAB |
241 MUSB_RXCSR_DMAMODE);
242 musb_writew(epio, MUSB_RXCSR, csr);
243 }
244
245 dmaengine_terminate_all(ux500_channel->dma_chan);
246 channel->status = MUSB_DMA_STATUS_FREE;
247 }
248 return 0;
249}
250
251static void ux500_dma_controller_stop(struct ux500_dma_controller *controller)
252{
253 struct ux500_dma_channel *ux500_channel;
254 struct dma_channel *channel;
255 u8 ch_num;
256
257 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
258 channel = &controller->rx_channel[ch_num].channel;
259 ux500_channel = channel->private_data;
260
261 ux500_dma_channel_release(channel);
262
263 if (ux500_channel->dma_chan)
264 dma_release_channel(ux500_channel->dma_chan);
265 }
266
267 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
268 channel = &controller->tx_channel[ch_num].channel;
269 ux500_channel = channel->private_data;
270
271 ux500_dma_channel_release(channel);
272
273 if (ux500_channel->dma_chan)
274 dma_release_channel(ux500_channel->dma_chan);
275 }
276}
277
278static int ux500_dma_controller_start(struct ux500_dma_controller *controller)
279{
280 struct ux500_dma_channel *ux500_channel = NULL;
281 struct musb *musb = controller->private_data;
282 struct device *dev = musb->controller;
283 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
284 struct ux500_musb_board_data *data;
285 struct dma_channel *dma_channel = NULL;
286 char **chan_names;
287 u32 ch_num;
288 u8 dir;
289 u8 is_tx = 0;
290
291 void **param_array;
292 struct ux500_dma_channel *channel_array;
293 dma_cap_mask_t mask;
294
295 if (!plat) {
296 dev_err(musb->controller, "No platform data\n");
297 return -EINVAL;
298 }
299
300 data = plat->board_data;
301
302 dma_cap_zero(mask);
303 dma_cap_set(DMA_SLAVE, mask);
304
305
306 channel_array = controller->rx_channel;
307 param_array = data ? data->dma_rx_param_array : NULL;
308 chan_names = (char **)iep_chan_names;
309
310 for (dir = 0; dir < 2; dir++) {
311 for (ch_num = 0;
312 ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
313 ch_num++) {
314 ux500_channel = &channel_array[ch_num];
315 ux500_channel->controller = controller;
316 ux500_channel->ch_num = ch_num;
317 ux500_channel->is_tx = is_tx;
318
319 dma_channel = &(ux500_channel->channel);
320 dma_channel->private_data = ux500_channel;
321 dma_channel->status = MUSB_DMA_STATUS_FREE;
322 dma_channel->max_len = SZ_16M;
323
324 ux500_channel->dma_chan =
325 dma_request_slave_channel(dev, chan_names[ch_num]);
326
327 if (!ux500_channel->dma_chan)
328 ux500_channel->dma_chan =
329 dma_request_channel(mask,
330 data ?
331 data->dma_filter :
332 NULL,
333 param_array ?
334 param_array[ch_num] :
335 NULL);
336
337 if (!ux500_channel->dma_chan) {
338 ERR("Dma pipe allocation error dir=%d ch=%d\n",
339 dir, ch_num);
340
341
342 ux500_dma_controller_stop(controller);
343
344 return -EBUSY;
345 }
346
347 }
348
349
350 channel_array = controller->tx_channel;
351 param_array = data ? data->dma_tx_param_array : NULL;
352 chan_names = (char **)oep_chan_names;
353 is_tx = 1;
354 }
355
356 return 0;
357}
358
359void ux500_dma_controller_destroy(struct dma_controller *c)
360{
361 struct ux500_dma_controller *controller = container_of(c,
362 struct ux500_dma_controller, controller);
363
364 ux500_dma_controller_stop(controller);
365 kfree(controller);
366}
367EXPORT_SYMBOL_GPL(ux500_dma_controller_destroy);
368
369struct dma_controller *
370ux500_dma_controller_create(struct musb *musb, void __iomem *base)
371{
372 struct ux500_dma_controller *controller;
373 struct platform_device *pdev = to_platform_device(musb->controller);
374 struct resource *iomem;
375 int ret;
376
377 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
378 if (!controller)
379 goto kzalloc_fail;
380
381 controller->private_data = musb;
382
383
384 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385 if (!iomem) {
386 dev_err(musb->controller, "no memory resource defined\n");
387 goto plat_get_fail;
388 }
389
390 controller->phy_base = (dma_addr_t) iomem->start;
391
392 controller->controller.channel_alloc = ux500_dma_channel_allocate;
393 controller->controller.channel_release = ux500_dma_channel_release;
394 controller->controller.channel_program = ux500_dma_channel_program;
395 controller->controller.channel_abort = ux500_dma_channel_abort;
396 controller->controller.is_compatible = ux500_dma_is_compatible;
397
398 ret = ux500_dma_controller_start(controller);
399 if (ret)
400 goto plat_get_fail;
401 return &controller->controller;
402
403plat_get_fail:
404 kfree(controller);
405kzalloc_fail:
406 return NULL;
407}
408EXPORT_SYMBOL_GPL(ux500_dma_controller_create);
409
