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13#ifndef __SOC_ZYNQMP_FIRMWARE_H__
14#define __SOC_ZYNQMP_FIRMWARE_H__
15
16#include <linux/device.h>
17
18#define ZYNQMP_PM_VERSION_MAJOR 1
19#define ZYNQMP_PM_VERSION_MINOR 0
20
21#define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24#define ZYNQMP_TZ_VERSION_MAJOR 1
25#define ZYNQMP_TZ_VERSION_MINOR 0
26
27#define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30#define ZYNQMP_PM_MAX_LATENCY (~0U)
31#define ZYNQMP_PM_MAX_QOS 100U
32
33
34#define PM_SIP_SVC 0xC2000000
35#define PM_SET_SUSPEND_MODE 0xa02
36#define PM_GET_TRUSTZONE_VERSION 0xa03
37
38
39#define PAYLOAD_ARG_CNT 5U
40
41
42#define CB_ARG_CNT 4
43
44
45#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
46
47
48#define PM_USAGE_NO_MASTER 0x0U
49#define PM_USAGE_CURRENT_MASTER 0x1U
50#define PM_USAGE_OTHER_MASTER 0x2U
51#define PM_USAGE_BOTH_MASTERS (PM_USAGE_CURRENT_MASTER | \
52 PM_USAGE_OTHER_MASTER)
53
54
55#define GGS_BASEADDR (0xFFD80030U)
56#define GSS_NUM_REGS (4)
57
58
59#define PGGS_BASEADDR (0xFFD80050U)
60#define PGSS_NUM_REGS (4)
61
62
63#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
64#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
65#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
66#define ZYNQMP_PM_CAPABILITY_POWER 0x8U
67
68
69#define CLK_GET_NAME_RESP_LEN 16
70#define CLK_GET_TOPOLOGY_RESP_WORDS 3
71#define CLK_GET_FIXEDFACTOR_RESP_WORDS 2
72#define CLK_GET_PARENTS_RESP_WORDS 3
73#define CLK_GET_ATTR_RESP_WORDS 1
74
75enum pm_api_id {
76
77 PM_GET_API_VERSION = 1,
78 PM_SET_CONFIGURATION,
79 PM_GET_NODE_STATUS,
80 PM_GET_OPERATING_CHARACTERISTIC,
81 PM_REGISTER_NOTIFIER,
82
83 PM_REQUEST_SUSPEND,
84 PM_SELF_SUSPEND,
85 PM_FORCE_POWERDOWN,
86 PM_ABORT_SUSPEND,
87 PM_REQUEST_WAKEUP,
88 PM_SET_WAKEUP_SOURCE,
89 PM_SYSTEM_SHUTDOWN,
90
91 PM_REQUEST_NODE,
92 PM_RELEASE_NODE,
93 PM_SET_REQUIREMENT,
94 PM_SET_MAX_LATENCY,
95
96 PM_RESET_ASSERT,
97 PM_RESET_GET_STATUS,
98 PM_MMIO_WRITE,
99 PM_MMIO_READ,
100 PM_PM_INIT_FINALIZE,
101 PM_FPGA_LOAD,
102 PM_FPGA_GET_STATUS,
103 PM_GET_CHIPID,
104
105
106 PM_SECURE_SHA = 26,
107 PM_SECURE_RSA,
108
109 PM_PINCTRL_REQUEST,
110 PM_PINCTRL_RELEASE,
111 PM_PINCTRL_GET_FUNCTION,
112 PM_PINCTRL_SET_FUNCTION,
113 PM_PINCTRL_CONFIG_PARAM_GET,
114 PM_PINCTRL_CONFIG_PARAM_SET,
115
116 PM_IOCTL,
117
118 PM_QUERY_DATA,
119
120 PM_CLOCK_ENABLE,
121 PM_CLOCK_DISABLE,
122 PM_CLOCK_GETSTATE,
123 PM_CLOCK_SETDIVIDER,
124 PM_CLOCK_GETDIVIDER,
125 PM_CLOCK_SETRATE,
126 PM_CLOCK_GETRATE,
127 PM_CLOCK_SETPARENT,
128 PM_CLOCK_GETPARENT,
129};
130
131
132enum pm_ret_status {
133 XST_PM_SUCCESS = 0,
134 XST_PM_INTERNAL = 2000,
135 XST_PM_CONFLICT,
136 XST_PM_NO_ACCESS,
137 XST_PM_INVALID_NODE,
138 XST_PM_DOUBLE_REQ,
139 XST_PM_ABORT_SUSPEND,
140};
141
142enum zynqmp_pm_reset_action {
143 PM_RESET_ACTION_RELEASE,
144 PM_RESET_ACTION_ASSERT,
145 PM_RESET_ACTION_PULSE,
146};
147
148enum zynqmp_pm_reset {
149 ZYNQMP_PM_RESET_START = 999,
150 ZYNQMP_PM_RESET_PCIE_CFG,
151 ZYNQMP_PM_RESET_PCIE_BRIDGE,
152 ZYNQMP_PM_RESET_PCIE_CTRL,
153 ZYNQMP_PM_RESET_DP,
154 ZYNQMP_PM_RESET_SWDT_CRF,
155 ZYNQMP_PM_RESET_AFI_FM5,
156 ZYNQMP_PM_RESET_AFI_FM4,
157 ZYNQMP_PM_RESET_AFI_FM3,
158 ZYNQMP_PM_RESET_AFI_FM2,
159 ZYNQMP_PM_RESET_AFI_FM1,
160 ZYNQMP_PM_RESET_AFI_FM0,
161 ZYNQMP_PM_RESET_GDMA,
162 ZYNQMP_PM_RESET_GPU_PP1,
163 ZYNQMP_PM_RESET_GPU_PP0,
164 ZYNQMP_PM_RESET_GPU,
165 ZYNQMP_PM_RESET_GT,
166 ZYNQMP_PM_RESET_SATA,
167 ZYNQMP_PM_RESET_ACPU3_PWRON,
168 ZYNQMP_PM_RESET_ACPU2_PWRON,
169 ZYNQMP_PM_RESET_ACPU1_PWRON,
170 ZYNQMP_PM_RESET_ACPU0_PWRON,
171 ZYNQMP_PM_RESET_APU_L2,
172 ZYNQMP_PM_RESET_ACPU3,
173 ZYNQMP_PM_RESET_ACPU2,
174 ZYNQMP_PM_RESET_ACPU1,
175 ZYNQMP_PM_RESET_ACPU0,
176 ZYNQMP_PM_RESET_DDR,
177 ZYNQMP_PM_RESET_APM_FPD,
178 ZYNQMP_PM_RESET_SOFT,
179 ZYNQMP_PM_RESET_GEM0,
180 ZYNQMP_PM_RESET_GEM1,
181 ZYNQMP_PM_RESET_GEM2,
182 ZYNQMP_PM_RESET_GEM3,
183 ZYNQMP_PM_RESET_QSPI,
184 ZYNQMP_PM_RESET_UART0,
185 ZYNQMP_PM_RESET_UART1,
186 ZYNQMP_PM_RESET_SPI0,
187 ZYNQMP_PM_RESET_SPI1,
188 ZYNQMP_PM_RESET_SDIO0,
189 ZYNQMP_PM_RESET_SDIO1,
190 ZYNQMP_PM_RESET_CAN0,
191 ZYNQMP_PM_RESET_CAN1,
192 ZYNQMP_PM_RESET_I2C0,
193 ZYNQMP_PM_RESET_I2C1,
194 ZYNQMP_PM_RESET_TTC0,
195 ZYNQMP_PM_RESET_TTC1,
196 ZYNQMP_PM_RESET_TTC2,
197 ZYNQMP_PM_RESET_TTC3,
198 ZYNQMP_PM_RESET_SWDT_CRL,
199 ZYNQMP_PM_RESET_NAND,
200 ZYNQMP_PM_RESET_ADMA,
201 ZYNQMP_PM_RESET_GPIO,
202 ZYNQMP_PM_RESET_IOU_CC,
203 ZYNQMP_PM_RESET_TIMESTAMP,
204 ZYNQMP_PM_RESET_RPU_R50,
205 ZYNQMP_PM_RESET_RPU_R51,
206 ZYNQMP_PM_RESET_RPU_AMBA,
207 ZYNQMP_PM_RESET_OCM,
208 ZYNQMP_PM_RESET_RPU_PGE,
209 ZYNQMP_PM_RESET_USB0_CORERESET,
210 ZYNQMP_PM_RESET_USB1_CORERESET,
211 ZYNQMP_PM_RESET_USB0_HIBERRESET,
212 ZYNQMP_PM_RESET_USB1_HIBERRESET,
213 ZYNQMP_PM_RESET_USB0_APB,
214 ZYNQMP_PM_RESET_USB1_APB,
215 ZYNQMP_PM_RESET_IPI,
216 ZYNQMP_PM_RESET_APM_LPD,
217 ZYNQMP_PM_RESET_RTC,
218 ZYNQMP_PM_RESET_SYSMON,
219 ZYNQMP_PM_RESET_AFI_FM6,
220 ZYNQMP_PM_RESET_LPD_SWDT,
221 ZYNQMP_PM_RESET_FPD,
222 ZYNQMP_PM_RESET_RPU_DBG1,
223 ZYNQMP_PM_RESET_RPU_DBG0,
224 ZYNQMP_PM_RESET_DBG_LPD,
225 ZYNQMP_PM_RESET_DBG_FPD,
226 ZYNQMP_PM_RESET_APLL,
227 ZYNQMP_PM_RESET_DPLL,
228 ZYNQMP_PM_RESET_VPLL,
229 ZYNQMP_PM_RESET_IOPLL,
230 ZYNQMP_PM_RESET_RPLL,
231 ZYNQMP_PM_RESET_GPO3_PL_0,
232 ZYNQMP_PM_RESET_GPO3_PL_1,
233 ZYNQMP_PM_RESET_GPO3_PL_2,
234 ZYNQMP_PM_RESET_GPO3_PL_3,
235 ZYNQMP_PM_RESET_GPO3_PL_4,
236 ZYNQMP_PM_RESET_GPO3_PL_5,
237 ZYNQMP_PM_RESET_GPO3_PL_6,
238 ZYNQMP_PM_RESET_GPO3_PL_7,
239 ZYNQMP_PM_RESET_GPO3_PL_8,
240 ZYNQMP_PM_RESET_GPO3_PL_9,
241 ZYNQMP_PM_RESET_GPO3_PL_10,
242 ZYNQMP_PM_RESET_GPO3_PL_11,
243 ZYNQMP_PM_RESET_GPO3_PL_12,
244 ZYNQMP_PM_RESET_GPO3_PL_13,
245 ZYNQMP_PM_RESET_GPO3_PL_14,
246 ZYNQMP_PM_RESET_GPO3_PL_15,
247 ZYNQMP_PM_RESET_GPO3_PL_16,
248 ZYNQMP_PM_RESET_GPO3_PL_17,
249 ZYNQMP_PM_RESET_GPO3_PL_18,
250 ZYNQMP_PM_RESET_GPO3_PL_19,
251 ZYNQMP_PM_RESET_GPO3_PL_20,
252 ZYNQMP_PM_RESET_GPO3_PL_21,
253 ZYNQMP_PM_RESET_GPO3_PL_22,
254 ZYNQMP_PM_RESET_GPO3_PL_23,
255 ZYNQMP_PM_RESET_GPO3_PL_24,
256 ZYNQMP_PM_RESET_GPO3_PL_25,
257 ZYNQMP_PM_RESET_GPO3_PL_26,
258 ZYNQMP_PM_RESET_GPO3_PL_27,
259 ZYNQMP_PM_RESET_GPO3_PL_28,
260 ZYNQMP_PM_RESET_GPO3_PL_29,
261 ZYNQMP_PM_RESET_GPO3_PL_30,
262 ZYNQMP_PM_RESET_GPO3_PL_31,
263 ZYNQMP_PM_RESET_RPU_LS,
264 ZYNQMP_PM_RESET_PS_ONLY,
265 ZYNQMP_PM_RESET_PL,
266 ZYNQMP_PM_RESET_PS_PL0,
267 ZYNQMP_PM_RESET_PS_PL1,
268 ZYNQMP_PM_RESET_PS_PL2,
269 ZYNQMP_PM_RESET_PS_PL3,
270 ZYNQMP_PM_RESET_END
271};
272
273enum zynqmp_pm_request_ack {
274 ZYNQMP_PM_REQUEST_ACK_NO = 1,
275 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
276 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
277};
278
279enum zynqmp_pm_abort_reason {
280 ZYNQMP_PM_ABORT_REASON_WAKEUP_EVENT = 100,
281 ZYNQMP_PM_ABORT_REASON_POWER_UNIT_BUSY,
282 ZYNQMP_PM_ABORT_REASON_NO_POWERDOWN,
283 ZYNQMP_PM_ABORT_REASON_UNKNOWN,
284};
285
286enum zynqmp_pm_suspend_reason {
287 ZYNQMP_PM_SUSPEND_REASON_POWER_UNIT_REQUEST = 201,
288 ZYNQMP_PM_SUSPEND_REASON_ALERT,
289 ZYNQMP_PM_SUSPEND_REASON_SYSTEM_SHUTDOWN,
290};
291
292enum zynqmp_pm_ram_state {
293 ZYNQMP_PM_RAM_STATE_OFF = 1,
294 ZYNQMP_PM_RAM_STATE_RETENTION,
295 ZYNQMP_PM_RAM_STATE_ON,
296};
297
298enum zynqmp_pm_opchar_type {
299 ZYNQMP_PM_OPERATING_CHARACTERISTIC_POWER = 1,
300 ZYNQMP_PM_OPERATING_CHARACTERISTIC_ENERGY,
301 ZYNQMP_PM_OPERATING_CHARACTERISTIC_TEMPERATURE,
302};
303
304enum zynqmp_pm_shutdown_type {
305 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
306 ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
307 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
308};
309
310enum zynqmp_pm_shutdown_subtype {
311 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
312 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
313 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
314};
315
316enum pm_node_id {
317 NODE_UNKNOWN = 0,
318 NODE_APU,
319 NODE_APU_0,
320 NODE_APU_1,
321 NODE_APU_2,
322 NODE_APU_3,
323 NODE_RPU,
324 NODE_RPU_0,
325 NODE_RPU_1,
326 NODE_PLD,
327 NODE_FPD,
328 NODE_OCM_BANK_0,
329 NODE_OCM_BANK_1,
330 NODE_OCM_BANK_2,
331 NODE_OCM_BANK_3,
332 NODE_TCM_0_A,
333 NODE_TCM_0_B,
334 NODE_TCM_1_A,
335 NODE_TCM_1_B,
336 NODE_L2,
337 NODE_GPU_PP_0,
338 NODE_GPU_PP_1,
339 NODE_USB_0,
340 NODE_USB_1,
341 NODE_TTC_0,
342 NODE_TTC_1,
343 NODE_TTC_2,
344 NODE_TTC_3,
345 NODE_SATA,
346 NODE_ETH_0,
347 NODE_ETH_1,
348 NODE_ETH_2,
349 NODE_ETH_3,
350 NODE_UART_0,
351 NODE_UART_1,
352 NODE_SPI_0,
353 NODE_SPI_1,
354 NODE_I2C_0,
355 NODE_I2C_1,
356 NODE_SD_0,
357 NODE_SD_1,
358 NODE_DP,
359 NODE_GDMA,
360 NODE_ADMA,
361 NODE_NAND,
362 NODE_QSPI,
363 NODE_GPIO,
364 NODE_CAN_0,
365 NODE_CAN_1,
366 NODE_EXTERN,
367 NODE_APLL,
368 NODE_VPLL,
369 NODE_DPLL,
370 NODE_RPLL,
371 NODE_IOPLL,
372 NODE_DDR,
373 NODE_IPI_APU,
374 NODE_IPI_RPU_0,
375 NODE_GPU,
376 NODE_PCIE,
377 NODE_PCAP,
378 NODE_RTC,
379 NODE_LPD,
380 NODE_VCU,
381 NODE_IPI_RPU_1,
382 NODE_IPI_PL_0,
383 NODE_IPI_PL_1,
384 NODE_IPI_PL_2,
385 NODE_IPI_PL_3,
386 NODE_PL,
387 NODE_GEM_TSU,
388 NODE_SWDT_0,
389 NODE_SWDT_1,
390 NODE_CSU,
391 NODE_PJTAG,
392 NODE_TRACE,
393 NODE_TESTSCAN,
394 NODE_PMU,
395 NODE_MAX,
396};
397
398enum pm_pinctrl_config_param {
399 PM_PINCTRL_CONFIG_SLEW_RATE,
400 PM_PINCTRL_CONFIG_BIAS_STATUS,
401 PM_PINCTRL_CONFIG_PULL_CTRL,
402 PM_PINCTRL_CONFIG_SCHMITT_CMOS,
403 PM_PINCTRL_CONFIG_DRIVE_STRENGTH,
404 PM_PINCTRL_CONFIG_VOLTAGE_STATUS,
405 PM_PINCTRL_CONFIG_MAX,
406};
407
408enum pm_pinctrl_slew_rate {
409 PM_PINCTRL_SLEW_RATE_FAST,
410 PM_PINCTRL_SLEW_RATE_SLOW,
411};
412
413enum pm_pinctrl_bias_status {
414 PM_PINCTRL_BIAS_DISABLE,
415 PM_PINCTRL_BIAS_ENABLE,
416};
417
418enum pm_pinctrl_pull_ctrl {
419 PM_PINCTRL_BIAS_PULL_DOWN,
420 PM_PINCTRL_BIAS_PULL_UP,
421};
422
423enum pm_pinctrl_schmitt_cmos {
424 PM_PINCTRL_INPUT_TYPE_CMOS,
425 PM_PINCTRL_INPUT_TYPE_SCHMITT,
426};
427
428enum pm_pinctrl_drive_strength {
429 PM_PINCTRL_DRIVE_STRENGTH_2MA,
430 PM_PINCTRL_DRIVE_STRENGTH_4MA,
431 PM_PINCTRL_DRIVE_STRENGTH_8MA,
432 PM_PINCTRL_DRIVE_STRENGTH_12MA,
433};
434
435enum pm_ioctl_id {
436 IOCTL_GET_RPU_OPER_MODE,
437 IOCTL_SET_RPU_OPER_MODE,
438 IOCTL_RPU_BOOT_ADDR_CONFIG,
439 IOCTL_TCM_COMB_CONFIG,
440 IOCTL_SET_TAPDELAY_BYPASS,
441 IOCTL_SET_SGMII_MODE,
442 IOCTL_SD_DLL_RESET,
443 IOCTL_SET_SD_TAPDELAY,
444
445 IOCTL_SET_PLL_FRAC_MODE,
446 IOCTL_GET_PLL_FRAC_MODE,
447 IOCTL_SET_PLL_FRAC_DATA,
448 IOCTL_GET_PLL_FRAC_DATA,
449 IOCTL_WRITE_GGS,
450 IOCTL_READ_GGS,
451 IOCTL_WRITE_PGGS,
452 IOCTL_READ_PGGS,
453
454 IOCTL_ULPI_RESET,
455};
456
457enum rpu_oper_mode {
458 PM_RPU_MODE_LOCKSTEP,
459 PM_RPU_MODE_SPLIT,
460};
461
462enum rpu_boot_mem {
463 PM_RPU_BOOTMEM_LOVEC,
464 PM_RPU_BOOTMEM_HIVEC,
465};
466
467enum rpu_tcm_comb {
468 PM_RPU_TCM_SPLIT,
469 PM_RPU_TCM_COMB,
470};
471
472enum tap_delay_signal_type {
473 PM_TAPDELAY_NAND_DQS_IN,
474 PM_TAPDELAY_NAND_DQS_OUT,
475 PM_TAPDELAY_QSPI,
476 PM_TAPDELAY_MAX,
477};
478
479enum tap_delay_bypass_ctrl {
480 PM_TAPDELAY_BYPASS_DISABLE,
481 PM_TAPDELAY_BYPASS_ENABLE,
482};
483
484enum sgmii_mode {
485 PM_SGMII_DISABLE,
486 PM_SGMII_ENABLE,
487};
488
489enum tap_delay_type {
490 PM_TAPDELAY_INPUT,
491 PM_TAPDELAY_OUTPUT,
492};
493
494enum dll_reset_type {
495 PM_DLL_RESET_ASSERT,
496 PM_DLL_RESET_RELEASE,
497 PM_DLL_RESET_PULSE,
498};
499
500enum topology_type {
501 TYPE_INVALID,
502 TYPE_MUX,
503 TYPE_PLL,
504 TYPE_FIXEDFACTOR,
505 TYPE_DIV1,
506 TYPE_DIV2,
507 TYPE_GATE,
508};
509
510enum pm_query_id {
511 PM_QID_INVALID,
512 PM_QID_CLOCK_GET_NAME,
513 PM_QID_CLOCK_GET_TOPOLOGY,
514 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
515 PM_QID_CLOCK_GET_PARENTS,
516 PM_QID_CLOCK_GET_ATTRIBUTES,
517 PM_QID_PINCTRL_GET_NUM_PINS,
518 PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
519 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
520 PM_QID_PINCTRL_GET_FUNCTION_NAME,
521 PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
522 PM_QID_PINCTRL_GET_PIN_GROUPS,
523};
524
525struct zynqmp_pm_query_data {
526 u32 qid;
527 u32 arg1;
528 u32 arg2;
529 u32 arg3;
530};
531
532struct zynqmp_eemi_ops {
533 int (*get_api_version)(u32 *version);
534 int (*get_chipid)(u32 *idcode, u32 *version);
535 int (*reset_assert)(const enum zynqmp_pm_reset reset,
536 const enum zynqmp_pm_reset_action assert_flag);
537 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
538 int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
539 int (*fpga_get_status)(u32 *value);
540 int (*sha_hash)(const u64 address, const u32 size, const u32 flags);
541 int (*rsa)(const u64 address, const u32 size, const u32 flags);
542 int (*request_suspend)(const u32 node,
543 const enum zynqmp_pm_request_ack ack,
544 const u32 latency,
545 const u32 state);
546 int (*force_powerdown)(const u32 target,
547 const enum zynqmp_pm_request_ack ack);
548 int (*request_wakeup)(const u32 node,
549 const bool set_addr,
550 const u64 address,
551 const enum zynqmp_pm_request_ack ack);
552 int (*set_wakeup_source)(const u32 target,
553 const u32 wakeup_node,
554 const u32 enable);
555 int (*system_shutdown)(const u32 type, const u32 subtype);
556 int (*request_node)(const u32 node,
557 const u32 capabilities,
558 const u32 qos,
559 const enum zynqmp_pm_request_ack ack);
560 int (*release_node)(const u32 node);
561 int (*set_requirement)(const u32 node,
562 const u32 capabilities,
563 const u32 qos,
564 const enum zynqmp_pm_request_ack ack);
565 int (*set_max_latency)(const u32 node, const u32 latency);
566 int (*set_configuration)(const u32 physical_addr);
567 int (*get_node_status)(const u32 node, u32 *const status,
568 u32 *const requirements, u32 *const usage);
569 int (*get_operating_characteristic)(const u32 node,
570 const enum zynqmp_pm_opchar_type
571 type, u32 *const result);
572 int (*init_finalize)(void);
573 int (*set_suspend_mode)(u32 mode);
574 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
575 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
576 int (*pinctrl_request)(const u32 pin);
577 int (*pinctrl_release)(const u32 pin);
578 int (*pinctrl_get_function)(const u32 pin, u32 *id);
579 int (*pinctrl_set_function)(const u32 pin, const u32 id);
580 int (*pinctrl_get_config)(const u32 pin, const u32 param, u32 *value);
581 int (*pinctrl_set_config)(const u32 pin, const u32 param, u32 value);
582 int (*clock_enable)(u32 clock_id);
583 int (*clock_disable)(u32 clock_id);
584 int (*clock_getstate)(u32 clock_id, u32 *state);
585 int (*clock_setdivider)(u32 clock_id, u32 divider);
586 int (*clock_getdivider)(u32 clock_id, u32 *divider);
587 int (*clock_setrate)(u32 clock_id, u64 rate);
588 int (*clock_getrate)(u32 clock_id, u64 *rate);
589 int (*clock_setparent)(u32 clock_id, u32 parent_id);
590 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
591};
592
593
594
595
596int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
597 u32 arg2, u32 arg3, u32 *ret_payload);
598
599int zynqmp_pm_ggs_init(struct kobject *parent_kobj);
600
601#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
602const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
603#else
604static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
605{
606 return NULL;
607}
608#endif
609
610#endif
611
