1/* 2 * Secondary CPU startup routine source file. 3 * 4 * Copyright (C) 2009-2014 Texas Instruments, Inc. 5 * 6 * Author: 7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 8 * 9 * Interface functions needed for the SMP. This file is based on arm 10 * realview smp platform. 11 * Copyright (c) 2003 ARM Limited. 12 * 13 * This program is free software,you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18#include <linux/linkage.h> 19#include <linux/init.h> 20#include <asm/assembler.h> 21 22#include "omap44xx.h" 23 24/* Physical address needed since MMU not enabled yet on secondary core */ 25#define AUX_CORE_BOOT0_PA 0x48281800 26#define API_HYP_ENTRY 0x102 27 28ENTRY(omap_secondary_startup) 29#ifdef CONFIG_SMP 30 b secondary_startup 31#else 32/* Should never get here */ 33again: wfi 34 b again 35#endif 36#ENDPROC(omap_secondary_startup) 37 38/* 39 * OMAP5 specific entry point for secondary CPU to jump from ROM 40 * code. This routine also provides a holding flag into which 41 * secondary core is held until we're ready for it to initialise. 42 * The primary core will update this flag using a hardware 43 * register AuxCoreBoot0. 44 */ 45ENTRY(omap5_secondary_startup) 46wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 47 ldr r0, [r2] 48 mov r0, r0, lsr #5 49 mrc p15, 0, r4, c0, c0, 5 50 and r4, r4, #0x0f 51 cmp r0, r4 52 bne wait 53 b omap_secondary_startup 54ENDPROC(omap5_secondary_startup) 55/* 56 * Same as omap5_secondary_startup except we call into the ROM to 57 * enable HYP mode first. This is called instead of 58 * omap5_secondary_startup if the primary CPU was put into HYP mode by 59 * the boot loader. 60 */ 61ENTRY(omap5_secondary_hyp_startup) 62wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 63 ldr r0, [r2] 64 mov r0, r0, lsr #5 65 mrc p15, 0, r4, c0, c0, 5 66 and r4, r4, #0x0f 67 cmp r0, r4 68 bne wait_2 69 ldr r12, =API_HYP_ENTRY 70 badr r0, hyp_boot 71 smc #0 72hyp_boot: 73 b omap_secondary_startup 74ENDPROC(omap5_secondary_hyp_startup) 75/* 76 * OMAP4 specific entry point for secondary CPU to jump from ROM 77 * code. This routine also provides a holding flag into which 78 * secondary core is held until we're ready for it to initialise. 79 * The primary core will update this flag using a hardware 80 * register AuxCoreBoot0. 81 */ 82ENTRY(omap4_secondary_startup) 83hold: ldr r12,=0x103 84 dsb 85 smc #0 @ read from AuxCoreBoot0 86 mov r0, r0, lsr #9 87 mrc p15, 0, r4, c0, c0, 5 88 and r4, r4, #0x0f 89 cmp r0, r4 90 bne hold 91 92 /* 93 * we've been released from the wait loop,secondary_stack 94 * should now contain the SVC stack for this core 95 */ 96 b omap_secondary_startup 97ENDPROC(omap4_secondary_startup) 98 99ENTRY(omap4460_secondary_startup) 100hold_2: ldr r12,=0x103 101 dsb 102 smc #0 @ read from AuxCoreBoot0 103 mov r0, r0, lsr #9 104 mrc p15, 0, r4, c0, c0, 5 105 and r4, r4, #0x0f 106 cmp r0, r4 107 bne hold_2 108 109 /* 110 * GIC distributor control register has changed between 111 * CortexA9 r1pX and r2pX. The Control Register secure 112 * banked version is now composed of 2 bits: 113 * bit 0 == Secure Enable 114 * bit 1 == Non-Secure Enable 115 * The Non-Secure banked register has not changed 116 * Because the ROM Code is based on the r1pX GIC, the CPU1 117 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 118 * The workaround must be: 119 * 1) Before doing the CPU1 wakeup, CPU0 must disable 120 * the GIC distributor 121 * 2) CPU1 must re-enable the GIC distributor on 122 * it's wakeup path. 123 */ 124 ldr r1, =OMAP44XX_GIC_DIST_BASE 125 ldr r0, [r1] 126 orr r0, #1 127 str r0, [r1] 128 129 /* 130 * we've been released from the wait loop,secondary_stack 131 * should now contain the SVC stack for this core 132 */ 133 b omap_secondary_startup 134ENDPROC(omap4460_secondary_startup) 135