LXR linux/arch/arm64/include/asm/ptrace.h

   1/*
   2 * Based on arch/arm/include/asm/ptrace.h
   3 *
   4 * Copyright (C) 1996-2003 Russell King
   5 * Copyright (C) 2012 ARM Ltd.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19#ifndef __ASM_PTRACE_H
  20#define __ASM_PTRACE_H
  21
  22#include <uapi/asm/ptrace.h>
  23
  24/* Current Exception Level values, as contained in CurrentEL */
  25#define CurrentEL_EL1           (1 << 2)
  26#define CurrentEL_EL2           (2 << 2)
  27
  28/* AArch32-specific ptrace requests */
  29#define COMPAT_PTRACE_GETREGS           12
  30#define COMPAT_PTRACE_SETREGS           13
  31#define COMPAT_PTRACE_GET_THREAD_AREA   22
  32#define COMPAT_PTRACE_SET_SYSCALL       23
  33#define COMPAT_PTRACE_GETVFPREGS        27
  34#define COMPAT_PTRACE_SETVFPREGS        28
  35#define COMPAT_PTRACE_GETHBPREGS        29
  36#define COMPAT_PTRACE_SETHBPREGS        30
  37
  38/* AArch32 CPSR bits */
  39#define COMPAT_PSR_MODE_MASK    0x0000001f
  40#define COMPAT_PSR_MODE_USR     0x00000010
  41#define COMPAT_PSR_MODE_FIQ     0x00000011
  42#define COMPAT_PSR_MODE_IRQ     0x00000012
  43#define COMPAT_PSR_MODE_SVC     0x00000013
  44#define COMPAT_PSR_MODE_ABT     0x00000017
  45#define COMPAT_PSR_MODE_HYP     0x0000001a
  46#define COMPAT_PSR_MODE_UND     0x0000001b
  47#define COMPAT_PSR_MODE_SYS     0x0000001f
  48#define COMPAT_PSR_T_BIT        0x00000020
  49#define COMPAT_PSR_F_BIT        0x00000040
  50#define COMPAT_PSR_I_BIT        0x00000080
  51#define COMPAT_PSR_A_BIT        0x00000100
  52#define COMPAT_PSR_E_BIT        0x00000200
  53#define COMPAT_PSR_J_BIT        0x01000000
  54#define COMPAT_PSR_Q_BIT        0x08000000
  55#define COMPAT_PSR_V_BIT        0x10000000
  56#define COMPAT_PSR_C_BIT        0x20000000
  57#define COMPAT_PSR_Z_BIT        0x40000000
  58#define COMPAT_PSR_N_BIT        0x80000000
  59#define COMPAT_PSR_IT_MASK      0x0600fc00      /* If-Then execution state mask */
  60#define COMPAT_PSR_GE_MASK      0x000f0000
  61
  62#ifdef CONFIG_CPU_BIG_ENDIAN
  63#define COMPAT_PSR_ENDSTATE     COMPAT_PSR_E_BIT
  64#else
  65#define COMPAT_PSR_ENDSTATE     0
  66#endif
  67
  68/*
  69 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
  70 * process is located in memory.
  71 */
  72#define COMPAT_PT_TEXT_ADDR             0x10000
  73#define COMPAT_PT_DATA_ADDR             0x10004
  74#define COMPAT_PT_TEXT_END_ADDR         0x10008
  75
  76/*
  77 * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
  78 * a syscall -- i.e., its most recent entry into the kernel from
  79 * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
  80 *
  81 * This must have the value -1, for ABI compatibility with ptrace etc.
  82 */
  83#define NO_SYSCALL (-1)
  84
  85#ifndef __ASSEMBLY__
  86#include <linux/bug.h>
  87#include <linux/types.h>
  88
  89/* sizeof(struct user) for AArch32 */
  90#define COMPAT_USER_SZ  296
  91
  92/* Architecturally defined mapping between AArch32 and AArch64 registers */
  93#define compat_usr(x)   regs[(x)]
  94#define compat_fp       regs[11]
  95#define compat_sp       regs[13]
  96#define compat_lr       regs[14]
  97#define compat_sp_hyp   regs[15]
  98#define compat_lr_irq   regs[16]
  99#define compat_sp_irq   regs[17]
 100#define compat_lr_svc   regs[18]
 101#define compat_sp_svc   regs[19]
 102#define compat_lr_abt   regs[20]
 103#define compat_sp_abt   regs[21]
 104#define compat_lr_und   regs[22]
 105#define compat_sp_und   regs[23]
 106#define compat_r8_fiq   regs[24]
 107#define compat_r9_fiq   regs[25]
 108#define compat_r10_fiq  regs[26]
 109#define compat_r11_fiq  regs[27]
 110#define compat_r12_fiq  regs[28]
 111#define compat_sp_fiq   regs[29]
 112#define compat_lr_fiq   regs[30]
 113
 114/*
 115 * This struct defines the way the registers are stored on the stack during an
 116 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
 117 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
 118 */
 119struct pt_regs {
 120        union {
 121                struct user_pt_regs user_regs;
 122                struct {
 123                        u64 regs[31];
 124                        u64 sp;
 125                        u64 pc;
 126                        u64 pstate;
 127                };
 128        };
 129        u64 orig_x0;
 130#ifdef __AARCH64EB__
 131        u32 unused2;
 132        s32 syscallno;
 133#else
 134        s32 syscallno;
 135        u32 unused2;
 136#endif
 137
 138        u64 orig_addr_limit;
 139        u64 unused;     // maintain 16 byte alignment
 140        u64 stackframe[2];
 141};
 142
 143static inline bool in_syscall(struct pt_regs const *regs)
 144{
 145        return regs->syscallno != NO_SYSCALL;
 146}
 147
 148static inline void forget_syscall(struct pt_regs *regs)
 149{
 150        regs->syscallno = NO_SYSCALL;
 151}
 152
 153#define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
 154
 155#define arch_has_single_step()  (1)
 156
 157#ifdef CONFIG_COMPAT
 158#define compat_thumb_mode(regs) \
 159        (((regs)->pstate & COMPAT_PSR_T_BIT))
 160#else
 161#define compat_thumb_mode(regs) (0)
 162#endif
 163
 164#define user_mode(regs) \
 165        (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
 166
 167#define compat_user_mode(regs)  \
 168        (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
 169         (PSR_MODE32_BIT | PSR_MODE_EL0t))
 170
 171#define processor_mode(regs) \
 172        ((regs)->pstate & PSR_MODE_MASK)
 173
 174#define interrupts_enabled(regs) \
 175        (!((regs)->pstate & PSR_I_BIT))
 176
 177#define fast_interrupts_enabled(regs) \
 178        (!((regs)->pstate & PSR_F_BIT))
 179
 180#define GET_USP(regs) \
 181        (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
 182
 183#define SET_USP(ptregs, value) \
 184        (!compat_user_mode(regs) ? ((regs)->sp = value) : ((regs)->compat_sp = value))
 185
 186extern int regs_query_register_offset(const char *name);
 187extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
 188                                               unsigned int n);
 189
 190/**
 191 * regs_get_register() - get register value from its offset
 192 * @regs:       pt_regs from which register value is gotten
 193 * @offset:     offset of the register.
 194 *
 195 * regs_get_register returns the value of a register whose offset from @regs.
 196 * The @offset is the offset of the register in struct pt_regs.
 197 * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
 198 */
 199static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
 200{
 201        u64 val = 0;
 202
 203        WARN_ON(offset & 7);
 204
 205        offset >>= 3;
 206        switch (offset) {
 207        case 0 ... 30:
 208                val = regs->regs[offset];
 209                break;
 210        case offsetof(struct pt_regs, sp) >> 3:
 211                val = regs->sp;
 212                break;
 213        case offsetof(struct pt_regs, pc) >> 3:
 214                val = regs->pc;
 215                break;
 216        case offsetof(struct pt_regs, pstate) >> 3:
 217                val = regs->pstate;
 218                break;
 219        default:
 220                val = 0;
 221        }
 222
 223        return val;
 224}
 225
 226/*
 227 * Read a register given an architectural register index r.
 228 * This handles the common case where 31 means XZR, not SP.
 229 */
 230static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
 231{
 232        return (r == 31) ? 0 : regs->regs[r];
 233}
 234
 235/*
 236 * Write a register given an architectural register index r.
 237 * This handles the common case where 31 means XZR, not SP.
 238 */
 239static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
 240                                     unsigned long val)
 241{
 242        if (r != 31)
 243                regs->regs[r] = val;
 244}
 245
 246/* Valid only for Kernel mode traps. */
 247static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 248{
 249        return regs->sp;
 250}
 251
 252static inline unsigned long regs_return_value(struct pt_regs *regs)
 253{
 254        return regs->regs[0];
 255}
 256
 257/* We must avoid circular header include via sched.h */
 258struct task_struct;
 259int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
 260
 261#define GET_IP(regs)            ((unsigned long)(regs)->pc)
 262#define SET_IP(regs, value)     ((regs)->pc = ((u64) (value)))
 263
 264#define GET_FP(ptregs)          ((unsigned long)(ptregs)->regs[29])
 265#define SET_FP(ptregs, value)   ((ptregs)->regs[29] = ((u64) (value)))
 266
 267#include <asm-generic/ptrace.h>
 268
 269#define procedure_link_pointer(regs)    ((regs)->regs[30])
 270
 271static inline void procedure_link_pointer_set(struct pt_regs *regs,
 272                                           unsigned long val)
 273{
 274        procedure_link_pointer(regs) = val;
 275}
 276
 277#undef profile_pc
 278extern unsigned long profile_pc(struct pt_regs *regs);
 279
 280#endif /* __ASSEMBLY__ */
 281#endif
 282