1
2#ifndef __iop_sap_out_defs_h
3#define __iop_sap_out_defs_h
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18#ifndef REG_RD
19#define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
22#endif
23
24#ifndef REG_WR
25#define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28#endif
29
30#ifndef REG_RD_VECT
31#define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
35#endif
36
37#ifndef REG_WR_VECT
38#define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
42#endif
43
44#ifndef REG_RD_INT
45#define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47#endif
48
49#ifndef REG_WR_INT
50#define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
52#endif
53
54#ifndef REG_RD_INT_VECT
55#define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
58#endif
59
60#ifndef REG_WR_INT_VECT
61#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
64#endif
65
66#ifndef REG_TYPE_CONV
67#define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69#endif
70
71#ifndef reg_page_size
72#define reg_page_size 8192
73#endif
74
75#ifndef REG_ADDR
76#define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78#endif
79
80#ifndef REG_ADDR_VECT
81#define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
84#endif
85
86
87
88
89typedef struct {
90 unsigned int clk0_src : 2;
91 unsigned int clk0_gate_src : 2;
92 unsigned int clk0_force_src : 3;
93 unsigned int clk1_src : 2;
94 unsigned int clk1_gate_src : 2;
95 unsigned int clk1_force_src : 3;
96 unsigned int clk2_src : 2;
97 unsigned int clk2_gate_src : 2;
98 unsigned int clk2_force_src : 3;
99 unsigned int clk3_src : 2;
100 unsigned int clk3_gate_src : 2;
101 unsigned int clk3_force_src : 3;
102 unsigned int dummy1 : 4;
103} reg_iop_sap_out_rw_gen_gated;
104#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
105#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
106
107
108typedef struct {
109 unsigned int byte0_clk_sel : 3;
110 unsigned int byte0_gated_clk : 2;
111 unsigned int byte0_clk_inv : 1;
112 unsigned int byte1_clk_sel : 3;
113 unsigned int byte1_gated_clk : 2;
114 unsigned int byte1_clk_inv : 1;
115 unsigned int byte2_clk_sel : 3;
116 unsigned int byte2_gated_clk : 2;
117 unsigned int byte2_clk_inv : 1;
118 unsigned int byte3_clk_sel : 3;
119 unsigned int byte3_gated_clk : 2;
120 unsigned int byte3_clk_inv : 1;
121 unsigned int dummy1 : 8;
122} reg_iop_sap_out_rw_bus0;
123#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
124#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
125
126
127typedef struct {
128 unsigned int byte0_clk_sel : 3;
129 unsigned int byte0_gated_clk : 2;
130 unsigned int byte0_clk_inv : 1;
131 unsigned int byte1_clk_sel : 3;
132 unsigned int byte1_gated_clk : 2;
133 unsigned int byte1_clk_inv : 1;
134 unsigned int byte2_clk_sel : 3;
135 unsigned int byte2_gated_clk : 2;
136 unsigned int byte2_clk_inv : 1;
137 unsigned int byte3_clk_sel : 3;
138 unsigned int byte3_gated_clk : 2;
139 unsigned int byte3_clk_inv : 1;
140 unsigned int dummy1 : 8;
141} reg_iop_sap_out_rw_bus1;
142#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
143#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
144
145
146typedef struct {
147 unsigned int byte0_clk_sel : 3;
148 unsigned int byte0_clk_ext : 3;
149 unsigned int byte0_gated_clk : 2;
150 unsigned int byte0_clk_inv : 1;
151 unsigned int byte0_logic : 2;
152 unsigned int byte1_clk_sel : 3;
153 unsigned int byte1_clk_ext : 3;
154 unsigned int byte1_gated_clk : 2;
155 unsigned int byte1_clk_inv : 1;
156 unsigned int byte1_logic : 2;
157 unsigned int dummy1 : 10;
158} reg_iop_sap_out_rw_bus0_lo_oe;
159#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
160#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
161
162
163typedef struct {
164 unsigned int byte2_clk_sel : 3;
165 unsigned int byte2_clk_ext : 3;
166 unsigned int byte2_gated_clk : 2;
167 unsigned int byte2_clk_inv : 1;
168 unsigned int byte2_logic : 2;
169 unsigned int byte3_clk_sel : 3;
170 unsigned int byte3_clk_ext : 3;
171 unsigned int byte3_gated_clk : 2;
172 unsigned int byte3_clk_inv : 1;
173 unsigned int byte3_logic : 2;
174 unsigned int dummy1 : 10;
175} reg_iop_sap_out_rw_bus0_hi_oe;
176#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
177#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
178
179
180typedef struct {
181 unsigned int byte0_clk_sel : 3;
182 unsigned int byte0_clk_ext : 3;
183 unsigned int byte0_gated_clk : 2;
184 unsigned int byte0_clk_inv : 1;
185 unsigned int byte0_logic : 2;
186 unsigned int byte1_clk_sel : 3;
187 unsigned int byte1_clk_ext : 3;
188 unsigned int byte1_gated_clk : 2;
189 unsigned int byte1_clk_inv : 1;
190 unsigned int byte1_logic : 2;
191 unsigned int dummy1 : 10;
192} reg_iop_sap_out_rw_bus1_lo_oe;
193#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
194#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
195
196
197typedef struct {
198 unsigned int byte2_clk_sel : 3;
199 unsigned int byte2_clk_ext : 3;
200 unsigned int byte2_gated_clk : 2;
201 unsigned int byte2_clk_inv : 1;
202 unsigned int byte2_logic : 2;
203 unsigned int byte3_clk_sel : 3;
204 unsigned int byte3_clk_ext : 3;
205 unsigned int byte3_gated_clk : 2;
206 unsigned int byte3_clk_inv : 1;
207 unsigned int byte3_logic : 2;
208 unsigned int dummy1 : 10;
209} reg_iop_sap_out_rw_bus1_hi_oe;
210#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
211#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
212
213#define STRIDE_iop_sap_out_rw_gio 4
214
215typedef struct {
216 unsigned int out_clk_sel : 3;
217 unsigned int out_clk_ext : 4;
218 unsigned int out_gated_clk : 2;
219 unsigned int out_clk_inv : 1;
220 unsigned int out_logic : 1;
221 unsigned int oe_clk_sel : 3;
222 unsigned int oe_clk_ext : 3;
223 unsigned int oe_gated_clk : 2;
224 unsigned int oe_clk_inv : 1;
225 unsigned int oe_logic : 2;
226 unsigned int dummy1 : 10;
227} reg_iop_sap_out_rw_gio;
228#define REG_RD_ADDR_iop_sap_out_rw_gio 28
229#define REG_WR_ADDR_iop_sap_out_rw_gio 28
230
231
232
233enum {
234 regk_iop_sap_out_and = 0x00000002,
235 regk_iop_sap_out_clk0 = 0x00000000,
236 regk_iop_sap_out_clk1 = 0x00000001,
237 regk_iop_sap_out_clk12 = 0x00000002,
238 regk_iop_sap_out_clk2 = 0x00000002,
239 regk_iop_sap_out_clk200 = 0x00000001,
240 regk_iop_sap_out_clk3 = 0x00000003,
241 regk_iop_sap_out_ext = 0x00000003,
242 regk_iop_sap_out_gated = 0x00000004,
243 regk_iop_sap_out_gio1 = 0x00000000,
244 regk_iop_sap_out_gio13 = 0x00000002,
245 regk_iop_sap_out_gio13_clk = 0x0000000c,
246 regk_iop_sap_out_gio15 = 0x00000001,
247 regk_iop_sap_out_gio18 = 0x00000003,
248 regk_iop_sap_out_gio18_clk = 0x0000000d,
249 regk_iop_sap_out_gio1_clk = 0x00000008,
250 regk_iop_sap_out_gio21_clk = 0x0000000e,
251 regk_iop_sap_out_gio23 = 0x00000002,
252 regk_iop_sap_out_gio29_clk = 0x0000000f,
253 regk_iop_sap_out_gio31 = 0x00000003,
254 regk_iop_sap_out_gio5 = 0x00000001,
255 regk_iop_sap_out_gio5_clk = 0x00000009,
256 regk_iop_sap_out_gio6_clk = 0x0000000a,
257 regk_iop_sap_out_gio7 = 0x00000000,
258 regk_iop_sap_out_gio7_clk = 0x0000000b,
259 regk_iop_sap_out_gio_in13 = 0x00000001,
260 regk_iop_sap_out_gio_in21 = 0x00000002,
261 regk_iop_sap_out_gio_in29 = 0x00000003,
262 regk_iop_sap_out_gio_in5 = 0x00000000,
263 regk_iop_sap_out_inv = 0x00000001,
264 regk_iop_sap_out_nand = 0x00000003,
265 regk_iop_sap_out_no = 0x00000000,
266 regk_iop_sap_out_none = 0x00000000,
267 regk_iop_sap_out_rw_bus0_default = 0x00000000,
268 regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000,
269 regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000,
270 regk_iop_sap_out_rw_bus1_default = 0x00000000,
271 regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000,
272 regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000,
273 regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
274 regk_iop_sap_out_rw_gio_default = 0x00000000,
275 regk_iop_sap_out_rw_gio_size = 0x00000020,
276 regk_iop_sap_out_spu0_gio0 = 0x00000002,
277 regk_iop_sap_out_spu0_gio1 = 0x00000003,
278 regk_iop_sap_out_spu0_gio12 = 0x00000004,
279 regk_iop_sap_out_spu0_gio13 = 0x00000004,
280 regk_iop_sap_out_spu0_gio14 = 0x00000004,
281 regk_iop_sap_out_spu0_gio15 = 0x00000004,
282 regk_iop_sap_out_spu0_gio2 = 0x00000002,
283 regk_iop_sap_out_spu0_gio3 = 0x00000003,
284 regk_iop_sap_out_spu0_gio4 = 0x00000002,
285 regk_iop_sap_out_spu0_gio5 = 0x00000003,
286 regk_iop_sap_out_spu0_gio6 = 0x00000002,
287 regk_iop_sap_out_spu0_gio7 = 0x00000003,
288 regk_iop_sap_out_spu1_gio0 = 0x00000005,
289 regk_iop_sap_out_spu1_gio1 = 0x00000006,
290 regk_iop_sap_out_spu1_gio12 = 0x00000007,
291 regk_iop_sap_out_spu1_gio13 = 0x00000007,
292 regk_iop_sap_out_spu1_gio14 = 0x00000007,
293 regk_iop_sap_out_spu1_gio15 = 0x00000007,
294 regk_iop_sap_out_spu1_gio2 = 0x00000005,
295 regk_iop_sap_out_spu1_gio3 = 0x00000006,
296 regk_iop_sap_out_spu1_gio4 = 0x00000005,
297 regk_iop_sap_out_spu1_gio5 = 0x00000006,
298 regk_iop_sap_out_spu1_gio6 = 0x00000005,
299 regk_iop_sap_out_spu1_gio7 = 0x00000006,
300 regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004,
301 regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005,
302 regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006,
303 regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007,
304 regk_iop_sap_out_tmr = 0x00000005,
305 regk_iop_sap_out_yes = 0x00000001
306};
307#endif
308
