1
2#ifndef __iop_sw_cpu_defs_h
3#define __iop_sw_cpu_defs_h
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17
18#ifndef REG_RD
19#define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
22#endif
23
24#ifndef REG_WR
25#define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28#endif
29
30#ifndef REG_RD_VECT
31#define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
35#endif
36
37#ifndef REG_WR_VECT
38#define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
42#endif
43
44#ifndef REG_RD_INT
45#define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
47#endif
48
49#ifndef REG_WR_INT
50#define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
52#endif
53
54#ifndef REG_RD_INT_VECT
55#define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
58#endif
59
60#ifndef REG_WR_INT_VECT
61#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
64#endif
65
66#ifndef REG_TYPE_CONV
67#define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
69#endif
70
71#ifndef reg_page_size
72#define reg_page_size 8192
73#endif
74
75#ifndef REG_ADDR
76#define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
78#endif
79
80#ifndef REG_ADDR_VECT
81#define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
84#endif
85
86
87
88
89typedef struct {
90 unsigned int keep_owner : 1;
91 unsigned int cmd : 2;
92 unsigned int size : 3;
93 unsigned int wr_spu0_mem : 1;
94 unsigned int wr_spu1_mem : 1;
95 unsigned int dummy1 : 24;
96} reg_iop_sw_cpu_rw_mc_ctrl;
97#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
98#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
99
100
101typedef struct {
102 unsigned int val : 32;
103} reg_iop_sw_cpu_rw_mc_data;
104#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
105#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
106
107
108typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
109#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
110#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
111
112
113typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
114#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
115
116
117typedef unsigned int reg_iop_sw_cpu_r_mc_data;
118#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
119
120
121typedef struct {
122 unsigned int busy_cpu : 1;
123 unsigned int busy_mpu : 1;
124 unsigned int busy_spu0 : 1;
125 unsigned int busy_spu1 : 1;
126 unsigned int owned_by_cpu : 1;
127 unsigned int owned_by_mpu : 1;
128 unsigned int owned_by_spu0 : 1;
129 unsigned int owned_by_spu1 : 1;
130 unsigned int dummy1 : 24;
131} reg_iop_sw_cpu_r_mc_stat;
132#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
133
134
135typedef struct {
136 unsigned int byte0 : 8;
137 unsigned int byte1 : 8;
138 unsigned int byte2 : 8;
139 unsigned int byte3 : 8;
140} reg_iop_sw_cpu_rw_bus0_clr_mask;
141#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
142#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
143
144
145typedef struct {
146 unsigned int byte0 : 8;
147 unsigned int byte1 : 8;
148 unsigned int byte2 : 8;
149 unsigned int byte3 : 8;
150} reg_iop_sw_cpu_rw_bus0_set_mask;
151#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
152#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
153
154
155typedef struct {
156 unsigned int byte0 : 1;
157 unsigned int byte1 : 1;
158 unsigned int byte2 : 1;
159 unsigned int byte3 : 1;
160 unsigned int dummy1 : 28;
161} reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
162#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
163#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
164
165
166typedef struct {
167 unsigned int byte0 : 1;
168 unsigned int byte1 : 1;
169 unsigned int byte2 : 1;
170 unsigned int byte3 : 1;
171 unsigned int dummy1 : 28;
172} reg_iop_sw_cpu_rw_bus0_oe_set_mask;
173#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
174#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
175
176
177typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
178#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
179
180
181typedef struct {
182 unsigned int byte0 : 8;
183 unsigned int byte1 : 8;
184 unsigned int byte2 : 8;
185 unsigned int byte3 : 8;
186} reg_iop_sw_cpu_rw_bus1_clr_mask;
187#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
188#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
189
190
191typedef struct {
192 unsigned int byte0 : 8;
193 unsigned int byte1 : 8;
194 unsigned int byte2 : 8;
195 unsigned int byte3 : 8;
196} reg_iop_sw_cpu_rw_bus1_set_mask;
197#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
198#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
199
200
201typedef struct {
202 unsigned int byte0 : 1;
203 unsigned int byte1 : 1;
204 unsigned int byte2 : 1;
205 unsigned int byte3 : 1;
206 unsigned int dummy1 : 28;
207} reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
208#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
209#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
210
211
212typedef struct {
213 unsigned int byte0 : 1;
214 unsigned int byte1 : 1;
215 unsigned int byte2 : 1;
216 unsigned int byte3 : 1;
217 unsigned int dummy1 : 28;
218} reg_iop_sw_cpu_rw_bus1_oe_set_mask;
219#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
220#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
221
222
223typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
224#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
225
226
227typedef struct {
228 unsigned int val : 32;
229} reg_iop_sw_cpu_rw_gio_clr_mask;
230#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
231#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
232
233
234typedef struct {
235 unsigned int val : 32;
236} reg_iop_sw_cpu_rw_gio_set_mask;
237#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
238#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
239
240
241typedef struct {
242 unsigned int val : 32;
243} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
244#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
245#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
246
247
248typedef struct {
249 unsigned int val : 32;
250} reg_iop_sw_cpu_rw_gio_oe_set_mask;
251#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
252#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
253
254
255typedef unsigned int reg_iop_sw_cpu_r_gio_in;
256#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
257
258
259typedef struct {
260 unsigned int mpu_0 : 1;
261 unsigned int mpu_1 : 1;
262 unsigned int mpu_2 : 1;
263 unsigned int mpu_3 : 1;
264 unsigned int mpu_4 : 1;
265 unsigned int mpu_5 : 1;
266 unsigned int mpu_6 : 1;
267 unsigned int mpu_7 : 1;
268 unsigned int mpu_8 : 1;
269 unsigned int mpu_9 : 1;
270 unsigned int mpu_10 : 1;
271 unsigned int mpu_11 : 1;
272 unsigned int mpu_12 : 1;
273 unsigned int mpu_13 : 1;
274 unsigned int mpu_14 : 1;
275 unsigned int mpu_15 : 1;
276 unsigned int spu0_0 : 1;
277 unsigned int spu0_1 : 1;
278 unsigned int spu0_2 : 1;
279 unsigned int spu0_3 : 1;
280 unsigned int spu0_4 : 1;
281 unsigned int spu0_5 : 1;
282 unsigned int spu0_6 : 1;
283 unsigned int spu0_7 : 1;
284 unsigned int spu1_8 : 1;
285 unsigned int spu1_9 : 1;
286 unsigned int spu1_10 : 1;
287 unsigned int spu1_11 : 1;
288 unsigned int spu1_12 : 1;
289 unsigned int spu1_13 : 1;
290 unsigned int spu1_14 : 1;
291 unsigned int spu1_15 : 1;
292} reg_iop_sw_cpu_rw_intr0_mask;
293#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
294#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
295
296
297typedef struct {
298 unsigned int mpu_0 : 1;
299 unsigned int mpu_1 : 1;
300 unsigned int mpu_2 : 1;
301 unsigned int mpu_3 : 1;
302 unsigned int mpu_4 : 1;
303 unsigned int mpu_5 : 1;
304 unsigned int mpu_6 : 1;
305 unsigned int mpu_7 : 1;
306 unsigned int mpu_8 : 1;
307 unsigned int mpu_9 : 1;
308 unsigned int mpu_10 : 1;
309 unsigned int mpu_11 : 1;
310 unsigned int mpu_12 : 1;
311 unsigned int mpu_13 : 1;
312 unsigned int mpu_14 : 1;
313 unsigned int mpu_15 : 1;
314 unsigned int spu0_0 : 1;
315 unsigned int spu0_1 : 1;
316 unsigned int spu0_2 : 1;
317 unsigned int spu0_3 : 1;
318 unsigned int spu0_4 : 1;
319 unsigned int spu0_5 : 1;
320 unsigned int spu0_6 : 1;
321 unsigned int spu0_7 : 1;
322 unsigned int spu1_8 : 1;
323 unsigned int spu1_9 : 1;
324 unsigned int spu1_10 : 1;
325 unsigned int spu1_11 : 1;
326 unsigned int spu1_12 : 1;
327 unsigned int spu1_13 : 1;
328 unsigned int spu1_14 : 1;
329 unsigned int spu1_15 : 1;
330} reg_iop_sw_cpu_rw_ack_intr0;
331#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
332#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
333
334
335typedef struct {
336 unsigned int mpu_0 : 1;
337 unsigned int mpu_1 : 1;
338 unsigned int mpu_2 : 1;
339 unsigned int mpu_3 : 1;
340 unsigned int mpu_4 : 1;
341 unsigned int mpu_5 : 1;
342 unsigned int mpu_6 : 1;
343 unsigned int mpu_7 : 1;
344 unsigned int mpu_8 : 1;
345 unsigned int mpu_9 : 1;
346 unsigned int mpu_10 : 1;
347 unsigned int mpu_11 : 1;
348 unsigned int mpu_12 : 1;
349 unsigned int mpu_13 : 1;
350 unsigned int mpu_14 : 1;
351 unsigned int mpu_15 : 1;
352 unsigned int spu0_0 : 1;
353 unsigned int spu0_1 : 1;
354 unsigned int spu0_2 : 1;
355 unsigned int spu0_3 : 1;
356 unsigned int spu0_4 : 1;
357 unsigned int spu0_5 : 1;
358 unsigned int spu0_6 : 1;
359 unsigned int spu0_7 : 1;
360 unsigned int spu1_8 : 1;
361 unsigned int spu1_9 : 1;
362 unsigned int spu1_10 : 1;
363 unsigned int spu1_11 : 1;
364 unsigned int spu1_12 : 1;
365 unsigned int spu1_13 : 1;
366 unsigned int spu1_14 : 1;
367 unsigned int spu1_15 : 1;
368} reg_iop_sw_cpu_r_intr0;
369#define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
370
371
372typedef struct {
373 unsigned int mpu_0 : 1;
374 unsigned int mpu_1 : 1;
375 unsigned int mpu_2 : 1;
376 unsigned int mpu_3 : 1;
377 unsigned int mpu_4 : 1;
378 unsigned int mpu_5 : 1;
379 unsigned int mpu_6 : 1;
380 unsigned int mpu_7 : 1;
381 unsigned int mpu_8 : 1;
382 unsigned int mpu_9 : 1;
383 unsigned int mpu_10 : 1;
384 unsigned int mpu_11 : 1;
385 unsigned int mpu_12 : 1;
386 unsigned int mpu_13 : 1;
387 unsigned int mpu_14 : 1;
388 unsigned int mpu_15 : 1;
389 unsigned int spu0_0 : 1;
390 unsigned int spu0_1 : 1;
391 unsigned int spu0_2 : 1;
392 unsigned int spu0_3 : 1;
393 unsigned int spu0_4 : 1;
394 unsigned int spu0_5 : 1;
395 unsigned int spu0_6 : 1;
396 unsigned int spu0_7 : 1;
397 unsigned int spu1_8 : 1;
398 unsigned int spu1_9 : 1;
399 unsigned int spu1_10 : 1;
400 unsigned int spu1_11 : 1;
401 unsigned int spu1_12 : 1;
402 unsigned int spu1_13 : 1;
403 unsigned int spu1_14 : 1;
404 unsigned int spu1_15 : 1;
405} reg_iop_sw_cpu_r_masked_intr0;
406#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
407
408
409typedef struct {
410 unsigned int mpu_16 : 1;
411 unsigned int mpu_17 : 1;
412 unsigned int mpu_18 : 1;
413 unsigned int mpu_19 : 1;
414 unsigned int mpu_20 : 1;
415 unsigned int mpu_21 : 1;
416 unsigned int mpu_22 : 1;
417 unsigned int mpu_23 : 1;
418 unsigned int mpu_24 : 1;
419 unsigned int mpu_25 : 1;
420 unsigned int mpu_26 : 1;
421 unsigned int mpu_27 : 1;
422 unsigned int mpu_28 : 1;
423 unsigned int mpu_29 : 1;
424 unsigned int mpu_30 : 1;
425 unsigned int mpu_31 : 1;
426 unsigned int spu0_8 : 1;
427 unsigned int spu0_9 : 1;
428 unsigned int spu0_10 : 1;
429 unsigned int spu0_11 : 1;
430 unsigned int spu0_12 : 1;
431 unsigned int spu0_13 : 1;
432 unsigned int spu0_14 : 1;
433 unsigned int spu0_15 : 1;
434 unsigned int spu1_0 : 1;
435 unsigned int spu1_1 : 1;
436 unsigned int spu1_2 : 1;
437 unsigned int spu1_3 : 1;
438 unsigned int spu1_4 : 1;
439 unsigned int spu1_5 : 1;
440 unsigned int spu1_6 : 1;
441 unsigned int spu1_7 : 1;
442} reg_iop_sw_cpu_rw_intr1_mask;
443#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
444#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
445
446
447typedef struct {
448 unsigned int mpu_16 : 1;
449 unsigned int mpu_17 : 1;
450 unsigned int mpu_18 : 1;
451 unsigned int mpu_19 : 1;
452 unsigned int mpu_20 : 1;
453 unsigned int mpu_21 : 1;
454 unsigned int mpu_22 : 1;
455 unsigned int mpu_23 : 1;
456 unsigned int mpu_24 : 1;
457 unsigned int mpu_25 : 1;
458 unsigned int mpu_26 : 1;
459 unsigned int mpu_27 : 1;
460 unsigned int mpu_28 : 1;
461 unsigned int mpu_29 : 1;
462 unsigned int mpu_30 : 1;
463 unsigned int mpu_31 : 1;
464 unsigned int spu0_8 : 1;
465 unsigned int spu0_9 : 1;
466 unsigned int spu0_10 : 1;
467 unsigned int spu0_11 : 1;
468 unsigned int spu0_12 : 1;
469 unsigned int spu0_13 : 1;
470 unsigned int spu0_14 : 1;
471 unsigned int spu0_15 : 1;
472 unsigned int spu1_0 : 1;
473 unsigned int spu1_1 : 1;
474 unsigned int spu1_2 : 1;
475 unsigned int spu1_3 : 1;
476 unsigned int spu1_4 : 1;
477 unsigned int spu1_5 : 1;
478 unsigned int spu1_6 : 1;
479 unsigned int spu1_7 : 1;
480} reg_iop_sw_cpu_rw_ack_intr1;
481#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
482#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
483
484
485typedef struct {
486 unsigned int mpu_16 : 1;
487 unsigned int mpu_17 : 1;
488 unsigned int mpu_18 : 1;
489 unsigned int mpu_19 : 1;
490 unsigned int mpu_20 : 1;
491 unsigned int mpu_21 : 1;
492 unsigned int mpu_22 : 1;
493 unsigned int mpu_23 : 1;
494 unsigned int mpu_24 : 1;
495 unsigned int mpu_25 : 1;
496 unsigned int mpu_26 : 1;
497 unsigned int mpu_27 : 1;
498 unsigned int mpu_28 : 1;
499 unsigned int mpu_29 : 1;
500 unsigned int mpu_30 : 1;
501 unsigned int mpu_31 : 1;
502 unsigned int spu0_8 : 1;
503 unsigned int spu0_9 : 1;
504 unsigned int spu0_10 : 1;
505 unsigned int spu0_11 : 1;
506 unsigned int spu0_12 : 1;
507 unsigned int spu0_13 : 1;
508 unsigned int spu0_14 : 1;
509 unsigned int spu0_15 : 1;
510 unsigned int spu1_0 : 1;
511 unsigned int spu1_1 : 1;
512 unsigned int spu1_2 : 1;
513 unsigned int spu1_3 : 1;
514 unsigned int spu1_4 : 1;
515 unsigned int spu1_5 : 1;
516 unsigned int spu1_6 : 1;
517 unsigned int spu1_7 : 1;
518} reg_iop_sw_cpu_r_intr1;
519#define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
520
521
522typedef struct {
523 unsigned int mpu_16 : 1;
524 unsigned int mpu_17 : 1;
525 unsigned int mpu_18 : 1;
526 unsigned int mpu_19 : 1;
527 unsigned int mpu_20 : 1;
528 unsigned int mpu_21 : 1;
529 unsigned int mpu_22 : 1;
530 unsigned int mpu_23 : 1;
531 unsigned int mpu_24 : 1;
532 unsigned int mpu_25 : 1;
533 unsigned int mpu_26 : 1;
534 unsigned int mpu_27 : 1;
535 unsigned int mpu_28 : 1;
536 unsigned int mpu_29 : 1;
537 unsigned int mpu_30 : 1;
538 unsigned int mpu_31 : 1;
539 unsigned int spu0_8 : 1;
540 unsigned int spu0_9 : 1;
541 unsigned int spu0_10 : 1;
542 unsigned int spu0_11 : 1;
543 unsigned int spu0_12 : 1;
544 unsigned int spu0_13 : 1;
545 unsigned int spu0_14 : 1;
546 unsigned int spu0_15 : 1;
547 unsigned int spu1_0 : 1;
548 unsigned int spu1_1 : 1;
549 unsigned int spu1_2 : 1;
550 unsigned int spu1_3 : 1;
551 unsigned int spu1_4 : 1;
552 unsigned int spu1_5 : 1;
553 unsigned int spu1_6 : 1;
554 unsigned int spu1_7 : 1;
555} reg_iop_sw_cpu_r_masked_intr1;
556#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
557
558
559typedef struct {
560 unsigned int mpu_0 : 1;
561 unsigned int mpu_1 : 1;
562 unsigned int mpu_2 : 1;
563 unsigned int mpu_3 : 1;
564 unsigned int mpu_4 : 1;
565 unsigned int mpu_5 : 1;
566 unsigned int mpu_6 : 1;
567 unsigned int mpu_7 : 1;
568 unsigned int spu0_0 : 1;
569 unsigned int spu0_1 : 1;
570 unsigned int spu0_2 : 1;
571 unsigned int spu0_3 : 1;
572 unsigned int spu0_4 : 1;
573 unsigned int spu0_5 : 1;
574 unsigned int spu0_6 : 1;
575 unsigned int spu0_7 : 1;
576 unsigned int dmc_in0 : 1;
577 unsigned int dmc_out0 : 1;
578 unsigned int fifo_in0 : 1;
579 unsigned int fifo_out0 : 1;
580 unsigned int fifo_in0_extra : 1;
581 unsigned int fifo_out0_extra : 1;
582 unsigned int trigger_grp0 : 1;
583 unsigned int trigger_grp1 : 1;
584 unsigned int trigger_grp2 : 1;
585 unsigned int trigger_grp3 : 1;
586 unsigned int trigger_grp4 : 1;
587 unsigned int trigger_grp5 : 1;
588 unsigned int trigger_grp6 : 1;
589 unsigned int trigger_grp7 : 1;
590 unsigned int timer_grp0 : 1;
591 unsigned int timer_grp1 : 1;
592} reg_iop_sw_cpu_rw_intr2_mask;
593#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
594#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
595
596
597typedef struct {
598 unsigned int mpu_0 : 1;
599 unsigned int mpu_1 : 1;
600 unsigned int mpu_2 : 1;
601 unsigned int mpu_3 : 1;
602 unsigned int mpu_4 : 1;
603 unsigned int mpu_5 : 1;
604 unsigned int mpu_6 : 1;
605 unsigned int mpu_7 : 1;
606 unsigned int spu0_0 : 1;
607 unsigned int spu0_1 : 1;
608 unsigned int spu0_2 : 1;
609 unsigned int spu0_3 : 1;
610 unsigned int spu0_4 : 1;
611 unsigned int spu0_5 : 1;
612 unsigned int spu0_6 : 1;
613 unsigned int spu0_7 : 1;
614 unsigned int dummy1 : 16;
615} reg_iop_sw_cpu_rw_ack_intr2;
616#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
617#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
618
619
620typedef struct {
621 unsigned int mpu_0 : 1;
622 unsigned int mpu_1 : 1;
623 unsigned int mpu_2 : 1;
624 unsigned int mpu_3 : 1;
625 unsigned int mpu_4 : 1;
626 unsigned int mpu_5 : 1;
627 unsigned int mpu_6 : 1;
628 unsigned int mpu_7 : 1;
629 unsigned int spu0_0 : 1;
630 unsigned int spu0_1 : 1;
631 unsigned int spu0_2 : 1;
632 unsigned int spu0_3 : 1;
633 unsigned int spu0_4 : 1;
634 unsigned int spu0_5 : 1;
635 unsigned int spu0_6 : 1;
636 unsigned int spu0_7 : 1;
637 unsigned int dmc_in0 : 1;
638 unsigned int dmc_out0 : 1;
639 unsigned int fifo_in0 : 1;
640 unsigned int fifo_out0 : 1;
641 unsigned int fifo_in0_extra : 1;
642 unsigned int fifo_out0_extra : 1;
643 unsigned int trigger_grp0 : 1;
644 unsigned int trigger_grp1 : 1;
645 unsigned int trigger_grp2 : 1;
646 unsigned int trigger_grp3 : 1;
647 unsigned int trigger_grp4 : 1;
648 unsigned int trigger_grp5 : 1;
649 unsigned int trigger_grp6 : 1;
650 unsigned int trigger_grp7 : 1;
651 unsigned int timer_grp0 : 1;
652 unsigned int timer_grp1 : 1;
653} reg_iop_sw_cpu_r_intr2;
654#define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
655
656
657typedef struct {
658 unsigned int mpu_0 : 1;
659 unsigned int mpu_1 : 1;
660 unsigned int mpu_2 : 1;
661 unsigned int mpu_3 : 1;
662 unsigned int mpu_4 : 1;
663 unsigned int mpu_5 : 1;
664 unsigned int mpu_6 : 1;
665 unsigned int mpu_7 : 1;
666 unsigned int spu0_0 : 1;
667 unsigned int spu0_1 : 1;
668 unsigned int spu0_2 : 1;
669 unsigned int spu0_3 : 1;
670 unsigned int spu0_4 : 1;
671 unsigned int spu0_5 : 1;
672 unsigned int spu0_6 : 1;
673 unsigned int spu0_7 : 1;
674 unsigned int dmc_in0 : 1;
675 unsigned int dmc_out0 : 1;
676 unsigned int fifo_in0 : 1;
677 unsigned int fifo_out0 : 1;
678 unsigned int fifo_in0_extra : 1;
679 unsigned int fifo_out0_extra : 1;
680 unsigned int trigger_grp0 : 1;
681 unsigned int trigger_grp1 : 1;
682 unsigned int trigger_grp2 : 1;
683 unsigned int trigger_grp3 : 1;
684 unsigned int trigger_grp4 : 1;
685 unsigned int trigger_grp5 : 1;
686 unsigned int trigger_grp6 : 1;
687 unsigned int trigger_grp7 : 1;
688 unsigned int timer_grp0 : 1;
689 unsigned int timer_grp1 : 1;
690} reg_iop_sw_cpu_r_masked_intr2;
691#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
692
693
694typedef struct {
695 unsigned int mpu_16 : 1;
696 unsigned int mpu_17 : 1;
697 unsigned int mpu_18 : 1;
698 unsigned int mpu_19 : 1;
699 unsigned int mpu_20 : 1;
700 unsigned int mpu_21 : 1;
701 unsigned int mpu_22 : 1;
702 unsigned int mpu_23 : 1;
703 unsigned int spu1_0 : 1;
704 unsigned int spu1_1 : 1;
705 unsigned int spu1_2 : 1;
706 unsigned int spu1_3 : 1;
707 unsigned int spu1_4 : 1;
708 unsigned int spu1_5 : 1;
709 unsigned int spu1_6 : 1;
710 unsigned int spu1_7 : 1;
711 unsigned int dmc_in1 : 1;
712 unsigned int dmc_out1 : 1;
713 unsigned int fifo_in1 : 1;
714 unsigned int fifo_out1 : 1;
715 unsigned int fifo_in1_extra : 1;
716 unsigned int fifo_out1_extra : 1;
717 unsigned int trigger_grp0 : 1;
718 unsigned int trigger_grp1 : 1;
719 unsigned int trigger_grp2 : 1;
720 unsigned int trigger_grp3 : 1;
721 unsigned int trigger_grp4 : 1;
722 unsigned int trigger_grp5 : 1;
723 unsigned int trigger_grp6 : 1;
724 unsigned int trigger_grp7 : 1;
725 unsigned int timer_grp2 : 1;
726 unsigned int timer_grp3 : 1;
727} reg_iop_sw_cpu_rw_intr3_mask;
728#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
729#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
730
731
732typedef struct {
733 unsigned int mpu_16 : 1;
734 unsigned int mpu_17 : 1;
735 unsigned int mpu_18 : 1;
736 unsigned int mpu_19 : 1;
737 unsigned int mpu_20 : 1;
738 unsigned int mpu_21 : 1;
739 unsigned int mpu_22 : 1;
740 unsigned int mpu_23 : 1;
741 unsigned int spu1_0 : 1;
742 unsigned int spu1_1 : 1;
743 unsigned int spu1_2 : 1;
744 unsigned int spu1_3 : 1;
745 unsigned int spu1_4 : 1;
746 unsigned int spu1_5 : 1;
747 unsigned int spu1_6 : 1;
748 unsigned int spu1_7 : 1;
749 unsigned int dummy1 : 16;
750} reg_iop_sw_cpu_rw_ack_intr3;
751#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
752#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
753
754
755typedef struct {
756 unsigned int mpu_16 : 1;
757 unsigned int mpu_17 : 1;
758 unsigned int mpu_18 : 1;
759 unsigned int mpu_19 : 1;
760 unsigned int mpu_20 : 1;
761 unsigned int mpu_21 : 1;
762 unsigned int mpu_22 : 1;
763 unsigned int mpu_23 : 1;
764 unsigned int spu1_0 : 1;
765 unsigned int spu1_1 : 1;
766 unsigned int spu1_2 : 1;
767 unsigned int spu1_3 : 1;
768 unsigned int spu1_4 : 1;
769 unsigned int spu1_5 : 1;
770 unsigned int spu1_6 : 1;
771 unsigned int spu1_7 : 1;
772 unsigned int dmc_in1 : 1;
773 unsigned int dmc_out1 : 1;
774 unsigned int fifo_in1 : 1;
775 unsigned int fifo_out1 : 1;
776 unsigned int fifo_in1_extra : 1;
777 unsigned int fifo_out1_extra : 1;
778 unsigned int trigger_grp0 : 1;
779 unsigned int trigger_grp1 : 1;
780 unsigned int trigger_grp2 : 1;
781 unsigned int trigger_grp3 : 1;
782 unsigned int trigger_grp4 : 1;
783 unsigned int trigger_grp5 : 1;
784 unsigned int trigger_grp6 : 1;
785 unsigned int trigger_grp7 : 1;
786 unsigned int timer_grp2 : 1;
787 unsigned int timer_grp3 : 1;
788} reg_iop_sw_cpu_r_intr3;
789#define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
790
791
792typedef struct {
793 unsigned int mpu_16 : 1;
794 unsigned int mpu_17 : 1;
795 unsigned int mpu_18 : 1;
796 unsigned int mpu_19 : 1;
797 unsigned int mpu_20 : 1;
798 unsigned int mpu_21 : 1;
799 unsigned int mpu_22 : 1;
800 unsigned int mpu_23 : 1;
801 unsigned int spu1_0 : 1;
802 unsigned int spu1_1 : 1;
803 unsigned int spu1_2 : 1;
804 unsigned int spu1_3 : 1;
805 unsigned int spu1_4 : 1;
806 unsigned int spu1_5 : 1;
807 unsigned int spu1_6 : 1;
808 unsigned int spu1_7 : 1;
809 unsigned int dmc_in1 : 1;
810 unsigned int dmc_out1 : 1;
811 unsigned int fifo_in1 : 1;
812 unsigned int fifo_out1 : 1;
813 unsigned int fifo_in1_extra : 1;
814 unsigned int fifo_out1_extra : 1;
815 unsigned int trigger_grp0 : 1;
816 unsigned int trigger_grp1 : 1;
817 unsigned int trigger_grp2 : 1;
818 unsigned int trigger_grp3 : 1;
819 unsigned int trigger_grp4 : 1;
820 unsigned int trigger_grp5 : 1;
821 unsigned int trigger_grp6 : 1;
822 unsigned int trigger_grp7 : 1;
823 unsigned int timer_grp2 : 1;
824 unsigned int timer_grp3 : 1;
825} reg_iop_sw_cpu_r_masked_intr3;
826#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
827
828
829
830enum {
831 regk_iop_sw_cpu_copy = 0x00000000,
832 regk_iop_sw_cpu_no = 0x00000000,
833 regk_iop_sw_cpu_rd = 0x00000002,
834 regk_iop_sw_cpu_reg_copy = 0x00000001,
835 regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
836 regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
837 regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
838 regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
839 regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
840 regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
841 regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
842 regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
843 regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
844 regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
845 regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
846 regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
847 regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
848 regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
849 regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000,
850 regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,
851 regk_iop_sw_cpu_wr = 0x00000003,
852 regk_iop_sw_cpu_yes = 0x00000001
853};
854#endif
855
