LXR linux/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __pinmux_defs_h
   3#define __pinmux_defs_h
   4
   5/*
   6 * This file is autogenerated from
   7 *   file:           ../../inst/pinmux/rtl/guinness/pinmux_regs.r
   8 *     id:           pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp 
   9 *     last modfied: Mon Apr 11 16:09:11 2005
  10 * 
  11 *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
  12 *      id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
  13 * Any changes here will be lost.
  14 *
  15 * -*- buffer-read-only: t -*-
  16 */
  17/* Main access macros */
  18#ifndef REG_RD
  19#define REG_RD( scope, inst, reg ) \
  20  REG_READ( reg_##scope##_##reg, \
  21            (inst) + REG_RD_ADDR_##scope##_##reg )
  22#endif
  23
  24#ifndef REG_WR
  25#define REG_WR( scope, inst, reg, val ) \
  26  REG_WRITE( reg_##scope##_##reg, \
  27             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28#endif
  29
  30#ifndef REG_RD_VECT
  31#define REG_RD_VECT( scope, inst, reg, index ) \
  32  REG_READ( reg_##scope##_##reg, \
  33            (inst) + REG_RD_ADDR_##scope##_##reg + \
  34            (index) * STRIDE_##scope##_##reg )
  35#endif
  36
  37#ifndef REG_WR_VECT
  38#define REG_WR_VECT( scope, inst, reg, index, val ) \
  39  REG_WRITE( reg_##scope##_##reg, \
  40             (inst) + REG_WR_ADDR_##scope##_##reg + \
  41             (index) * STRIDE_##scope##_##reg, (val) )
  42#endif
  43
  44#ifndef REG_RD_INT
  45#define REG_RD_INT( scope, inst, reg ) \
  46  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47#endif
  48
  49#ifndef REG_WR_INT
  50#define REG_WR_INT( scope, inst, reg, val ) \
  51  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52#endif
  53
  54#ifndef REG_RD_INT_VECT
  55#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57            (index) * STRIDE_##scope##_##reg )
  58#endif
  59
  60#ifndef REG_WR_INT_VECT
  61#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63             (index) * STRIDE_##scope##_##reg, (val) )
  64#endif
  65
  66#ifndef REG_TYPE_CONV
  67#define REG_TYPE_CONV( type, orgtype, val ) \
  68  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69#endif
  70
  71#ifndef reg_page_size
  72#define reg_page_size 8192
  73#endif
  74
  75#ifndef REG_ADDR
  76#define REG_ADDR( scope, inst, reg ) \
  77  ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78#endif
  79
  80#ifndef REG_ADDR_VECT
  81#define REG_ADDR_VECT( scope, inst, reg, index ) \
  82  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83    (index) * STRIDE_##scope##_##reg )
  84#endif
  85
  86/* C-code for register scope pinmux */
  87
  88/* Register rw_pa, scope pinmux, type rw */
  89typedef struct {
  90  unsigned int pa0    : 1;
  91  unsigned int pa1    : 1;
  92  unsigned int pa2    : 1;
  93  unsigned int pa3    : 1;
  94  unsigned int pa4    : 1;
  95  unsigned int pa5    : 1;
  96  unsigned int pa6    : 1;
  97  unsigned int pa7    : 1;
  98  unsigned int csp2_n : 1;
  99  unsigned int csp3_n : 1;
 100  unsigned int csp5_n : 1;
 101  unsigned int csp6_n : 1;
 102  unsigned int hsh4   : 1;
 103  unsigned int hsh5   : 1;
 104  unsigned int hsh6   : 1;
 105  unsigned int hsh7   : 1;
 106  unsigned int dummy1 : 16;
 107} reg_pinmux_rw_pa;
 108#define REG_RD_ADDR_pinmux_rw_pa 0
 109#define REG_WR_ADDR_pinmux_rw_pa 0
 110
 111/* Register rw_hwprot, scope pinmux, type rw */
 112typedef struct {
 113  unsigned int ser1     : 1;
 114  unsigned int ser2     : 1;
 115  unsigned int ser3     : 1;
 116  unsigned int sser0    : 1;
 117  unsigned int sser1    : 1;
 118  unsigned int ata0     : 1;
 119  unsigned int ata1     : 1;
 120  unsigned int ata2     : 1;
 121  unsigned int ata3     : 1;
 122  unsigned int ata      : 1;
 123  unsigned int eth1     : 1;
 124  unsigned int eth1_mgm : 1;
 125  unsigned int timer    : 1;
 126  unsigned int p21      : 1;
 127  unsigned int dummy1   : 18;
 128} reg_pinmux_rw_hwprot;
 129#define REG_RD_ADDR_pinmux_rw_hwprot 4
 130#define REG_WR_ADDR_pinmux_rw_hwprot 4
 131
 132/* Register rw_pb_gio, scope pinmux, type rw */
 133typedef struct {
 134  unsigned int pb0  : 1;
 135  unsigned int pb1  : 1;
 136  unsigned int pb2  : 1;
 137  unsigned int pb3  : 1;
 138  unsigned int pb4  : 1;
 139  unsigned int pb5  : 1;
 140  unsigned int pb6  : 1;
 141  unsigned int pb7  : 1;
 142  unsigned int pb8  : 1;
 143  unsigned int pb9  : 1;
 144  unsigned int pb10 : 1;
 145  unsigned int pb11 : 1;
 146  unsigned int pb12 : 1;
 147  unsigned int pb13 : 1;
 148  unsigned int pb14 : 1;
 149  unsigned int pb15 : 1;
 150  unsigned int pb16 : 1;
 151  unsigned int pb17 : 1;
 152  unsigned int dummy1 : 14;
 153} reg_pinmux_rw_pb_gio;
 154#define REG_RD_ADDR_pinmux_rw_pb_gio 8
 155#define REG_WR_ADDR_pinmux_rw_pb_gio 8
 156
 157/* Register rw_pb_iop, scope pinmux, type rw */
 158typedef struct {
 159  unsigned int pb0  : 1;
 160  unsigned int pb1  : 1;
 161  unsigned int pb2  : 1;
 162  unsigned int pb3  : 1;
 163  unsigned int pb4  : 1;
 164  unsigned int pb5  : 1;
 165  unsigned int pb6  : 1;
 166  unsigned int pb7  : 1;
 167  unsigned int pb8  : 1;
 168  unsigned int pb9  : 1;
 169  unsigned int pb10 : 1;
 170  unsigned int pb11 : 1;
 171  unsigned int pb12 : 1;
 172  unsigned int pb13 : 1;
 173  unsigned int pb14 : 1;
 174  unsigned int pb15 : 1;
 175  unsigned int pb16 : 1;
 176  unsigned int pb17 : 1;
 177  unsigned int dummy1 : 14;
 178} reg_pinmux_rw_pb_iop;
 179#define REG_RD_ADDR_pinmux_rw_pb_iop 12
 180#define REG_WR_ADDR_pinmux_rw_pb_iop 12
 181
 182/* Register rw_pc_gio, scope pinmux, type rw */
 183typedef struct {
 184  unsigned int pc0  : 1;
 185  unsigned int pc1  : 1;
 186  unsigned int pc2  : 1;
 187  unsigned int pc3  : 1;
 188  unsigned int pc4  : 1;
 189  unsigned int pc5  : 1;
 190  unsigned int pc6  : 1;
 191  unsigned int pc7  : 1;
 192  unsigned int pc8  : 1;
 193  unsigned int pc9  : 1;
 194  unsigned int pc10 : 1;
 195  unsigned int pc11 : 1;
 196  unsigned int pc12 : 1;
 197  unsigned int pc13 : 1;
 198  unsigned int pc14 : 1;
 199  unsigned int pc15 : 1;
 200  unsigned int pc16 : 1;
 201  unsigned int pc17 : 1;
 202  unsigned int dummy1 : 14;
 203} reg_pinmux_rw_pc_gio;
 204#define REG_RD_ADDR_pinmux_rw_pc_gio 16
 205#define REG_WR_ADDR_pinmux_rw_pc_gio 16
 206
 207/* Register rw_pc_iop, scope pinmux, type rw */
 208typedef struct {
 209  unsigned int pc0  : 1;
 210  unsigned int pc1  : 1;
 211  unsigned int pc2  : 1;
 212  unsigned int pc3  : 1;
 213  unsigned int pc4  : 1;
 214  unsigned int pc5  : 1;
 215  unsigned int pc6  : 1;
 216  unsigned int pc7  : 1;
 217  unsigned int pc8  : 1;
 218  unsigned int pc9  : 1;
 219  unsigned int pc10 : 1;
 220  unsigned int pc11 : 1;
 221  unsigned int pc12 : 1;
 222  unsigned int pc13 : 1;
 223  unsigned int pc14 : 1;
 224  unsigned int pc15 : 1;
 225  unsigned int pc16 : 1;
 226  unsigned int pc17 : 1;
 227  unsigned int dummy1 : 14;
 228} reg_pinmux_rw_pc_iop;
 229#define REG_RD_ADDR_pinmux_rw_pc_iop 20
 230#define REG_WR_ADDR_pinmux_rw_pc_iop 20
 231
 232/* Register rw_pd_gio, scope pinmux, type rw */
 233typedef struct {
 234  unsigned int pd0  : 1;
 235  unsigned int pd1  : 1;
 236  unsigned int pd2  : 1;
 237  unsigned int pd3  : 1;
 238  unsigned int pd4  : 1;
 239  unsigned int pd5  : 1;
 240  unsigned int pd6  : 1;
 241  unsigned int pd7  : 1;
 242  unsigned int pd8  : 1;
 243  unsigned int pd9  : 1;
 244  unsigned int pd10 : 1;
 245  unsigned int pd11 : 1;
 246  unsigned int pd12 : 1;
 247  unsigned int pd13 : 1;
 248  unsigned int pd14 : 1;
 249  unsigned int pd15 : 1;
 250  unsigned int pd16 : 1;
 251  unsigned int pd17 : 1;
 252  unsigned int dummy1 : 14;
 253} reg_pinmux_rw_pd_gio;
 254#define REG_RD_ADDR_pinmux_rw_pd_gio 24
 255#define REG_WR_ADDR_pinmux_rw_pd_gio 24
 256
 257/* Register rw_pd_iop, scope pinmux, type rw */
 258typedef struct {
 259  unsigned int pd0  : 1;
 260  unsigned int pd1  : 1;
 261  unsigned int pd2  : 1;
 262  unsigned int pd3  : 1;
 263  unsigned int pd4  : 1;
 264  unsigned int pd5  : 1;
 265  unsigned int pd6  : 1;
 266  unsigned int pd7  : 1;
 267  unsigned int pd8  : 1;
 268  unsigned int pd9  : 1;
 269  unsigned int pd10 : 1;
 270  unsigned int pd11 : 1;
 271  unsigned int pd12 : 1;
 272  unsigned int pd13 : 1;
 273  unsigned int pd14 : 1;
 274  unsigned int pd15 : 1;
 275  unsigned int pd16 : 1;
 276  unsigned int pd17 : 1;
 277  unsigned int dummy1 : 14;
 278} reg_pinmux_rw_pd_iop;
 279#define REG_RD_ADDR_pinmux_rw_pd_iop 28
 280#define REG_WR_ADDR_pinmux_rw_pd_iop 28
 281
 282/* Register rw_pe_gio, scope pinmux, type rw */
 283typedef struct {
 284  unsigned int pe0  : 1;
 285  unsigned int pe1  : 1;
 286  unsigned int pe2  : 1;
 287  unsigned int pe3  : 1;
 288  unsigned int pe4  : 1;
 289  unsigned int pe5  : 1;
 290  unsigned int pe6  : 1;
 291  unsigned int pe7  : 1;
 292  unsigned int pe8  : 1;
 293  unsigned int pe9  : 1;
 294  unsigned int pe10 : 1;
 295  unsigned int pe11 : 1;
 296  unsigned int pe12 : 1;
 297  unsigned int pe13 : 1;
 298  unsigned int pe14 : 1;
 299  unsigned int pe15 : 1;
 300  unsigned int pe16 : 1;
 301  unsigned int pe17 : 1;
 302  unsigned int dummy1 : 14;
 303} reg_pinmux_rw_pe_gio;
 304#define REG_RD_ADDR_pinmux_rw_pe_gio 32
 305#define REG_WR_ADDR_pinmux_rw_pe_gio 32
 306
 307/* Register rw_pe_iop, scope pinmux, type rw */
 308typedef struct {
 309  unsigned int pe0  : 1;
 310  unsigned int pe1  : 1;
 311  unsigned int pe2  : 1;
 312  unsigned int pe3  : 1;
 313  unsigned int pe4  : 1;
 314  unsigned int pe5  : 1;
 315  unsigned int pe6  : 1;
 316  unsigned int pe7  : 1;
 317  unsigned int pe8  : 1;
 318  unsigned int pe9  : 1;
 319  unsigned int pe10 : 1;
 320  unsigned int pe11 : 1;
 321  unsigned int pe12 : 1;
 322  unsigned int pe13 : 1;
 323  unsigned int pe14 : 1;
 324  unsigned int pe15 : 1;
 325  unsigned int pe16 : 1;
 326  unsigned int pe17 : 1;
 327  unsigned int dummy1 : 14;
 328} reg_pinmux_rw_pe_iop;
 329#define REG_RD_ADDR_pinmux_rw_pe_iop 36
 330#define REG_WR_ADDR_pinmux_rw_pe_iop 36
 331
 332/* Register rw_usb_phy, scope pinmux, type rw */
 333typedef struct {
 334  unsigned int en_usb0 : 1;
 335  unsigned int en_usb1 : 1;
 336  unsigned int dummy1  : 30;
 337} reg_pinmux_rw_usb_phy;
 338#define REG_RD_ADDR_pinmux_rw_usb_phy 40
 339#define REG_WR_ADDR_pinmux_rw_usb_phy 40
 340
 341
 342/* Constants */
 343enum {
 344  regk_pinmux_no                           = 0x00000000,
 345  regk_pinmux_rw_hwprot_default            = 0x00000000,
 346  regk_pinmux_rw_pa_default                = 0x00000000,
 347  regk_pinmux_rw_pb_gio_default            = 0x00000000,
 348  regk_pinmux_rw_pb_iop_default            = 0x00000000,
 349  regk_pinmux_rw_pc_gio_default            = 0x00000000,
 350  regk_pinmux_rw_pc_iop_default            = 0x00000000,
 351  regk_pinmux_rw_pd_gio_default            = 0x00000000,
 352  regk_pinmux_rw_pd_iop_default            = 0x00000000,
 353  regk_pinmux_rw_pe_gio_default            = 0x00000000,
 354  regk_pinmux_rw_pe_iop_default            = 0x00000000,
 355  regk_pinmux_rw_usb_phy_default           = 0x00000000,
 356  regk_pinmux_yes                          = 0x00000001
 357};
 358#endif /* __pinmux_defs_h */
 359