LXR linux/arch/ia64/kernel/brl

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Emulation of the "brl" instruction for IA64 processors that
   4 *  don't support it in hardware.
   5 *  Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com>
   6 *
   7 *    02/22/02  D. Mosberger    Clear si_flgs, si_isr, and si_imm to avoid
   8 *                              leaking kernel bits.
   9 */
  10
  11#include <linux/kernel.h>
  12#include <linux/sched/signal.h>
  13#include <linux/uaccess.h>
  14#include <asm/processor.h>
  15
  16extern char ia64_set_b1, ia64_set_b2, ia64_set_b3, ia64_set_b4, ia64_set_b5;
  17
  18struct illegal_op_return {
  19        unsigned long fkt, arg1, arg2, arg3;
  20};
  21
  22/*
  23 *  The unimplemented bits of a virtual address must be set
  24 *  to the value of the most significant implemented bit.
  25 *  unimpl_va_mask includes all unimplemented bits and
  26 *  the most significant implemented bit, so the result
  27 *  of an and operation with the mask must be all 0's
  28 *  or all 1's for the address to be valid.
  29 */
  30#define unimplemented_virtual_address(va) (                                             \
  31        ((va) & local_cpu_data->unimpl_va_mask) != 0 &&                                 \
  32        ((va) & local_cpu_data->unimpl_va_mask) != local_cpu_data->unimpl_va_mask       \
  33)
  34
  35/*
  36 *  The unimplemented bits of a physical address must be 0.
  37 *  unimpl_pa_mask includes all unimplemented bits, so the result
  38 *  of an and operation with the mask must be all 0's for the
  39 *  address to be valid.
  40 */
  41#define unimplemented_physical_address(pa) (            \
  42        ((pa) & local_cpu_data->unimpl_pa_mask) != 0    \
  43)
  44
  45/*
  46 *  Handle an illegal operation fault that was caused by an
  47 *  unimplemented "brl" instruction.
  48 *  If we are not successful (e.g because the illegal operation
  49 *  wasn't caused by a "brl" after all), we return -1.
  50 *  If we are successful, we return either 0 or the address
  51 *  of a "fixup" function for manipulating preserved register
  52 *  state.
  53 */
  54
  55struct illegal_op_return
  56ia64_emulate_brl (struct pt_regs *regs, unsigned long ar_ec)
  57{
  58        unsigned long bundle[2];
  59        unsigned long opcode, btype, qp, offset, cpl;
  60        unsigned long next_ip;
  61        struct siginfo siginfo;
  62        struct illegal_op_return rv;
  63        long tmp_taken, unimplemented_address;
  64
  65        rv.fkt = (unsigned long) -1;
  66
  67        /*
  68         *  Decode the instruction bundle.
  69         */
  70
  71        if (copy_from_user(bundle, (void *) (regs->cr_iip), sizeof(bundle)))
  72                return rv;
  73
  74        next_ip = (unsigned long) regs->cr_iip + 16;
  75
  76        /* "brl" must be in slot 2. */
  77        if (ia64_psr(regs)->ri != 1) return rv;
  78
  79        /* Must be "mlx" template */
  80        if ((bundle[0] & 0x1e) != 0x4) return rv;
  81
  82        opcode = (bundle[1] >> 60);
  83        btype = ((bundle[1] >> 29) & 0x7);
  84        qp = ((bundle[1] >> 23) & 0x3f);
  85        offset = ((bundle[1] & 0x0800000000000000L) << 4)
  86                | ((bundle[1] & 0x00fffff000000000L) >> 32)
  87                | ((bundle[1] & 0x00000000007fffffL) << 40)
  88                | ((bundle[0] & 0xffff000000000000L) >> 24);
  89
  90        tmp_taken = regs->pr & (1L << qp);
  91
  92        switch(opcode) {
  93
  94                case 0xC:
  95                        /*
  96                         *  Long Branch.
  97                         */
  98                        if (btype != 0) return rv;
  99                        rv.fkt = 0;
 100                        if (!(tmp_taken)) {
 101                                /*
 102                                 *  Qualifying predicate is 0.
 103                                 *  Skip instruction.
 104                                 */
 105                                regs->cr_iip = next_ip;
 106                                ia64_psr(regs)->ri = 0;
 107                                return rv;
 108                        }
 109                        break;
 110
 111                case 0xD:
 112                        /*
 113                         *  Long Call.
 114                         */
 115                        rv.fkt = 0;
 116                        if (!(tmp_taken)) {
 117                                /*
 118                                 *  Qualifying predicate is 0.
 119                                 *  Skip instruction.
 120                                 */
 121                                regs->cr_iip = next_ip;
 122                                ia64_psr(regs)->ri = 0;
 123                                return rv;
 124                        }
 125
 126                        /*
 127                         *  BR[btype] = IP+16
 128                         */
 129                        switch(btype) {
 130                                case 0:
 131                                        regs->b0 = next_ip;
 132                                        break;
 133                                case 1:
 134                                        rv.fkt = (unsigned long) &ia64_set_b1;
 135                                        break;
 136                                case 2:
 137                                        rv.fkt = (unsigned long) &ia64_set_b2;
 138                                        break;
 139                                case 3:
 140                                        rv.fkt = (unsigned long) &ia64_set_b3;
 141                                        break;
 142                                case 4:
 143                                        rv.fkt = (unsigned long) &ia64_set_b4;
 144                                        break;
 145                                case 5:
 146                                        rv.fkt = (unsigned long) &ia64_set_b5;
 147                                        break;
 148                                case 6:
 149                                        regs->b6 = next_ip;
 150                                        break;
 151                                case 7:
 152                                        regs->b7 = next_ip;
 153                                        break;
 154                        }
 155                        rv.arg1 = next_ip;
 156
 157                        /*
 158                         *  AR[PFS].pfm = CFM
 159                         *  AR[PFS].pec = AR[EC]
 160                         *  AR[PFS].ppl = PSR.cpl
 161                         */
 162                        cpl = ia64_psr(regs)->cpl;
 163                        regs->ar_pfs = ((regs->cr_ifs & 0x3fffffffff)
 164                                        | (ar_ec << 52) | (cpl << 62));
 165
 166                        /*
 167                         *  CFM.sof -= CFM.sol
 168                         *  CFM.sol = 0
 169                         *  CFM.sor = 0
 170                         *  CFM.rrb.gr = 0
 171                         *  CFM.rrb.fr = 0
 172                         *  CFM.rrb.pr = 0
 173                         */
 174                        regs->cr_ifs = ((regs->cr_ifs & 0xffffffc00000007f)
 175                                        - ((regs->cr_ifs >> 7) & 0x7f));
 176
 177                        break;
 178
 179                default:
 180                        /*
 181                         *  Unknown opcode.
 182                         */
 183                        return rv;
 184
 185        }
 186
 187        regs->cr_iip += offset;
 188        ia64_psr(regs)->ri = 0;
 189
 190        if (ia64_psr(regs)->it == 0)
 191                unimplemented_address = unimplemented_physical_address(regs->cr_iip);
 192        else
 193                unimplemented_address = unimplemented_virtual_address(regs->cr_iip);
 194
 195        if (unimplemented_address) {
 196                /*
 197                 *  The target address contains unimplemented bits.
 198                 */
 199                printk(KERN_DEBUG "Woah! Unimplemented Instruction Address Trap!\n");
 200                siginfo.si_signo = SIGILL;
 201                siginfo.si_errno = 0;
 202                siginfo.si_flags = 0;
 203                siginfo.si_isr = 0;
 204                siginfo.si_imm = 0;
 205                siginfo.si_code = ILL_BADIADDR;
 206                force_sig_info(SIGILL, &siginfo, current);
 207        } else if (ia64_psr(regs)->tb) {
 208                /*
 209                 *  Branch Tracing is enabled.
 210                 *  Force a taken branch signal.
 211                 */
 212                siginfo.si_signo = SIGTRAP;
 213                siginfo.si_errno = 0;
 214                siginfo.si_code = TRAP_BRANCH;
 215                siginfo.si_flags = 0;
 216                siginfo.si_isr = 0;
 217                siginfo.si_addr = 0;
 218                siginfo.si_imm = 0;
 219                force_sig_info(SIGTRAP, &siginfo, current);
 220        } else if (ia64_psr(regs)->ss) {
 221                /*
 222                 *  Single Step is enabled.
 223                 *  Force a trace signal.
 224                 */
 225                siginfo.si_signo = SIGTRAP;
 226                siginfo.si_errno = 0;
 227                siginfo.si_code = TRAP_TRACE;
 228                siginfo.si_flags = 0;
 229                siginfo.si_isr = 0;
 230                siginfo.si_addr = 0;
 231                siginfo.si_imm = 0;
 232                force_sig_info(SIGTRAP, &siginfo, current);
 233        }
 234        return rv;
 235}
 236