LXR linux/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

   1/*
   2 * Support for MicroBlaze PVR (processor version register)
   3 *
   4 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   5 * Copyright (C) 2007-2009 PetaLogix
   6 * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
   7 *
   8 * This file is subject to the terms and conditions of the GNU General Public
   9 * License. See the file "COPYING" in the main directory of this archive
  10 * for more details.
  11 */
  12
  13#include <linux/init.h>
  14#include <linux/string.h>
  15#include <asm/pvr.h>
  16#include <asm/cpuinfo.h>
  17
  18/*
  19 * Helper macro to map between fields in our struct cpuinfo, and
  20 * the PVR macros in pvr.h.
  21 */
  22
  23#define CI(c, p) { ci->c = PVR_##p(pvr); }
  24
  25#if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE)
  26#define err_printk(x) \
  27        early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n");
  28#else
  29#define err_printk(x) \
  30        pr_info("ERROR: Microblaze " x "-different for PVR and DTS\n");
  31#endif
  32
  33void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
  34{
  35        struct pvr_s pvr;
  36        u32 temp; /* for saving temp value */
  37        get_pvr(&pvr);
  38
  39        CI(ver_code, VERSION);
  40        if (!ci->ver_code) {
  41                pr_err("ERROR: MB has broken PVR regs -> use DTS setting\n");
  42                return;
  43        }
  44
  45        temp = PVR_USE_BARREL(pvr) | PVR_USE_MSR_INSTR(pvr) |
  46                PVR_USE_PCMP_INSTR(pvr) | PVR_USE_DIV(pvr);
  47        if (ci->use_instr != temp)
  48                err_printk("BARREL, MSR, PCMP or DIV");
  49        ci->use_instr = temp;
  50
  51        temp = PVR_USE_HW_MUL(pvr) | PVR_USE_MUL64(pvr);
  52        if (ci->use_mult != temp)
  53                err_printk("HW_MUL");
  54        ci->use_mult = temp;
  55
  56        temp = PVR_USE_FPU(pvr) | PVR_USE_FPU2(pvr);
  57        if (ci->use_fpu != temp)
  58                err_printk("HW_FPU");
  59        ci->use_fpu = temp;
  60
  61        ci->use_exc = PVR_OPCODE_0x0_ILLEGAL(pvr) |
  62                        PVR_UNALIGNED_EXCEPTION(pvr) |
  63                        PVR_ILL_OPCODE_EXCEPTION(pvr) |
  64                        PVR_IOPB_BUS_EXCEPTION(pvr) |
  65                        PVR_DOPB_BUS_EXCEPTION(pvr) |
  66                        PVR_DIV_ZERO_EXCEPTION(pvr) |
  67                        PVR_FPU_EXCEPTION(pvr) |
  68                        PVR_FSL_EXCEPTION(pvr);
  69
  70        CI(pvr_user1, USER1);
  71        CI(pvr_user2, USER2);
  72
  73        CI(mmu, USE_MMU);
  74        CI(mmu_privins, MMU_PRIVINS);
  75        CI(endian, ENDIAN);
  76
  77        CI(use_icache, USE_ICACHE);
  78        CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);
  79        CI(icache_write, ICACHE_ALLOW_WR);
  80        ci->icache_line_length = PVR_ICACHE_LINE_LEN(pvr) << 2;
  81        CI(icache_size, ICACHE_BYTE_SIZE);
  82        CI(icache_base, ICACHE_BASEADDR);
  83        CI(icache_high, ICACHE_HIGHADDR);
  84
  85        CI(use_dcache, USE_DCACHE);
  86        CI(dcache_tagbits, DCACHE_ADDR_TAG_BITS);
  87        CI(dcache_write, DCACHE_ALLOW_WR);
  88        ci->dcache_line_length = PVR_DCACHE_LINE_LEN(pvr) << 2;
  89        CI(dcache_size, DCACHE_BYTE_SIZE);
  90        CI(dcache_base, DCACHE_BASEADDR);
  91        CI(dcache_high, DCACHE_HIGHADDR);
  92
  93        temp = PVR_DCACHE_USE_WRITEBACK(pvr);
  94        if (ci->dcache_wb != temp)
  95                err_printk("DCACHE WB");
  96        ci->dcache_wb = temp;
  97
  98        CI(use_dopb, D_OPB);
  99        CI(use_iopb, I_OPB);
 100        CI(use_dlmb, D_LMB);
 101        CI(use_ilmb, I_LMB);
 102        CI(num_fsl, FSL_LINKS);
 103
 104        CI(irq_edge, INTERRUPT_IS_EDGE);
 105        CI(irq_positive, EDGE_IS_POSITIVE);
 106
 107        CI(area_optimised, AREA_OPTIMISED);
 108
 109        CI(hw_debug, DEBUG_ENABLED);
 110        CI(num_pc_brk, NUMBER_OF_PC_BRK);
 111        CI(num_rd_brk, NUMBER_OF_RD_ADDR_BRK);
 112        CI(num_wr_brk, NUMBER_OF_WR_ADDR_BRK);
 113
 114        CI(fpga_family_code, TARGET_FAMILY);
 115}
 116