1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 07 Ralf Baechle 7 */ 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 10 11#include <asm/cpu.h> 12 13/* 14 * IP27 only comes with R1x000 family processors, all using the same config 15 */ 16#define cpu_has_tlb 1 17#define cpu_has_tlbinv 0 18#define cpu_has_segments 0 19#define cpu_has_eva 0 20#define cpu_has_htw 0 21#define cpu_has_rixiex 0 22#define cpu_has_maar 0 23#define cpu_has_rw_llb 0 24#define cpu_has_3kex 0 25#define cpu_has_4kex 1 26#define cpu_has_3k_cache 0 27#define cpu_has_4k_cache 1 28#define cpu_has_6k_cache 0 29#define cpu_has_8k_cache 0 30#define cpu_has_tx39_cache 0 31#define cpu_has_fpu 1 32#define cpu_has_nofpuex 0 33#define cpu_has_32fpr 1 34#define cpu_has_counter 1 35#define cpu_has_watch 1 36#define cpu_has_64bits 1 37#define cpu_has_divec 0 38#define cpu_has_vce 0 39#define cpu_has_cache_cdex_p 0 40#define cpu_has_cache_cdex_s 0 41#define cpu_has_prefetch 1 42#define cpu_has_mcheck 0 43#define cpu_has_ejtag 0 44#define cpu_has_llsc 1 45#define cpu_has_mips16 0 46#define cpu_has_mips16e2 0 47#define cpu_has_mdmx 0 48#define cpu_has_mips3d 0 49#define cpu_has_smartmips 0 50#define cpu_has_rixi 0 51#define cpu_has_xpa 0 52#define cpu_has_vtag_icache 0 53#define cpu_has_dc_aliases 0 54#define cpu_has_ic_fills_f_dc 0 55 56#define cpu_icache_snoops_remote_store 1 57 58#define cpu_has_mips32r1 0 59#define cpu_has_mips32r2 0 60#define cpu_has_mips64r1 0 61#define cpu_has_mips64r2 0 62#define cpu_has_mips32r6 0 63#define cpu_has_mips64r6 0 64 65#define cpu_has_dsp 0 66#define cpu_has_dsp2 0 67#define cpu_has_mipsmt 0 68#define cpu_has_userlocal 0 69#define cpu_has_inclusive_pcaches 1 70#define cpu_hwrena_impl_bits 0 71#define cpu_has_perf_cntr_intr_bit 0 72#define cpu_has_vz 0 73#define cpu_has_fre 0 74#define cpu_has_cdmm 0 75 76#define cpu_dcache_line_size() 32 77#define cpu_icache_line_size() 64 78#define cpu_scache_line_size() 128 79 80#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ 81