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10#ifndef _ASM_POWERPC_REG_H
11#define _ASM_POWERPC_REG_H
12#ifdef __KERNEL__
13
14#include <linux/stringify.h>
15#include <asm/cputable.h>
16
17
18#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
19#include <asm/reg_booke.h>
20#endif
21
22#ifdef CONFIG_FSL_EMB_PERFMON
23#include <asm/reg_fsl_emb.h>
24#endif
25
26#ifdef CONFIG_PPC_8xx
27#include <asm/reg_8xx.h>
28#endif
29
30#define MSR_SF_LG 63
31#define MSR_ISF_LG 61
32#define MSR_HV_LG 60
33#define MSR_TS_T_LG 34
34#define MSR_TS_S_LG 33
35#define MSR_TS_LG 33
36#define MSR_TM_LG 32
37#define MSR_VEC_LG 25
38#define MSR_VSX_LG 23
39#define MSR_POW_LG 18
40#define MSR_WE_LG 18
41#define MSR_TGPR_LG 17
42#define MSR_CE_LG 17
43#define MSR_ILE_LG 16
44#define MSR_EE_LG 15
45#define MSR_PR_LG 14
46#define MSR_FP_LG 13
47#define MSR_ME_LG 12
48#define MSR_FE0_LG 11
49#define MSR_SE_LG 10
50#define MSR_BE_LG 9
51#define MSR_DE_LG 9
52#define MSR_FE1_LG 8
53#define MSR_IP_LG 6
54#define MSR_IR_LG 5
55#define MSR_DR_LG 4
56#define MSR_PE_LG 3
57#define MSR_PX_LG 2
58#define MSR_PMM_LG 2
59#define MSR_RI_LG 1
60#define MSR_LE_LG 0
61
62#ifdef __ASSEMBLY__
63#define __MASK(X) (1<<(X))
64#else
65#define __MASK(X) (1UL<<(X))
66#endif
67
68#ifdef CONFIG_PPC64
69#define MSR_SF __MASK(MSR_SF_LG)
70#define MSR_ISF __MASK(MSR_ISF_LG)
71#define MSR_HV __MASK(MSR_HV_LG)
72#else
73
74#define MSR_SF 0
75#define MSR_ISF 0
76#define MSR_HV 0
77#endif
78
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81
82
83#ifndef MSR_SPE
84#define MSR_SPE 0
85#endif
86
87#define MSR_VEC __MASK(MSR_VEC_LG)
88#define MSR_VSX __MASK(MSR_VSX_LG)
89#define MSR_POW __MASK(MSR_POW_LG)
90#define MSR_WE __MASK(MSR_WE_LG)
91#define MSR_TGPR __MASK(MSR_TGPR_LG)
92#define MSR_CE __MASK(MSR_CE_LG)
93#define MSR_ILE __MASK(MSR_ILE_LG)
94#define MSR_EE __MASK(MSR_EE_LG)
95#define MSR_PR __MASK(MSR_PR_LG)
96#define MSR_FP __MASK(MSR_FP_LG)
97#define MSR_ME __MASK(MSR_ME_LG)
98#define MSR_FE0 __MASK(MSR_FE0_LG)
99#define MSR_SE __MASK(MSR_SE_LG)
100#define MSR_BE __MASK(MSR_BE_LG)
101#define MSR_DE __MASK(MSR_DE_LG)
102#define MSR_FE1 __MASK(MSR_FE1_LG)
103#define MSR_IP __MASK(MSR_IP_LG)
104#define MSR_IR __MASK(MSR_IR_LG)
105#define MSR_DR __MASK(MSR_DR_LG)
106#define MSR_PE __MASK(MSR_PE_LG)
107#define MSR_PX __MASK(MSR_PX_LG)
108#ifndef MSR_PMM
109#define MSR_PMM __MASK(MSR_PMM_LG)
110#endif
111#define MSR_RI __MASK(MSR_RI_LG)
112#define MSR_LE __MASK(MSR_LE_LG)
113
114#define MSR_TM __MASK(MSR_TM_LG)
115#define MSR_TS_N 0
116#define MSR_TS_S __MASK(MSR_TS_S_LG)
117#define MSR_TS_T __MASK(MSR_TS_T_LG)
118#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S)
119#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0)
120#define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK)
121#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
122#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
123
124#if defined(CONFIG_PPC_BOOK3S_64)
125#define MSR_64BIT MSR_SF
126
127
128#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
129#ifdef __BIG_ENDIAN__
130#define MSR_ __MSR
131#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
132#else
133#define MSR_ (__MSR | MSR_LE)
134#define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
135#endif
136#define MSR_KERNEL (MSR_ | MSR_64BIT)
137#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
138#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
139#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
140
141#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
142#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
143#endif
144
145#ifndef MSR_64BIT
146#define MSR_64BIT 0
147#endif
148
149
150#define PSSCR_RL_MASK 0x0000000F
151#define PSSCR_MTL_MASK 0x000000F0
152#define PSSCR_TR_MASK 0x00000300
153#define PSSCR_PSLL_MASK 0x000F0000
154#define PSSCR_EC 0x00100000
155#define PSSCR_ESL 0x00200000
156#define PSSCR_SD 0x00400000
157#define PSSCR_PLS 0xf000000000000000
158#define PSSCR_GUEST_VIS 0xf0000000000003ff
159
160
161#define FPSCR_FX 0x80000000
162#define FPSCR_FEX 0x40000000
163#define FPSCR_VX 0x20000000
164#define FPSCR_OX 0x10000000
165#define FPSCR_UX 0x08000000
166#define FPSCR_ZX 0x04000000
167#define FPSCR_XX 0x02000000
168#define FPSCR_VXSNAN 0x01000000
169#define FPSCR_VXISI 0x00800000
170#define FPSCR_VXIDI 0x00400000
171#define FPSCR_VXZDZ 0x00200000
172#define FPSCR_VXIMZ 0x00100000
173#define FPSCR_VXVC 0x00080000
174#define FPSCR_FR 0x00040000
175#define FPSCR_FI 0x00020000
176#define FPSCR_FPRF 0x0001f000
177#define FPSCR_FPCC 0x0000f000
178#define FPSCR_VXSOFT 0x00000400
179#define FPSCR_VXSQRT 0x00000200
180#define FPSCR_VXCVI 0x00000100
181#define FPSCR_VE 0x00000080
182#define FPSCR_OE 0x00000040
183#define FPSCR_UE 0x00000020
184#define FPSCR_ZE 0x00000010
185#define FPSCR_XE 0x00000008
186#define FPSCR_NI 0x00000004
187#define FPSCR_RN 0x00000003
188
189
190#define SPEFSCR_SOVH 0x80000000
191#define SPEFSCR_OVH 0x40000000
192#define SPEFSCR_FGH 0x20000000
193#define SPEFSCR_FXH 0x10000000
194#define SPEFSCR_FINVH 0x08000000
195#define SPEFSCR_FDBZH 0x04000000
196#define SPEFSCR_FUNFH 0x02000000
197#define SPEFSCR_FOVFH 0x01000000
198#define SPEFSCR_FINXS 0x00200000
199#define SPEFSCR_FINVS 0x00100000
200#define SPEFSCR_FDBZS 0x00080000
201#define SPEFSCR_FUNFS 0x00040000
202#define SPEFSCR_FOVFS 0x00020000
203#define SPEFSCR_MODE 0x00010000
204#define SPEFSCR_SOV 0x00008000
205#define SPEFSCR_OV 0x00004000
206#define SPEFSCR_FG 0x00002000
207#define SPEFSCR_FX 0x00001000
208#define SPEFSCR_FINV 0x00000800
209#define SPEFSCR_FDBZ 0x00000400
210#define SPEFSCR_FUNF 0x00000200
211#define SPEFSCR_FOVF 0x00000100
212#define SPEFSCR_FINXE 0x00000040
213#define SPEFSCR_FINVE 0x00000020
214#define SPEFSCR_FDBZE 0x00000010
215#define SPEFSCR_FUNFE 0x00000008
216#define SPEFSCR_FOVFE 0x00000004
217#define SPEFSCR_FRMC 0x00000003
218
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220
221#ifdef CONFIG_40x
222#define SPRN_PID 0x3B1
223#else
224#define SPRN_PID 0x030
225#ifdef CONFIG_BOOKE
226#define SPRN_PID0 SPRN_PID
227#endif
228#endif
229
230#define SPRN_CTR 0x009
231#define SPRN_DSCR 0x11
232#define SPRN_CFAR 0x1c
233#define SPRN_AMR 0x1d
234#define SPRN_UAMOR 0x9d
235#define SPRN_AMOR 0x15d
236#define SPRN_ACOP 0x1F
237#define SPRN_TFIAR 0x81
238#define SPRN_TEXASR 0x82
239#define SPRN_TEXASRU 0x83
240#define TEXASR_FS __MASK(63-36)
241#define SPRN_TFHAR 0x80
242#define SPRN_TIDR 144
243#define SPRN_CTRLF 0x088
244#define SPRN_CTRLT 0x098
245#define CTRL_CT 0xc0000000
246#define CTRL_CT0 0x80000000
247#define CTRL_CT1 0x40000000
248#define CTRL_TE 0x00c00000
249#define CTRL_RUNLATCH 0x1
250#define SPRN_DAWR 0xB4
251#define SPRN_RPR 0xBA
252#define SPRN_CIABR 0xBB
253#define CIABR_PRIV 0x3
254#define CIABR_PRIV_USER 1
255#define CIABR_PRIV_SUPER 2
256#define CIABR_PRIV_HYPER 3
257#define SPRN_DAWRX 0xBC
258#define DAWRX_USER __MASK(0)
259#define DAWRX_KERNEL __MASK(1)
260#define DAWRX_HYP __MASK(2)
261#define DAWRX_WTI __MASK(3)
262#define DAWRX_WT __MASK(4)
263#define DAWRX_DR __MASK(5)
264#define DAWRX_DW __MASK(6)
265#define SPRN_DABR 0x3F5
266#define SPRN_DABR2 0x13D
267#define SPRN_DABRX 0x3F7
268#define DABRX_USER __MASK(0)
269#define DABRX_KERNEL __MASK(1)
270#define DABRX_HYP __MASK(2)
271#define DABRX_BTI __MASK(3)
272#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
273#define SPRN_DAR 0x013
274#define SPRN_DBCR 0x136
275#define SPRN_DSISR 0x012
276#define DSISR_BAD_DIRECT_ST 0x80000000
277#define DSISR_NOHPTE 0x40000000
278#define DSISR_ATTR_CONFLICT 0x20000000
279#define DSISR_NOEXEC_OR_G 0x10000000
280#define DSISR_PROTFAULT 0x08000000
281#define DSISR_BADACCESS 0x04000000
282#define DSISR_ISSTORE 0x02000000
283#define DSISR_DABRMATCH 0x00400000
284#define DSISR_NOSEGMENT 0x00200000
285#define DSISR_KEYFAULT 0x00200000
286#define DSISR_BAD_EXT_CTRL 0x00100000
287#define DSISR_UNSUPP_MMU 0x00080000
288#define DSISR_SET_RC 0x00040000
289#define DSISR_PRTABLE_FAULT 0x00020000
290#define DSISR_ICSWX_NO_CT 0x00004000
291#define DSISR_BAD_COPYPASTE 0x00000008
292#define DSISR_BAD_AMO 0x00000004
293#define DSISR_BAD_CI_LDST 0x00000002
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310#define DSISR_BAD_FAULT_32S (DSISR_BAD_DIRECT_ST | \
311 DSISR_BADACCESS | \
312 DSISR_BAD_EXT_CTRL)
313#define DSISR_BAD_FAULT_64S (DSISR_BAD_FAULT_32S | \
314 DSISR_ATTR_CONFLICT | \
315 DSISR_KEYFAULT | \
316 DSISR_UNSUPP_MMU | \
317 DSISR_PRTABLE_FAULT | \
318 DSISR_ICSWX_NO_CT | \
319 DSISR_BAD_COPYPASTE | \
320 DSISR_BAD_AMO | \
321 DSISR_BAD_CI_LDST)
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324
325
326#define DSISR_SRR1_MATCH_32S (DSISR_NOHPTE | \
327 DSISR_NOEXEC_OR_G | \
328 DSISR_PROTFAULT)
329#define DSISR_SRR1_MATCH_64S (DSISR_SRR1_MATCH_32S | \
330 DSISR_KEYFAULT | \
331 DSISR_UNSUPP_MMU | \
332 DSISR_SET_RC | \
333 DSISR_PRTABLE_FAULT)
334
335#define SPRN_TBRL 0x10C
336#define SPRN_TBRU 0x10D
337#define SPRN_CIR 0x11B
338#define SPRN_TBWL 0x11C
339#define SPRN_TBWU 0x11D
340#define SPRN_TBU40 0x11E
341#define SPRN_SPURR 0x134
342#define SPRN_HSPRG0 0x130
343#define SPRN_HSPRG1 0x131
344#define SPRN_HDSISR 0x132
345#define SPRN_HDAR 0x133
346#define SPRN_HDEC 0x136
347#define SPRN_HIOR 0x137
348#define SPRN_RMOR 0x138
349#define SPRN_HRMOR 0x139
350#define SPRN_HSRR0 0x13A
351#define SPRN_HSRR1 0x13B
352#define SPRN_ASDR 0x330
353#define SPRN_IC 0x350
354#define SPRN_VTB 0x351
355#define SPRN_LDBAR 0x352
356#define SPRN_PMICR 0x354
357#define SPRN_PMSR 0x355
358#define SPRN_PMMAR 0x356
359#define SPRN_PSSCR 0x357
360#define SPRN_PSSCR_PR 0x337
361#define SPRN_PMCR 0x374
362
363
364#define FSCR_SCV_LG 12
365#define FSCR_MSGP_LG 10
366#define FSCR_TAR_LG 8
367#define FSCR_EBB_LG 7
368#define FSCR_TM_LG 5
369#define FSCR_BHRB_LG 4
370#define FSCR_PM_LG 3
371#define FSCR_DSCR_LG 2
372#define FSCR_VECVSX_LG 1
373#define FSCR_FP_LG 0
374#define SPRN_FSCR 0x099
375#define FSCR_SCV __MASK(FSCR_SCV_LG)
376#define FSCR_TAR __MASK(FSCR_TAR_LG)
377#define FSCR_EBB __MASK(FSCR_EBB_LG)
378#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
379#define SPRN_HFSCR 0xbe
380#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
381#define HFSCR_TAR __MASK(FSCR_TAR_LG)
382#define HFSCR_EBB __MASK(FSCR_EBB_LG)
383#define HFSCR_TM __MASK(FSCR_TM_LG)
384#define HFSCR_PM __MASK(FSCR_PM_LG)
385#define HFSCR_BHRB __MASK(FSCR_BHRB_LG)
386#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
387#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
388#define HFSCR_FP __MASK(FSCR_FP_LG)
389#define SPRN_TAR 0x32f
390#define SPRN_LPCR 0x13E
391#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
392#define LPCR_VPM1 ASM_CONST(0x4000000000000000)
393#define LPCR_ISL ASM_CONST(0x2000000000000000)
394#define LPCR_VC_SH 61
395#define LPCR_DPFD_SH 52
396#define LPCR_DPFD (ASM_CONST(7) << LPCR_DPFD_SH)
397#define LPCR_VRMASD_SH 47
398#define LPCR_VRMASD (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
399#define LPCR_VRMA_L ASM_CONST(0x0008000000000000)
400#define LPCR_VRMA_LP0 ASM_CONST(0x0001000000000000)
401#define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
402#define LPCR_RMLS 0x1C000000
403#define LPCR_RMLS_SH 26
404#define LPCR_ILE ASM_CONST(0x0000000002000000)
405#define LPCR_AIL ASM_CONST(0x0000000001800000)
406#define LPCR_AIL_0 ASM_CONST(0x0000000000000000)
407#define LPCR_AIL_3 ASM_CONST(0x0000000001800000)
408#define LPCR_ONL ASM_CONST(0x0000000000040000)
409#define LPCR_LD ASM_CONST(0x0000000000020000)
410#define LPCR_PECE ASM_CONST(0x000000000001f000)
411#define LPCR_PECEDP ASM_CONST(0x0000000000010000)
412#define LPCR_PECEDH ASM_CONST(0x0000000000008000)
413#define LPCR_PECE0 ASM_CONST(0x0000000000004000)
414#define LPCR_PECE1 ASM_CONST(0x0000000000002000)
415#define LPCR_PECE2 ASM_CONST(0x0000000000001000)
416#define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000)
417#define LPCR_MER ASM_CONST(0x0000000000000800)
418#define LPCR_MER_SH 11
419#define LPCR_GTSE ASM_CONST(0x0000000000000400)
420#define LPCR_TC ASM_CONST(0x0000000000000200)
421#define LPCR_HEIC ASM_CONST(0x0000000000000010)
422#define LPCR_LPES 0x0000000c
423#define LPCR_LPES0 ASM_CONST(0x0000000000000008)
424#define LPCR_LPES1 ASM_CONST(0x0000000000000004)
425#define LPCR_LPES_SH 2
426#define LPCR_RMI ASM_CONST(0x0000000000000002)
427#define LPCR_HVICE ASM_CONST(0x0000000000000002)
428#define LPCR_HDICE ASM_CONST(0x0000000000000001)
429#define LPCR_UPRT ASM_CONST(0x0000000000400000)
430#define LPCR_HR ASM_CONST(0x0000000000100000)
431#ifndef SPRN_LPID
432#define SPRN_LPID 0x13F
433#endif
434#define LPID_RSVD 0x3ff
435#define SPRN_HMER 0x150
436#define SPRN_HMEER 0x151
437#define SPRN_PCR 0x152
438#define PCR_VEC_DIS (1ul << (63-0))
439#define PCR_VSX_DIS (1ul << (63-1))
440#define PCR_TM_DIS (1ul << (63-2))
441
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444
445
446#define PCR_ARCH_207 0x8
447#define PCR_ARCH_206 0x4
448#define PCR_ARCH_205 0x2
449#define SPRN_HEIR 0x153
450#define SPRN_TLBINDEXR 0x154
451#define SPRN_TLBVPNR 0x155
452#define SPRN_TLBRPNR 0x156
453#define SPRN_TLBLPIDR 0x157
454#define SPRN_DBAT0L 0x219
455#define SPRN_DBAT0U 0x218
456#define SPRN_DBAT1L 0x21B
457#define SPRN_DBAT1U 0x21A
458#define SPRN_DBAT2L 0x21D
459#define SPRN_DBAT2U 0x21C
460#define SPRN_DBAT3L 0x21F
461#define SPRN_DBAT3U 0x21E
462#define SPRN_DBAT4L 0x239
463#define SPRN_DBAT4U 0x238
464#define SPRN_DBAT5L 0x23B
465#define SPRN_DBAT5U 0x23A
466#define SPRN_DBAT6L 0x23D
467#define SPRN_DBAT6U 0x23C
468#define SPRN_DBAT7L 0x23F
469#define SPRN_DBAT7U 0x23E
470#define SPRN_PPR 0x380
471#define SPRN_TSCR 0x399
472
473#define SPRN_DEC 0x016
474#define SPRN_DER 0x095
475#define DER_RSTE 0x40000000
476#define DER_CHSTPE 0x20000000
477#define DER_MCIE 0x10000000
478#define DER_EXTIE 0x02000000
479#define DER_ALIE 0x01000000
480#define DER_PRIE 0x00800000
481#define DER_FPUVIE 0x00400000
482#define DER_DECIE 0x00200000
483#define DER_SYSIE 0x00040000
484#define DER_TRE 0x00020000
485#define DER_SEIE 0x00004000
486#define DER_ITLBMSE 0x00002000
487#define DER_ITLBERE 0x00001000
488#define DER_DTLBMSE 0x00000800
489#define DER_DTLBERE 0x00000400
490#define DER_LBRKE 0x00000008
491#define DER_IBRKE 0x00000004
492#define DER_EBRKE 0x00000002
493#define DER_DPIE 0x00000001
494#define SPRN_DMISS 0x3D0
495#define SPRN_DHDES 0x0B1
496#define SPRN_DPDES 0x0B0
497#define SPRN_EAR 0x11A
498#define SPRN_HASH1 0x3D2
499#define SPRN_HASH2 0x3D3
500#define SPRN_HID0 0x3F0
501#define HID0_HDICE_SH (63 - 23)
502#define HID0_EMCP (1<<31)
503#define HID0_EBA (1<<29)
504#define HID0_EBD (1<<28)
505#define HID0_SBCLK (1<<27)
506#define HID0_EICE (1<<26)
507#define HID0_TBEN (1<<26)
508#define HID0_ECLK (1<<25)
509#define HID0_PAR (1<<24)
510#define HID0_STEN (1<<24)
511#define HID0_HIGH_BAT (1<<23)
512#define HID0_DOZE (1<<23)
513#define HID0_NAP (1<<22)
514#define HID0_SLEEP (1<<21)
515#define HID0_DPM (1<<20)
516#define HID0_BHTCLR (1<<18)
517#define HID0_XAEN (1<<17)
518#define HID0_NHR (1<<16)
519#define HID0_ICE (1<<15)
520#define HID0_DCE (1<<14)
521#define HID0_ILOCK (1<<13)
522#define HID0_DLOCK (1<<12)
523#define HID0_ICFI (1<<11)
524#define HID0_DCI (1<<10)
525#define HID0_SPD (1<<9)
526#define HID0_DAPUEN (1<<8)
527#define HID0_SGE (1<<7)
528#define HID0_SIED (1<<7)
529#define HID0_DCFA (1<<6)
530#define HID0_LRSTK (1<<4)
531#define HID0_BTIC (1<<5)
532#define HID0_ABE (1<<3)
533#define HID0_FOLD (1<<3)
534#define HID0_BHTE (1<<2)
535#define HID0_BTCD (1<<1)
536#define HID0_NOPDST (1<<1)
537#define HID0_NOPTI (1<<0)
538
539#define HID0_POWER8_4LPARMODE __MASK(61)
540#define HID0_POWER8_2LPARMODE __MASK(57)
541#define HID0_POWER8_1TO2LPAR __MASK(52)
542#define HID0_POWER8_1TO4LPAR __MASK(51)
543#define HID0_POWER8_DYNLPARDIS __MASK(48)
544
545
546#define HID0_POWER9_RADIX __MASK(63 - 8)
547
548#define SPRN_HID1 0x3F1
549#ifdef CONFIG_6xx
550#define HID1_EMCP (1<<31)
551#define HID1_DFS (1<<22)
552#define HID1_PC0 (1<<16)
553#define HID1_PC1 (1<<15)
554#define HID1_PC2 (1<<14)
555#define HID1_PC3 (1<<13)
556#define HID1_SYNCBE (1<<11)
557#define HID1_ABE (1<<10)
558#define HID1_PS (1<<16)
559#endif
560#define SPRN_HID2 0x3F8
561#define SPRN_HID2_GEKKO 0x398
562#define SPRN_IABR 0x3F2
563#define SPRN_IABR2 0x3FA
564#define SPRN_IBCR 0x135
565#define SPRN_IAMR 0x03D
566#define SPRN_HID4 0x3F4
567#define HID4_LPES0 (1ul << (63-0))
568#define HID4_RMLS2_SH (63 - 2)
569#define HID4_LPID5_SH (63 - 6)
570#define HID4_RMOR_SH (63 - 22)
571#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH)
572#define HID4_LPES1 (1 << (63-57))
573#define HID4_RMLS0_SH (63 - 58)
574#define HID4_LPID1_SH 0
575#define SPRN_HID4_GEKKO 0x3F3
576#define SPRN_HID5 0x3F6
577#define SPRN_HID6 0x3F9
578#define HID6_LB (0x0F<<12)
579#define HID6_DLP (1<<20)
580#define SPRN_TSC_CELL 0x399
581#define TSC_CELL_DEC_ENABLE_0 0x400000
582#define TSC_CELL_DEC_ENABLE_1 0x200000
583#define TSC_CELL_EE_ENABLE 0x100000
584#define TSC_CELL_EE_BOOST 0x080000
585#define SPRN_TSC 0x3FD
586#define SPRN_TST 0x3FC
587#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
588#define SPRN_IAC1 0x3F4
589#define SPRN_IAC2 0x3F5
590#endif
591#define SPRN_IBAT0L 0x211
592#define SPRN_IBAT0U 0x210
593#define SPRN_IBAT1L 0x213
594#define SPRN_IBAT1U 0x212
595#define SPRN_IBAT2L 0x215
596#define SPRN_IBAT2U 0x214
597#define SPRN_IBAT3L 0x217
598#define SPRN_IBAT3U 0x216
599#define SPRN_IBAT4L 0x231
600#define SPRN_IBAT4U 0x230
601#define SPRN_IBAT5L 0x233
602#define SPRN_IBAT5U 0x232
603#define SPRN_IBAT6L 0x235
604#define SPRN_IBAT6U 0x234
605#define SPRN_IBAT7L 0x237
606#define SPRN_IBAT7U 0x236
607#define SPRN_ICMP 0x3D5
608#define SPRN_ICTC 0x3FB
609#ifndef SPRN_ICTRL
610#define SPRN_ICTRL 0x3F3
611#endif
612#define ICTRL_EICE 0x08000000
613#define ICTRL_EDC 0x04000000
614#define ICTRL_EICP 0x00000100
615#define SPRN_IMISS 0x3D4
616#define SPRN_IMMR 0x27E
617#define SPRN_L2CR 0x3F9
618#define SPRN_L2CR2 0x3f8
619#define L2CR_L2E 0x80000000
620#define L2CR_L2PE 0x40000000
621#define L2CR_L2SIZ_MASK 0x30000000
622#define L2CR_L2SIZ_256KB 0x10000000
623#define L2CR_L2SIZ_512KB 0x20000000
624#define L2CR_L2SIZ_1MB 0x30000000
625#define L2CR_L2CLK_MASK 0x0e000000
626#define L2CR_L2CLK_DISABLED 0x00000000
627#define L2CR_L2CLK_DIV1 0x02000000
628#define L2CR_L2CLK_DIV1_5 0x04000000
629#define L2CR_L2CLK_DIV2 0x08000000
630#define L2CR_L2CLK_DIV2_5 0x0a000000
631#define L2CR_L2CLK_DIV3 0x0c000000
632#define L2CR_L2RAM_MASK 0x01800000
633#define L2CR_L2RAM_FLOW 0x00000000
634#define L2CR_L2RAM_PIPE 0x01000000
635#define L2CR_L2RAM_PIPE_LW 0x01800000
636#define L2CR_L2DO 0x00400000
637#define L2CR_L2I 0x00200000
638#define L2CR_L2CTL 0x00100000
639#define L2CR_L2WT 0x00080000
640#define L2CR_L2TS 0x00040000
641#define L2CR_L2OH_MASK 0x00030000
642#define L2CR_L2OH_0_5 0x00000000
643#define L2CR_L2OH_1_0 0x00010000
644#define L2CR_L2SL 0x00008000
645#define L2CR_L2DF 0x00004000
646#define L2CR_L2BYP 0x00002000
647#define L2CR_L2IP 0x00000001
648#define L2CR_L2IO_745x 0x00100000
649#define L2CR_L2DO_745x 0x00010000
650#define L2CR_L2REP_745x 0x00001000
651#define L2CR_L2HWF_745x 0x00000800
652#define SPRN_L3CR 0x3FA
653#define L3CR_L3E 0x80000000
654#define L3CR_L3PE 0x40000000
655#define L3CR_L3APE 0x20000000
656#define L3CR_L3SIZ 0x10000000
657#define L3CR_L3CLKEN 0x08000000
658#define L3CR_L3RES 0x04000000
659#define L3CR_L3CLKDIV 0x03800000
660#define L3CR_L3IO 0x00400000
661#define L3CR_L3SPO 0x00040000
662#define L3CR_L3CKSP 0x00030000
663#define L3CR_L3PSP 0x0000e000
664#define L3CR_L3REP 0x00001000
665#define L3CR_L3HWF 0x00000800
666#define L3CR_L3I 0x00000400
667#define L3CR_L3RT 0x00000300
668#define L3CR_L3NIRCA 0x00000080
669#define L3CR_L3DO 0x00000040
670#define L3CR_PMEN 0x00000004
671#define L3CR_PMSIZ 0x00000001
672
673#define SPRN_MSSCR0 0x3f6
674#define SPRN_MSSSR0 0x3f7
675#define SPRN_LDSTCR 0x3f8
676#define SPRN_LDSTDB 0x3f4
677#define SPRN_LR 0x008
678#ifndef SPRN_PIR
679#define SPRN_PIR 0x3FF
680#endif
681#define SPRN_TIR 0x1BE
682#define SPRN_PTCR 0x1D0
683#define SPRN_PSPB 0x09F
684#define SPRN_PTEHI 0x3D5
685#define SPRN_PTELO 0x3D6
686#define SPRN_PURR 0x135
687#define SPRN_PVR 0x11F
688#define SPRN_RPA 0x3D6
689#define SPRN_SDA 0x3BF
690#define SPRN_SDR1 0x019
691#define SPRN_ASR 0x118
692#define SPRN_SIA 0x3BB
693#define SPRN_SPRG0 0x110
694#define SPRN_SPRG1 0x111
695#define SPRN_SPRG2 0x112
696#define SPRN_SPRG3 0x113
697#define SPRN_USPRG3 0x103
698#define SPRN_SPRG4 0x114
699#define SPRN_USPRG4 0x104
700#define SPRN_SPRG5 0x115
701#define SPRN_USPRG5 0x105
702#define SPRN_SPRG6 0x116
703#define SPRN_USPRG6 0x106
704#define SPRN_SPRG7 0x117
705#define SPRN_USPRG7 0x107
706#define SPRN_SRR0 0x01A
707#define SPRN_SRR1 0x01B
708#define SRR1_ISI_NOPT 0x40000000
709#define SRR1_ISI_N_OR_G 0x10000000
710#define SRR1_ISI_PROT 0x08000000
711#define SRR1_WAKEMASK 0x00380000
712#define SRR1_WAKEMASK_P8 0x003c0000
713#define SRR1_WAKEMCE_RESVD 0x003c0000
714#define SRR1_WAKESYSERR 0x00300000
715#define SRR1_WAKEEE 0x00200000
716#define SRR1_WAKEHVI 0x00240000
717#define SRR1_WAKEMT 0x00280000
718#define SRR1_WAKEHMI 0x00280000
719#define SRR1_WAKEDEC 0x00180000
720#define SRR1_WAKEDBELL 0x00140000
721#define SRR1_WAKETHERM 0x00100000
722#define SRR1_WAKERESET 0x00100000
723#define SRR1_WAKEHDBELL 0x000c0000
724#define SRR1_WAKESTATE 0x00030000
725#define SRR1_WS_DEEPEST 0x00030000
726
727#define SRR1_WS_DEEPER 0x00020000
728#define SRR1_WS_DEEP 0x00010000
729#define SRR1_PROGTM 0x00200000
730#define SRR1_PROGFPE 0x00100000
731#define SRR1_PROGILL 0x00080000
732#define SRR1_PROGPRIV 0x00040000
733#define SRR1_PROGTRAP 0x00020000
734#define SRR1_PROGADDR 0x00010000
735
736#define SPRN_HSRR0 0x13A
737#define SPRN_HSRR1 0x13B
738#define HSRR1_DENORM 0x00100000
739
740#define SPRN_TBCTL 0x35f
741#define TBCTL_FREEZE 0x0000000000000000ull
742#define TBCTL_RESTART 0x0000000100000000ull
743#define TBCTL_UPDATE_UPPER 0x0000000200000000ull
744#define TBCTL_UPDATE_LOWER 0x0000000300000000ull
745
746#ifndef SPRN_SVR
747#define SPRN_SVR 0x11E
748#endif
749#define SPRN_THRM1 0x3FC
750
751#define THRM1_TIN (1 << 31)
752#define THRM1_TIV (1 << 30)
753#define THRM1_THRES(x) ((x&0x7f)<<23)
754#define THRM3_SITV(x) ((x&0x3fff)<<1)
755#define THRM1_TID (1<<2)
756#define THRM1_TIE (1<<1)
757#define THRM1_V (1<<0)
758#define SPRN_THRM2 0x3FD
759#define SPRN_THRM3 0x3FE
760#define THRM3_E (1<<0)
761#define SPRN_TLBMISS 0x3D4
762#define SPRN_UMMCR0 0x3A8
763#define SPRN_UMMCR1 0x3AC
764#define SPRN_UPMC1 0x3A9
765#define SPRN_UPMC2 0x3AA
766#define SPRN_UPMC3 0x3AD
767#define SPRN_UPMC4 0x3AE
768#define SPRN_USIA 0x3AB
769#define SPRN_VRSAVE 0x100
770#define SPRN_XER 0x001
771
772#define SPRN_MMCR0_GEKKO 0x3B8
773#define SPRN_MMCR1_GEKKO 0x3BC
774#define SPRN_PMC1_GEKKO 0x3B9
775#define SPRN_PMC2_GEKKO 0x3BA
776#define SPRN_PMC3_GEKKO 0x3BD
777#define SPRN_PMC4_GEKKO 0x3BE
778#define SPRN_WPAR_GEKKO 0x399
779
780#define SPRN_SCOMC 0x114
781#define SPRN_SCOMD 0x115
782
783
784#ifdef CONFIG_PPC64
785#define SPRN_MMCR0 795
786#define MMCR0_FC 0x80000000UL
787#define MMCR0_FCS 0x40000000UL
788#define MMCR0_KERNEL_DISABLE MMCR0_FCS
789#define MMCR0_FCP 0x20000000UL
790#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
791#define MMCR0_FCM1 0x10000000UL
792#define MMCR0_FCM0 0x08000000UL
793#define MMCR0_PMXE ASM_CONST(0x04000000)
794#define MMCR0_FCECE ASM_CONST(0x02000000)
795#define MMCR0_TBEE 0x00400000UL
796#define MMCR0_BHRBA 0x00200000UL
797#define MMCR0_EBE 0x00100000UL
798#define MMCR0_PMCC 0x000c0000UL
799#define MMCR0_PMCC_U6 0x00080000UL
800#define MMCR0_PMC1CE 0x00008000UL
801#define MMCR0_PMCjCE ASM_CONST(0x00004000)
802#define MMCR0_TRIGGER 0x00002000UL
803#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800)
804#define MMCR0_C56RUN ASM_CONST(0x00000100)
805
806#define MMCR0_PMAO ASM_CONST(0x00000080)
807#define MMCR0_SHRFC 0x00000040UL
808#define MMCR0_FC56 0x00000010UL
809#define MMCR0_FCTI 0x00000008UL
810#define MMCR0_FCTA 0x00000004UL
811#define MMCR0_FCWAIT 0x00000002UL
812#define MMCR0_FCHV 0x00000001UL
813#define SPRN_MMCR1 798
814#define SPRN_MMCR2 785
815#define SPRN_UMMCR2 769
816#define SPRN_MMCRA 0x312
817#define MMCRA_SDSYNC 0x80000000UL
818#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL
819#define MMCRA_SDAR_ERAT_MISS 0x20000000UL
820#define MMCRA_SIHV 0x10000000UL
821#define MMCRA_SIPR 0x08000000UL
822#define MMCRA_SLOT 0x07000000UL
823#define MMCRA_SLOT_SHIFT 24
824#define MMCRA_SAMPLE_ENABLE 0x00000001UL
825#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL
826#define POWER6_MMCRA_SIHV 0x0000040000000000ULL
827#define POWER6_MMCRA_SIPR 0x0000020000000000ULL
828#define POWER6_MMCRA_THRM 0x00000020UL
829#define POWER6_MMCRA_OTHER 0x0000000EUL
830
831#define POWER7P_MMCRA_SIAR_VALID 0x10000000
832#define POWER7P_MMCRA_SDAR_VALID 0x08000000
833
834#define SPRN_MMCRH 316
835#define SPRN_MMCRS 894
836#define SPRN_MMCRC 851
837#define SPRN_EBBHR 804
838#define SPRN_EBBRR 805
839#define SPRN_BESCR 806
840#define BESCR_GE 0x8000000000000000ULL
841#define SPRN_WORT 895
842#define SPRN_WORC 863
843
844#define SPRN_PMC1 787
845#define SPRN_PMC2 788
846#define SPRN_PMC3 789
847#define SPRN_PMC4 790
848#define SPRN_PMC5 791
849#define SPRN_PMC6 792
850#define SPRN_PMC7 793
851#define SPRN_PMC8 794
852#define SPRN_SIER 784
853#define SIER_SIPR 0x2000000
854#define SIER_SIHV 0x1000000
855#define SIER_SIAR_VALID 0x0400000
856#define SIER_SDAR_VALID 0x0200000
857#define SPRN_SIAR 796
858#define SPRN_SDAR 797
859#define SPRN_TACR 888
860#define SPRN_TCSCR 889
861#define SPRN_CSIGR 890
862#define SPRN_SPMC1 892
863#define SPRN_SPMC2 893
864
865
866#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
867#define MMCR2_USER_MASK 0x4020100804020000UL
868#define SIER_USER_MASK 0x7fffffUL
869
870#define SPRN_PA6T_MMCR0 795
871#define PA6T_MMCR0_EN0 0x0000000000000001UL
872#define PA6T_MMCR0_EN1 0x0000000000000002UL
873#define PA6T_MMCR0_EN2 0x0000000000000004UL
874#define PA6T_MMCR0_EN3 0x0000000000000008UL
875#define PA6T_MMCR0_EN4 0x0000000000000010UL
876#define PA6T_MMCR0_EN5 0x0000000000000020UL
877#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
878#define PA6T_MMCR0_PREN 0x0000000000000080UL
879#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
880#define PA6T_MMCR0_FCM0 0x0000000000000200UL
881#define PA6T_MMCR0_FCM1 0x0000000000000400UL
882#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
883#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
884#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
885#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
886#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
887#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
888#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
889#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
890#define PA6T_MMCR0_UOP 0x0000000000080000UL
891#define PA6T_MMCR0_TRG 0x0000000000100000UL
892#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
893#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
894#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
895#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
896#define PA6T_MMCR0_PROEN 0x0000000008000000UL
897#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
898#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
899#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
900#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
901#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
902#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
903#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
904#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
905#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
906#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
907#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
908#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
909#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
910
911#define SPRN_PA6T_MMCR1 798
912#define PA6T_MMCR1_ES2 0x00000000000000ffUL
913#define PA6T_MMCR1_ES3 0x000000000000ff00UL
914#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
915#define PA6T_MMCR1_ES5 0x00000000ff000000UL
916
917#define SPRN_PA6T_UPMC0 771
918#define SPRN_PA6T_UPMC1 772
919#define SPRN_PA6T_UPMC2 773
920#define SPRN_PA6T_UPMC3 774
921#define SPRN_PA6T_UPMC4 775
922#define SPRN_PA6T_UPMC5 776
923#define SPRN_PA6T_UMMCR0 779
924#define SPRN_PA6T_SIAR 780
925#define SPRN_PA6T_UMMCR1 782
926#define SPRN_PA6T_SIER 785
927#define SPRN_PA6T_PMC0 787
928#define SPRN_PA6T_PMC1 788
929#define SPRN_PA6T_PMC2 789
930#define SPRN_PA6T_PMC3 790
931#define SPRN_PA6T_PMC4 791
932#define SPRN_PA6T_PMC5 792
933#define SPRN_PA6T_TSR0 793
934#define SPRN_PA6T_TSR1 794
935#define SPRN_PA6T_TSR2 799
936#define SPRN_PA6T_TSR3 784
937
938#define SPRN_PA6T_IER 981
939#define SPRN_PA6T_DER 982
940#define SPRN_PA6T_BER 862
941#define SPRN_PA6T_MER 849
942
943#define SPRN_PA6T_IMA0 880
944#define SPRN_PA6T_IMA1 881
945#define SPRN_PA6T_IMA2 882
946#define SPRN_PA6T_IMA3 883
947#define SPRN_PA6T_IMA4 884
948#define SPRN_PA6T_IMA5 885
949#define SPRN_PA6T_IMA6 886
950#define SPRN_PA6T_IMA7 887
951#define SPRN_PA6T_IMA8 888
952#define SPRN_PA6T_IMA9 889
953#define SPRN_PA6T_BTCR 978
954#define SPRN_PA6T_IMAAT 979
955#define SPRN_PA6T_PCCR 1019
956#define SPRN_BKMK 1020
957#define SPRN_PA6T_RPCCR 1021
958
959
960#else
961#define SPRN_MMCR0 952
962#define MMCR0_FC 0x80000000UL
963#define MMCR0_FCS 0x40000000UL
964#define MMCR0_FCP 0x20000000UL
965#define MMCR0_FCM1 0x10000000UL
966#define MMCR0_FCM0 0x08000000UL
967#define MMCR0_PMXE 0x04000000UL
968#define MMCR0_FCECE 0x02000000UL
969#define MMCR0_TBEE 0x00400000UL
970#define MMCR0_PMC1CE 0x00008000UL
971#define MMCR0_PMCnCE 0x00004000UL
972#define MMCR0_TRIGGER 0x00002000UL
973#define MMCR0_PMC1SEL 0x00001fc0UL
974#define MMCR0_PMC2SEL 0x0000003fUL
975
976#define SPRN_MMCR1 956
977#define MMCR1_PMC3SEL 0xf8000000UL
978#define MMCR1_PMC4SEL 0x07c00000UL
979#define MMCR1_PMC5SEL 0x003e0000UL
980#define MMCR1_PMC6SEL 0x0001f800UL
981#define SPRN_MMCR2 944
982#define SPRN_PMC1 953
983#define SPRN_PMC2 954
984#define SPRN_PMC3 957
985#define SPRN_PMC4 958
986#define SPRN_PMC5 945
987#define SPRN_PMC6 946
988
989#define SPRN_SIAR 955
990
991
992#define MMCR0_PMC1_CYCLES (1 << 7)
993#define MMCR0_PMC1_ICACHEMISS (5 << 7)
994#define MMCR0_PMC1_DTLB (6 << 7)
995#define MMCR0_PMC2_DCACHEMISS 0x6
996#define MMCR0_PMC2_CYCLES 0x1
997#define MMCR0_PMC2_ITLB 0x7
998#define MMCR0_PMC2_LOADMISSTIME 0x5
999#endif
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1064
1065#ifdef CONFIG_PPC64
1066#define SPRN_SPRG_PACA SPRN_SPRG1
1067#else
1068#define SPRN_SPRG_THREAD SPRN_SPRG3
1069#endif
1070
1071#ifdef CONFIG_PPC_BOOK3S_64
1072#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2
1073#define SPRN_SPRG_HPACA SPRN_HSPRG0
1074#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1
1075#define SPRN_SPRG_VDSO_READ SPRN_USPRG3
1076#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3
1077
1078#define GET_PACA(rX) \
1079 BEGIN_FTR_SECTION_NESTED(66); \
1080 mfspr rX,SPRN_SPRG_PACA; \
1081 FTR_SECTION_ELSE_NESTED(66); \
1082 mfspr rX,SPRN_SPRG_HPACA; \
1083 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1084
1085#define SET_PACA(rX) \
1086 BEGIN_FTR_SECTION_NESTED(66); \
1087 mtspr SPRN_SPRG_PACA,rX; \
1088 FTR_SECTION_ELSE_NESTED(66); \
1089 mtspr SPRN_SPRG_HPACA,rX; \
1090 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1091
1092#define GET_SCRATCH0(rX) \
1093 BEGIN_FTR_SECTION_NESTED(66); \
1094 mfspr rX,SPRN_SPRG_SCRATCH0; \
1095 FTR_SECTION_ELSE_NESTED(66); \
1096 mfspr rX,SPRN_SPRG_HSCRATCH0; \
1097 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1098
1099#define SET_SCRATCH0(rX) \
1100 BEGIN_FTR_SECTION_NESTED(66); \
1101 mtspr SPRN_SPRG_SCRATCH0,rX; \
1102 FTR_SECTION_ELSE_NESTED(66); \
1103 mtspr SPRN_SPRG_HSCRATCH0,rX; \
1104 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1105
1106#else
1107#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0
1108#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX
1109
1110#endif
1111
1112#ifdef CONFIG_PPC_BOOK3E_64
1113#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8
1114#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3
1115#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9
1116#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2
1117#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6
1118#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0
1119#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1120#define SPRN_SPRG_VDSO_READ SPRN_USPRG7
1121#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7
1122
1123#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX
1124#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA
1125
1126#endif
1127
1128#ifdef CONFIG_PPC_BOOK3S_32
1129#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1130#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1131#define SPRN_SPRG_RTAS SPRN_SPRG2
1132#define SPRN_SPRG_603_LRU SPRN_SPRG4
1133#endif
1134
1135#ifdef CONFIG_40x
1136#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1137#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1138#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1139#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1140#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1141#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1142#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
1143#endif
1144
1145#ifdef CONFIG_BOOKE
1146#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
1147#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0
1148#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1
1149#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1
1150#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1151#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1152#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R
1153#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W
1154#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R
1155#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W
1156#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1
1157#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1
1158#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R
1159#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W
1160#ifdef CONFIG_E200
1161#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R
1162#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W
1163#else
1164#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9
1165#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9
1166#endif
1167#endif
1168
1169#ifdef CONFIG_PPC_8xx
1170#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1171#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1172#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1173#endif
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183#ifdef CONFIG_PPC64
1184#define MTFSF_L(REG) \
1185 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1186#else
1187#define MTFSF_L(REG) mtfsf 0xff, (REG)
1188#endif
1189
1190
1191
1192#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF)
1193#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF)
1194
1195#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1196
1197
1198
1199
1200
1201
1202#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF)
1203#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF)
1204#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF)
1205#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF)
1206#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF)
1207#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF)
1208
1209
1210
1211#define PVR_403GA 0x00200000
1212#define PVR_403GB 0x00200100
1213#define PVR_403GC 0x00200200
1214#define PVR_403GCX 0x00201400
1215#define PVR_405GP 0x40110000
1216#define PVR_476 0x11a52000
1217#define PVR_476FPE 0x7ff50000
1218#define PVR_STB03XXX 0x40310000
1219#define PVR_NP405H 0x41410000
1220#define PVR_NP405L 0x41610000
1221#define PVR_601 0x00010000
1222#define PVR_602 0x00050000
1223#define PVR_603 0x00030000
1224#define PVR_603e 0x00060000
1225#define PVR_603ev 0x00070000
1226#define PVR_603r 0x00071000
1227#define PVR_604 0x00040000
1228#define PVR_604e 0x00090000
1229#define PVR_604r 0x000A0000
1230#define PVR_620 0x00140000
1231#define PVR_740 0x00080000
1232#define PVR_750 PVR_740
1233#define PVR_740P 0x10080000
1234#define PVR_750P PVR_740P
1235#define PVR_7400 0x000C0000
1236#define PVR_7410 0x800C0000
1237#define PVR_7450 0x80000000
1238#define PVR_8540 0x80200000
1239#define PVR_8560 0x80200000
1240#define PVR_VER_E500V1 0x8020
1241#define PVR_VER_E500V2 0x8021
1242#define PVR_VER_E500MC 0x8023
1243#define PVR_VER_E5500 0x8024
1244#define PVR_VER_E6500 0x8040
1245
1246
1247
1248
1249
1250
1251
1252#define PVR_8xx 0x00500000
1253
1254#define PVR_8240 0x00810100
1255#define PVR_8245 0x80811014
1256#define PVR_8260 PVR_8240
1257
1258
1259#define PVR_476_ISS 0x00052000
1260
1261
1262#define PVR_NORTHSTAR 0x0033
1263#define PVR_PULSAR 0x0034
1264#define PVR_POWER4 0x0035
1265#define PVR_ICESTAR 0x0036
1266#define PVR_SSTAR 0x0037
1267#define PVR_POWER4p 0x0038
1268#define PVR_970 0x0039
1269#define PVR_POWER5 0x003A
1270#define PVR_POWER5p 0x003B
1271#define PVR_970FX 0x003C
1272#define PVR_POWER6 0x003E
1273#define PVR_POWER7 0x003F
1274#define PVR_630 0x0040
1275#define PVR_630p 0x0041
1276#define PVR_970MP 0x0044
1277#define PVR_970GX 0x0045
1278#define PVR_POWER7p 0x004A
1279#define PVR_POWER8E 0x004B
1280#define PVR_POWER8NVL 0x004C
1281#define PVR_POWER8 0x004D
1282#define PVR_POWER9 0x004E
1283#define PVR_BE 0x0070
1284#define PVR_PA6T 0x0090
1285
1286
1287#define PVR_ARCH_204 0x0f000001
1288#define PVR_ARCH_205 0x0f000002
1289#define PVR_ARCH_206 0x0f000003
1290#define PVR_ARCH_206p 0x0f100003
1291#define PVR_ARCH_207 0x0f000004
1292#define PVR_ARCH_300 0x0f000005
1293
1294
1295#ifndef __ASSEMBLY__
1296#define mfmsr() ({unsigned long rval; \
1297 asm volatile("mfmsr %0" : "=r" (rval) : \
1298 : "memory"); rval;})
1299#ifdef CONFIG_PPC_BOOK3S_64
1300#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
1301 : : "r" (v) : "memory")
1302#define mtmsr(v) __mtmsrd((v), 0)
1303#define __MTMSR "mtmsrd"
1304#else
1305#define mtmsr(v) asm volatile("mtmsr %0" : \
1306 : "r" ((unsigned long)(v)) \
1307 : "memory")
1308#define __MTMSR "mtmsr"
1309#endif
1310
1311static inline void mtmsr_isync(unsigned long val)
1312{
1313 asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1314 "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1315}
1316
1317#define mfspr(rn) ({unsigned long rval; \
1318 asm volatile("mfspr %0," __stringify(rn) \
1319 : "=r" (rval)); rval;})
1320#ifndef mtspr
1321#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
1322 : "r" ((unsigned long)(v)) \
1323 : "memory")
1324#endif
1325#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \
1326 : : "memory")
1327
1328extern unsigned long msr_check_and_set(unsigned long bits);
1329extern bool strict_msr_control;
1330extern void __msr_check_and_clear(unsigned long bits);
1331static inline void msr_check_and_clear(unsigned long bits)
1332{
1333 if (strict_msr_control)
1334 __msr_check_and_clear(bits);
1335}
1336
1337#ifdef __powerpc64__
1338#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1339#define mftb() ({unsigned long rval; \
1340 asm volatile( \
1341 "90: mfspr %0, %2;\n" \
1342 "97: cmpwi %0,0;\n" \
1343 " beq- 90b;\n" \
1344 "99:\n" \
1345 ".section __ftr_fixup,\"a\"\n" \
1346 ".align 3\n" \
1347 "98:\n" \
1348 " .8byte %1\n" \
1349 " .8byte %1\n" \
1350 " .8byte 97b-98b\n" \
1351 " .8byte 99b-98b\n" \
1352 " .8byte 0\n" \
1353 " .8byte 0\n" \
1354 ".previous" \
1355 : "=r" (rval) \
1356 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1357 rval;})
1358#else
1359#define mftb() ({unsigned long rval; \
1360 asm volatile("mfspr %0, %1" : \
1361 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1362#endif
1363
1364#else
1365
1366#if defined(CONFIG_PPC_8xx)
1367#define mftbl() ({unsigned long rval; \
1368 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1369#define mftbu() ({unsigned long rval; \
1370 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1371#else
1372#define mftbl() ({unsigned long rval; \
1373 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1374 "i" (SPRN_TBRL)); rval;})
1375#define mftbu() ({unsigned long rval; \
1376 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1377 "i" (SPRN_TBRU)); rval;})
1378#endif
1379#define mftb() mftbl()
1380#endif
1381
1382#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
1383#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
1384
1385#ifdef CONFIG_PPC32
1386#define mfsrin(v) ({unsigned int rval; \
1387 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1388 rval;})
1389#endif
1390
1391#define proc_trap() asm volatile("trap")
1392
1393extern unsigned long current_stack_pointer(void);
1394
1395extern unsigned long scom970_read(unsigned int address);
1396extern void scom970_write(unsigned int address, unsigned long value);
1397
1398struct pt_regs;
1399
1400extern void ppc_save_regs(struct pt_regs *regs);
1401
1402static inline void update_power8_hid0(unsigned long hid0)
1403{
1404
1405
1406
1407
1408
1409 asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1410}
1411#endif
1412#endif
1413#endif
1414