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11#include <linux/kernel_stat.h>
12#include <linux/interrupt.h>
13#include <linux/seq_file.h>
14#include <linux/proc_fs.h>
15#include <linux/profile.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/ftrace.h>
19#include <linux/errno.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/cpu.h>
23#include <linux/irq.h>
24#include <asm/irq_regs.h>
25#include <asm/cputime.h>
26#include <asm/lowcore.h>
27#include <asm/irq.h>
28#include <asm/hw_irq.h>
29#include "entry.h"
30
31DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
32EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
33
34struct irq_class {
35 int irq;
36 char *name;
37 char *desc;
38};
39
40
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43
44
45
46
47
48
49
50static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
51 {.irq = EXT_INTERRUPT, .name = "EXT"},
52 {.irq = IO_INTERRUPT, .name = "I/O"},
53 {.irq = THIN_INTERRUPT, .name = "AIO"},
54};
55
56
57
58
59
60
61static const struct irq_class irqclass_sub_desc[] = {
62 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
63 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
64 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
65 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
66 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
67 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
68 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
69 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
70 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
71 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
72 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
73 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
74 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
75 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
76 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
77 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
78 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
79 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
80 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
81 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
82 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
83 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
84 {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"},
85 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
86 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
87 {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" },
88 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" },
89 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
90 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
91 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
92 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
93};
94
95void __init init_IRQ(void)
96{
97 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
98 init_cio_interrupts();
99 init_airq_interrupts();
100 init_ext_interrupts();
101}
102
103void do_IRQ(struct pt_regs *regs, int irq)
104{
105 struct pt_regs *old_regs;
106
107 old_regs = set_irq_regs(regs);
108 irq_enter();
109 if (tod_after_eq(S390_lowcore.int_clock,
110 S390_lowcore.clock_comparator))
111
112 clock_comparator_work();
113 generic_handle_irq(irq);
114 irq_exit();
115 set_irq_regs(old_regs);
116}
117
118
119
120
121int show_interrupts(struct seq_file *p, void *v)
122{
123 int index = *(loff_t *) v;
124 int cpu, irq;
125
126 get_online_cpus();
127 if (index == 0) {
128 seq_puts(p, " ");
129 for_each_online_cpu(cpu)
130 seq_printf(p, "CPU%d ", cpu);
131 seq_putc(p, '\n');
132 }
133 if (index < NR_IRQS_BASE) {
134 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
135 irq = irqclass_main_desc[index].irq;
136 for_each_online_cpu(cpu)
137 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
138 seq_putc(p, '\n');
139 goto out;
140 }
141 if (index > NR_IRQS_BASE)
142 goto out;
143
144 for (index = 0; index < NR_ARCH_IRQS; index++) {
145 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
146 irq = irqclass_sub_desc[index].irq;
147 for_each_online_cpu(cpu)
148 seq_printf(p, "%10u ",
149 per_cpu(irq_stat, cpu).irqs[irq]);
150 if (irqclass_sub_desc[index].desc)
151 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
152 seq_putc(p, '\n');
153 }
154out:
155 put_online_cpus();
156 return 0;
157}
158
159unsigned int arch_dynirq_lower_bound(unsigned int from)
160{
161 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
162}
163
164
165
166
167void do_softirq_own_stack(void)
168{
169 unsigned long old, new;
170
171 old = current_stack_pointer();
172
173 new = S390_lowcore.async_stack;
174 if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
175
176 new -= STACK_FRAME_OVERHEAD;
177 ((struct stack_frame *) new)->back_chain = old;
178 asm volatile(" la 15,0(%0)\n"
179 " basr 14,%2\n"
180 " la 15,0(%1)\n"
181 : : "a" (new), "a" (old),
182 "a" (__do_softirq)
183 : "0", "1", "2", "3", "4", "5", "14",
184 "cc", "memory" );
185 } else {
186
187 __do_softirq();
188 }
189}
190
191
192
193
194
195static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
196
197struct ext_int_info {
198 ext_int_handler_t handler;
199 struct hlist_node entry;
200 struct rcu_head rcu;
201 u16 code;
202};
203
204
205static DEFINE_SPINLOCK(ext_int_hash_lock);
206
207static inline int ext_hash(u16 code)
208{
209 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
210
211 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
212}
213
214int register_external_irq(u16 code, ext_int_handler_t handler)
215{
216 struct ext_int_info *p;
217 unsigned long flags;
218 int index;
219
220 p = kmalloc(sizeof(*p), GFP_ATOMIC);
221 if (!p)
222 return -ENOMEM;
223 p->code = code;
224 p->handler = handler;
225 index = ext_hash(code);
226
227 spin_lock_irqsave(&ext_int_hash_lock, flags);
228 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
229 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
230 return 0;
231}
232EXPORT_SYMBOL(register_external_irq);
233
234int unregister_external_irq(u16 code, ext_int_handler_t handler)
235{
236 struct ext_int_info *p;
237 unsigned long flags;
238 int index = ext_hash(code);
239
240 spin_lock_irqsave(&ext_int_hash_lock, flags);
241 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
242 if (p->code == code && p->handler == handler) {
243 hlist_del_rcu(&p->entry);
244 kfree_rcu(p, rcu);
245 }
246 }
247 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
248 return 0;
249}
250EXPORT_SYMBOL(unregister_external_irq);
251
252static irqreturn_t do_ext_interrupt(int irq, void *dummy)
253{
254 struct pt_regs *regs = get_irq_regs();
255 struct ext_code ext_code;
256 struct ext_int_info *p;
257 int index;
258
259 ext_code = *(struct ext_code *) ®s->int_code;
260 if (ext_code.code != EXT_IRQ_CLK_COMP)
261 set_cpu_flag(CIF_NOHZ_DELAY);
262
263 index = ext_hash(ext_code.code);
264 rcu_read_lock();
265 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
266 if (unlikely(p->code != ext_code.code))
267 continue;
268 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
269 }
270 rcu_read_unlock();
271 return IRQ_HANDLED;
272}
273
274static struct irqaction external_interrupt = {
275 .name = "EXT",
276 .handler = do_ext_interrupt,
277};
278
279void __init init_ext_interrupts(void)
280{
281 int idx;
282
283 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
284 INIT_HLIST_HEAD(&ext_int_hash[idx]);
285
286 irq_set_chip_and_handler(EXT_INTERRUPT,
287 &dummy_irq_chip, handle_percpu_irq);
288 setup_irq(EXT_INTERRUPT, &external_interrupt);
289}
290
291static DEFINE_SPINLOCK(irq_subclass_lock);
292static unsigned char irq_subclass_refcount[64];
293
294void irq_subclass_register(enum irq_subclass subclass)
295{
296 spin_lock(&irq_subclass_lock);
297 if (!irq_subclass_refcount[subclass])
298 ctl_set_bit(0, subclass);
299 irq_subclass_refcount[subclass]++;
300 spin_unlock(&irq_subclass_lock);
301}
302EXPORT_SYMBOL(irq_subclass_register);
303
304void irq_subclass_unregister(enum irq_subclass subclass)
305{
306 spin_lock(&irq_subclass_lock);
307 irq_subclass_refcount[subclass]--;
308 if (!irq_subclass_refcount[subclass])
309 ctl_clear_bit(0, subclass);
310 spin_unlock(&irq_subclass_lock);
311}
312EXPORT_SYMBOL(irq_subclass_unregister);
313
