1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5/* 6 * CPU model specific register (MSR) numbers. 7 * 8 * Do not add new entries to this file unless the definitions are shared 9 * between multiple compilation units. 10 */ 11 12/* x86-64 specific MSRs */ 13#define MSR_EFER 0xc0000080 /* extended feature register */ 14#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 15#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 16#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 17#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 18#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 19#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 20#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 21#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 22 23/* EFER bits: */ 24#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 25#define _EFER_LME 8 /* Long mode enable */ 26#define _EFER_LMA 10 /* Long mode active (read-only) */ 27#define _EFER_NX 11 /* No execute enable */ 28#define _EFER_SVME 12 /* Enable virtualization */ 29#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 30#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 31 32#define EFER_SCE (1<<_EFER_SCE) 33#define EFER_LME (1<<_EFER_LME) 34#define EFER_LMA (1<<_EFER_LMA) 35#define EFER_NX (1<<_EFER_NX) 36#define EFER_SVME (1<<_EFER_SVME) 37#define EFER_LMSLE (1<<_EFER_LMSLE) 38#define EFER_FFXSR (1<<_EFER_FFXSR) 39 40/* Intel MSRs. Some also available on other CPUs */ 41 42#define MSR_PPIN_CTL 0x0000004e 43#define MSR_PPIN 0x0000004f 44 45#define MSR_IA32_PERFCTR0 0x000000c1 46#define MSR_IA32_PERFCTR1 0x000000c2 47#define MSR_FSB_FREQ 0x000000cd 48#define MSR_PLATFORM_INFO 0x000000ce 49#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 50#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 51 52#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 53#define NHM_C3_AUTO_DEMOTE (1UL << 25) 54#define NHM_C1_AUTO_DEMOTE (1UL << 26) 55#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 56#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 57#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 58 59#define MSR_MTRRcap 0x000000fe 60#define MSR_IA32_BBL_CR_CTL 0x00000119 61#define MSR_IA32_BBL_CR_CTL3 0x0000011e 62 63#define MSR_IA32_SYSENTER_CS 0x00000174 64#define MSR_IA32_SYSENTER_ESP 0x00000175 65#define MSR_IA32_SYSENTER_EIP 0x00000176 66 67#define MSR_IA32_MCG_CAP 0x00000179 68#define MSR_IA32_MCG_STATUS 0x0000017a 69#define MSR_IA32_MCG_CTL 0x0000017b 70#define MSR_IA32_MCG_EXT_CTL 0x000004d0 71 72#define MSR_OFFCORE_RSP_0 0x000001a6 73#define MSR_OFFCORE_RSP_1 0x000001a7 74#define MSR_TURBO_RATIO_LIMIT 0x000001ad 75#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 76#define MSR_TURBO_RATIO_LIMIT2 0x000001af 77 78#define MSR_LBR_SELECT 0x000001c8 79#define MSR_LBR_TOS 0x000001c9 80#define MSR_LBR_NHM_FROM 0x00000680 81#define MSR_LBR_NHM_TO 0x000006c0 82#define MSR_LBR_CORE_FROM 0x00000040 83#define MSR_LBR_CORE_TO 0x00000060 84 85#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 86#define LBR_INFO_MISPRED BIT_ULL(63) 87#define LBR_INFO_IN_TX BIT_ULL(62) 88#define LBR_INFO_ABORT BIT_ULL(61) 89#define LBR_INFO_CYCLES 0xffff 90 91#define MSR_IA32_PEBS_ENABLE 0x000003f1 92#define MSR_IA32_DS_AREA 0x00000600 93#define MSR_IA32_PERF_CAPABILITIES 0x00000345 94#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 95 96#define MSR_IA32_RTIT_CTL 0x00000570 97#define MSR_IA32_RTIT_STATUS 0x00000571 98#define MSR_IA32_RTIT_ADDR0_A 0x00000580 99#define MSR_IA32_RTIT_ADDR0_B 0x00000581 100#define MSR_IA32_RTIT_ADDR1_A 0x00000582 101#define MSR_IA32_RTIT_ADDR1_B 0x00000583 102#define MSR_IA32_RTIT_ADDR2_A 0x00000584 103#define MSR_IA32_RTIT_ADDR2_B 0x00000585 104#define MSR_IA32_RTIT_ADDR3_A 0x00000586 105#define MSR_IA32_RTIT_ADDR3_B 0x00000587 106#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 107#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 108#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 109 110#define MSR_MTRRfix64K_00000 0x00000250 111#define MSR_MTRRfix16K_80000 0x00000258 112#define MSR_MTRRfix16K_A0000 0x00000259 113#define MSR_MTRRfix4K_C0000 0x00000268 114#define MSR_MTRRfix4K_C8000 0x00000269 115#define MSR_MTRRfix4K_D0000 0x0000026a 116#define MSR_MTRRfix4K_D8000 0x0000026b 117#define MSR_MTRRfix4K_E0000 0x0000026c 118#define MSR_MTRRfix4K_E8000 0x0000026d 119#define MSR_MTRRfix4K_F0000 0x0000026e 120#define MSR_MTRRfix4K_F8000 0x0000026f 121#define MSR_MTRRdefType 0x000002ff 122 123#define MSR_IA32_CR_PAT 0x00000277 124 125#define MSR_IA32_DEBUGCTLMSR 0x000001d9 126#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 127#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 128#define MSR_IA32_LASTINTFROMIP 0x000001dd 129#define MSR_IA32_LASTINTTOIP 0x000001de 130 131/* DEBUGCTLMSR bits (others vary by model): */ 132#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 133#define DEBUGCTLMSR_BTF_SHIFT 1 134#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 135#define DEBUGCTLMSR_TR (1UL << 6) 136#define DEBUGCTLMSR_BTS (1UL << 7) 137#define DEBUGCTLMSR_BTINT (1UL << 8) 138#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 139#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 140#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 141#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 142#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 143 144#define MSR_PEBS_FRONTEND 0x000003f7 145 146#define MSR_IA32_POWER_CTL 0x000001fc 147 148#define MSR_IA32_MC0_CTL 0x00000400 149#define MSR_IA32_MC0_STATUS 0x00000401 150#define MSR_IA32_MC0_ADDR 0x00000402 151#define MSR_IA32_MC0_MISC 0x00000403 152 153/* C-state Residency Counters */ 154#define MSR_PKG_C3_RESIDENCY 0x000003f8 155#define MSR_PKG_C6_RESIDENCY 0x000003f9 156#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 157#define MSR_PKG_C7_RESIDENCY 0x000003fa 158#define MSR_CORE_C3_RESIDENCY 0x000003fc 159#define MSR_CORE_C6_RESIDENCY 0x000003fd 160#define MSR_CORE_C7_RESIDENCY 0x000003fe 161#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 162#define MSR_PKG_C2_RESIDENCY 0x0000060d 163#define MSR_PKG_C8_RESIDENCY 0x00000630 164#define MSR_PKG_C9_RESIDENCY 0x00000631 165#define MSR_PKG_C10_RESIDENCY 0x00000632 166 167/* Interrupt Response Limit */ 168#define MSR_PKGC3_IRTL 0x0000060a 169#define MSR_PKGC6_IRTL 0x0000060b 170#define MSR_PKGC7_IRTL 0x0000060c 171#define MSR_PKGC8_IRTL 0x00000633 172#define MSR_PKGC9_IRTL 0x00000634 173#define MSR_PKGC10_IRTL 0x00000635 174 175/* Run Time Average Power Limiting (RAPL) Interface */ 176 177#define MSR_RAPL_POWER_UNIT 0x00000606 178 179#define MSR_PKG_POWER_LIMIT 0x00000610 180#define MSR_PKG_ENERGY_STATUS 0x00000611 181#define MSR_PKG_PERF_STATUS 0x00000613 182#define MSR_PKG_POWER_INFO 0x00000614 183 184#define MSR_DRAM_POWER_LIMIT 0x00000618 185#define MSR_DRAM_ENERGY_STATUS 0x00000619 186#define MSR_DRAM_PERF_STATUS 0x0000061b 187#define MSR_DRAM_POWER_INFO 0x0000061c 188 189#define MSR_PP0_POWER_LIMIT 0x00000638 190#define MSR_PP0_ENERGY_STATUS 0x00000639 191#define MSR_PP0_POLICY 0x0000063a 192#define MSR_PP0_PERF_STATUS 0x0000063b 193 194#define MSR_PP1_POWER_LIMIT 0x00000640 195#define MSR_PP1_ENERGY_STATUS 0x00000641 196#define MSR_PP1_POLICY 0x00000642 197 198/* Config TDP MSRs */ 199#define MSR_CONFIG_TDP_NOMINAL 0x00000648 200#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 201#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 202#define MSR_CONFIG_TDP_CONTROL 0x0000064B 203#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 204 205#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 206 207#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 208#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 209#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 210#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 211 212#define MSR_CORE_C1_RES 0x00000660 213#define MSR_MODULE_C6_RES_MS 0x00000664 214 215#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 216#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 217 218#define MSR_ATOM_CORE_RATIOS 0x0000066a 219#define MSR_ATOM_CORE_VIDS 0x0000066b 220#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 221#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 222 223 224#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 225#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 226#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 227 228/* Hardware P state interface */ 229#define MSR_PPERF 0x0000064e 230#define MSR_PERF_LIMIT_REASONS 0x0000064f 231#define MSR_PM_ENABLE 0x00000770 232#define MSR_HWP_CAPABILITIES 0x00000771 233#define MSR_HWP_REQUEST_PKG 0x00000772 234#define MSR_HWP_INTERRUPT 0x00000773 235#define MSR_HWP_REQUEST 0x00000774 236#define MSR_HWP_STATUS 0x00000777 237 238/* CPUID.6.EAX */ 239#define HWP_BASE_BIT (1<<7) 240#define HWP_NOTIFICATIONS_BIT (1<<8) 241#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 242#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 243#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 244 245/* IA32_HWP_CAPABILITIES */ 246#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 247#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 248#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 249#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 250 251/* IA32_HWP_REQUEST */ 252#define HWP_MIN_PERF(x) (x & 0xff) 253#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 254#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 255#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 256#define HWP_EPP_PERFORMANCE 0x00 257#define HWP_EPP_BALANCE_PERFORMANCE 0x80 258#define HWP_EPP_BALANCE_POWERSAVE 0xC0 259#define HWP_EPP_POWERSAVE 0xFF 260#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 261#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 262 263/* IA32_HWP_STATUS */ 264#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 265#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 266 267/* IA32_HWP_INTERRUPT */ 268#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 269#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 270 271#define MSR_AMD64_MC0_MASK 0xc0010044 272 273#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 274#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 275#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 276#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 277 278#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 279 280/* These are consecutive and not in the normal 4er MCE bank block */ 281#define MSR_IA32_MC0_CTL2 0x00000280 282#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 283 284#define MSR_P6_PERFCTR0 0x000000c1 285#define MSR_P6_PERFCTR1 0x000000c2 286#define MSR_P6_EVNTSEL0 0x00000186 287#define MSR_P6_EVNTSEL1 0x00000187 288 289#define MSR_KNC_PERFCTR0 0x00000020 290#define MSR_KNC_PERFCTR1 0x00000021 291#define MSR_KNC_EVNTSEL0 0x00000028 292#define MSR_KNC_EVNTSEL1 0x00000029 293 294/* Alternative perfctr range with full access. */ 295#define MSR_IA32_PMC0 0x000004c1 296 297/* AMD64 MSRs. Not complete. See the architecture manual for a more 298 complete list. */ 299 300#define MSR_AMD64_PATCH_LEVEL 0x0000008b 301#define MSR_AMD64_TSC_RATIO 0xc0000104 302#define MSR_AMD64_NB_CFG 0xc001001f 303#define MSR_AMD64_PATCH_LOADER 0xc0010020 304#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 305#define MSR_AMD64_OSVW_STATUS 0xc0010141 306#define MSR_AMD64_LS_CFG 0xc0011020 307#define MSR_AMD64_DC_CFG 0xc0011022 308#define MSR_AMD64_BU_CFG2 0xc001102a 309#define MSR_AMD64_IBSFETCHCTL 0xc0011030 310#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 311#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 312#define MSR_AMD64_IBSFETCH_REG_COUNT 3 313#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 314#define MSR_AMD64_IBSOPCTL 0xc0011033 315#define MSR_AMD64_IBSOPRIP 0xc0011034 316#define MSR_AMD64_IBSOPDATA 0xc0011035 317#define MSR_AMD64_IBSOPDATA2 0xc0011036 318#define MSR_AMD64_IBSOPDATA3 0xc0011037 319#define MSR_AMD64_IBSDCLINAD 0xc0011038 320#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 321#define MSR_AMD64_IBSOP_REG_COUNT 7 322#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 323#define MSR_AMD64_IBSCTL 0xc001103a 324#define MSR_AMD64_IBSBRTARGET 0xc001103b 325#define MSR_AMD64_IBSOPDATA4 0xc001103d 326#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 327 328/* Fam 17h MSRs */ 329#define MSR_F17H_IRPERF 0xc00000e9 330 331/* Fam 16h MSRs */ 332#define MSR_F16H_L2I_PERF_CTL 0xc0010230 333#define MSR_F16H_L2I_PERF_CTR 0xc0010231 334#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 335#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 336#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 337#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 338 339/* Fam 15h MSRs */ 340#define MSR_F15H_PERF_CTL 0xc0010200 341#define MSR_F15H_PERF_CTR 0xc0010201 342#define MSR_F15H_NB_PERF_CTL 0xc0010240 343#define MSR_F15H_NB_PERF_CTR 0xc0010241 344#define MSR_F15H_PTSC 0xc0010280 345#define MSR_F15H_IC_CFG 0xc0011021 346 347/* Fam 10h MSRs */ 348#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 349#define FAM10H_MMIO_CONF_ENABLE (1<<0) 350#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 351#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 352#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 353#define FAM10H_MMIO_CONF_BASE_SHIFT 20 354#define MSR_FAM10H_NODE_ID 0xc001100c 355 356/* K8 MSRs */ 357#define MSR_K8_TOP_MEM1 0xc001001a 358#define MSR_K8_TOP_MEM2 0xc001001d 359#define MSR_K8_SYSCFG 0xc0010010 360#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 361#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 362#define MSR_K8_INT_PENDING_MSG 0xc0010055 363/* C1E active bits in int pending message */ 364#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 365#define MSR_K8_TSEG_ADDR 0xc0010112 366#define MSR_K8_TSEG_MASK 0xc0010113 367#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 368#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 369#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 370 371/* K7 MSRs */ 372#define MSR_K7_EVNTSEL0 0xc0010000 373#define MSR_K7_PERFCTR0 0xc0010004 374#define MSR_K7_EVNTSEL1 0xc0010001 375#define MSR_K7_PERFCTR1 0xc0010005 376#define MSR_K7_EVNTSEL2 0xc0010002 377#define MSR_K7_PERFCTR2 0xc0010006 378#define MSR_K7_EVNTSEL3 0xc0010003 379#define MSR_K7_PERFCTR3 0xc0010007 380#define MSR_K7_CLK_CTL 0xc001001b 381#define MSR_K7_HWCR 0xc0010015 382#define MSR_K7_FID_VID_CTL 0xc0010041 383#define MSR_K7_FID_VID_STATUS 0xc0010042 384 385/* K6 MSRs */ 386#define MSR_K6_WHCR 0xc0000082 387#define MSR_K6_UWCCR 0xc0000085 388#define MSR_K6_EPMR 0xc0000086 389#define MSR_K6_PSOR 0xc0000087 390#define MSR_K6_PFIR 0xc0000088 391 392/* Centaur-Hauls/IDT defined MSRs. */ 393#define MSR_IDT_FCR1 0x00000107 394#define MSR_IDT_FCR2 0x00000108 395#define MSR_IDT_FCR3 0x00000109 396#define MSR_IDT_FCR4 0x0000010a 397 398#define MSR_IDT_MCR0 0x00000110 399#define MSR_IDT_MCR1 0x00000111 400#define MSR_IDT_MCR2 0x00000112 401#define MSR_IDT_MCR3 0x00000113 402#define MSR_IDT_MCR4 0x00000114 403#define MSR_IDT_MCR5 0x00000115 404#define MSR_IDT_MCR6 0x00000116 405#define MSR_IDT_MCR7 0x00000117 406#define MSR_IDT_MCR_CTRL 0x00000120 407 408/* VIA Cyrix defined MSRs*/ 409#define MSR_VIA_FCR 0x00001107 410#define MSR_VIA_LONGHAUL 0x0000110a 411#define MSR_VIA_RNG 0x0000110b 412#define MSR_VIA_BCR2 0x00001147 413 414/* Transmeta defined MSRs */ 415#define MSR_TMTA_LONGRUN_CTRL 0x80868010 416#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 417#define MSR_TMTA_LRTI_READOUT 0x80868018 418#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 419 420/* Intel defined MSRs. */ 421#define MSR_IA32_P5_MC_ADDR 0x00000000 422#define MSR_IA32_P5_MC_TYPE 0x00000001 423#define MSR_IA32_TSC 0x00000010 424#define MSR_IA32_PLATFORM_ID 0x00000017 425#define MSR_IA32_EBL_CR_POWERON 0x0000002a 426#define MSR_EBC_FREQUENCY_ID 0x0000002c 427#define MSR_SMI_COUNT 0x00000034 428#define MSR_IA32_FEATURE_CONTROL 0x0000003a 429#define MSR_IA32_TSC_ADJUST 0x0000003b 430#define MSR_IA32_BNDCFGS 0x00000d90 431 432#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 433 434#define MSR_IA32_XSS 0x00000da0 435 436#define FEATURE_CONTROL_LOCKED (1<<0) 437#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 438#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 439#define FEATURE_CONTROL_LMCE (1<<20) 440 441#define MSR_IA32_APICBASE 0x0000001b 442#define MSR_IA32_APICBASE_BSP (1<<8) 443#define MSR_IA32_APICBASE_ENABLE (1<<11) 444#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 445 446#define MSR_IA32_TSCDEADLINE 0x000006e0 447 448#define MSR_IA32_UCODE_WRITE 0x00000079 449#define MSR_IA32_UCODE_REV 0x0000008b 450 451#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 452#define MSR_IA32_SMBASE 0x0000009e 453 454#define MSR_IA32_PERF_STATUS 0x00000198 455#define MSR_IA32_PERF_CTL 0x00000199 456#define INTEL_PERF_CTL_MASK 0xffff 457#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 458#define MSR_AMD_PERF_STATUS 0xc0010063 459#define MSR_AMD_PERF_CTL 0xc0010062 460 461#define MSR_IA32_MPERF 0x000000e7 462#define MSR_IA32_APERF 0x000000e8 463 464#define MSR_IA32_THERM_CONTROL 0x0000019a 465#define MSR_IA32_THERM_INTERRUPT 0x0000019b 466 467#define THERM_INT_HIGH_ENABLE (1 << 0) 468#define THERM_INT_LOW_ENABLE (1 << 1) 469#define THERM_INT_PLN_ENABLE (1 << 24) 470 471#define MSR_IA32_THERM_STATUS 0x0000019c 472 473#define THERM_STATUS_PROCHOT (1 << 0) 474#define THERM_STATUS_POWER_LIMIT (1 << 10) 475 476#define MSR_THERM2_CTL 0x0000019d 477 478#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 479 480#define MSR_IA32_MISC_ENABLE 0x000001a0 481 482#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 483 484#define MSR_MISC_FEATURE_CONTROL 0x000001a4 485#define MSR_MISC_PWR_MGMT 0x000001aa 486 487#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 488#define ENERGY_PERF_BIAS_PERFORMANCE 0 489#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 490#define ENERGY_PERF_BIAS_NORMAL 6 491#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 492#define ENERGY_PERF_BIAS_POWERSAVE 15 493 494#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 495 496#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 497#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 498 499#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 500 501#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 502#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 503#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 504 505/* Thermal Thresholds Support */ 506#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 507#define THERM_SHIFT_THRESHOLD0 8 508#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 509#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 510#define THERM_SHIFT_THRESHOLD1 16 511#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 512#define THERM_STATUS_THRESHOLD0 (1 << 6) 513#define THERM_LOG_THRESHOLD0 (1 << 7) 514#define THERM_STATUS_THRESHOLD1 (1 << 8) 515#define THERM_LOG_THRESHOLD1 (1 << 9) 516 517/* MISC_ENABLE bits: architectural */ 518#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 519#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 520#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 521#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 522#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 523#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 524#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 525#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 526#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 527#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 528#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 529#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 530#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 531#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 532#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 533#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 534#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 535#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 536#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 537#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 538 539/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 540#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 541#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 542#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 543#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 544#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 545#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 546#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 547#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 548#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 549#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 550#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 551#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 552#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 553#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 554#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 555#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 556#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 557#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 558#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 559#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 560#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 561#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 562#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 563#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 564#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 565#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 566#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 567#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 568#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 569#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 570 571/* MISC_FEATURES_ENABLES non-architectural features */ 572#define MSR_MISC_FEATURES_ENABLES 0x00000140 573 574#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 575#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 576#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 577 578#define MSR_IA32_TSC_DEADLINE 0x000006E0 579 580/* P4/Xeon+ specific */ 581#define MSR_IA32_MCG_EAX 0x00000180 582#define MSR_IA32_MCG_EBX 0x00000181 583#define MSR_IA32_MCG_ECX 0x00000182 584#define MSR_IA32_MCG_EDX 0x00000183 585#define MSR_IA32_MCG_ESI 0x00000184 586#define MSR_IA32_MCG_EDI 0x00000185 587#define MSR_IA32_MCG_EBP 0x00000186 588#define MSR_IA32_MCG_ESP 0x00000187 589#define MSR_IA32_MCG_EFLAGS 0x00000188 590#define MSR_IA32_MCG_EIP 0x00000189 591#define MSR_IA32_MCG_RESERVED 0x0000018a 592 593/* Pentium IV performance counter MSRs */ 594#define MSR_P4_BPU_PERFCTR0 0x00000300 595#define MSR_P4_BPU_PERFCTR1 0x00000301 596#define MSR_P4_BPU_PERFCTR2 0x00000302 597#define MSR_P4_BPU_PERFCTR3 0x00000303 598#define MSR_P4_MS_PERFCTR0 0x00000304 599#define MSR_P4_MS_PERFCTR1 0x00000305 600#define MSR_P4_MS_PERFCTR2 0x00000306 601#define MSR_P4_MS_PERFCTR3 0x00000307 602#define MSR_P4_FLAME_PERFCTR0 0x00000308 603#define MSR_P4_FLAME_PERFCTR1 0x00000309 604#define MSR_P4_FLAME_PERFCTR2 0x0000030a 605#define MSR_P4_FLAME_PERFCTR3 0x0000030b 606#define MSR_P4_IQ_PERFCTR0 0x0000030c 607#define MSR_P4_IQ_PERFCTR1 0x0000030d 608#define MSR_P4_IQ_PERFCTR2 0x0000030e 609#define MSR_P4_IQ_PERFCTR3 0x0000030f 610#define MSR_P4_IQ_PERFCTR4 0x00000310 611#define MSR_P4_IQ_PERFCTR5 0x00000311 612#define MSR_P4_BPU_CCCR0 0x00000360 613#define MSR_P4_BPU_CCCR1 0x00000361 614#define MSR_P4_BPU_CCCR2 0x00000362 615#define MSR_P4_BPU_CCCR3 0x00000363 616#define MSR_P4_MS_CCCR0 0x00000364 617#define MSR_P4_MS_CCCR1 0x00000365 618#define MSR_P4_MS_CCCR2 0x00000366 619#define MSR_P4_MS_CCCR3 0x00000367 620#define MSR_P4_FLAME_CCCR0 0x00000368 621#define MSR_P4_FLAME_CCCR1 0x00000369 622#define MSR_P4_FLAME_CCCR2 0x0000036a 623#define MSR_P4_FLAME_CCCR3 0x0000036b 624#define MSR_P4_IQ_CCCR0 0x0000036c 625#define MSR_P4_IQ_CCCR1 0x0000036d 626#define MSR_P4_IQ_CCCR2 0x0000036e 627#define MSR_P4_IQ_CCCR3 0x0000036f 628#define MSR_P4_IQ_CCCR4 0x00000370 629#define MSR_P4_IQ_CCCR5 0x00000371 630#define MSR_P4_ALF_ESCR0 0x000003ca 631#define MSR_P4_ALF_ESCR1 0x000003cb 632#define MSR_P4_BPU_ESCR0 0x000003b2 633#define MSR_P4_BPU_ESCR1 0x000003b3 634#define MSR_P4_BSU_ESCR0 0x000003a0 635#define MSR_P4_BSU_ESCR1 0x000003a1 636#define MSR_P4_CRU_ESCR0 0x000003b8 637#define MSR_P4_CRU_ESCR1 0x000003b9 638#define MSR_P4_CRU_ESCR2 0x000003cc 639#define MSR_P4_CRU_ESCR3 0x000003cd 640#define MSR_P4_CRU_ESCR4 0x000003e0 641#define MSR_P4_CRU_ESCR5 0x000003e1 642#define MSR_P4_DAC_ESCR0 0x000003a8 643#define MSR_P4_DAC_ESCR1 0x000003a9 644#define MSR_P4_FIRM_ESCR0 0x000003a4 645#define MSR_P4_FIRM_ESCR1 0x000003a5 646#define MSR_P4_FLAME_ESCR0 0x000003a6 647#define MSR_P4_FLAME_ESCR1 0x000003a7 648#define MSR_P4_FSB_ESCR0 0x000003a2 649#define MSR_P4_FSB_ESCR1 0x000003a3 650#define MSR_P4_IQ_ESCR0 0x000003ba 651#define MSR_P4_IQ_ESCR1 0x000003bb 652#define MSR_P4_IS_ESCR0 0x000003b4 653#define MSR_P4_IS_ESCR1 0x000003b5 654#define MSR_P4_ITLB_ESCR0 0x000003b6 655#define MSR_P4_ITLB_ESCR1 0x000003b7 656#define MSR_P4_IX_ESCR0 0x000003c8 657#define MSR_P4_IX_ESCR1 0x000003c9 658#define MSR_P4_MOB_ESCR0 0x000003aa 659#define MSR_P4_MOB_ESCR1 0x000003ab 660#define MSR_P4_MS_ESCR0 0x000003c0 661#define MSR_P4_MS_ESCR1 0x000003c1 662#define MSR_P4_PMH_ESCR0 0x000003ac 663#define MSR_P4_PMH_ESCR1 0x000003ad 664#define MSR_P4_RAT_ESCR0 0x000003bc 665#define MSR_P4_RAT_ESCR1 0x000003bd 666#define MSR_P4_SAAT_ESCR0 0x000003ae 667#define MSR_P4_SAAT_ESCR1 0x000003af 668#define MSR_P4_SSU_ESCR0 0x000003be 669#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 670 671#define MSR_P4_TBPU_ESCR0 0x000003c2 672#define MSR_P4_TBPU_ESCR1 0x000003c3 673#define MSR_P4_TC_ESCR0 0x000003c4 674#define MSR_P4_TC_ESCR1 0x000003c5 675#define MSR_P4_U2L_ESCR0 0x000003b0 676#define MSR_P4_U2L_ESCR1 0x000003b1 677 678#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 679 680/* Intel Core-based CPU performance counters */ 681#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 682#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 683#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 684#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 685#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 686#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 687#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 688 689/* Geode defined MSRs */ 690#define MSR_GEODE_BUSCONT_CONF0 0x00001900 691 692/* Intel VT MSRs */ 693#define MSR_IA32_VMX_BASIC 0x00000480 694#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 695#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 696#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 697#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 698#define MSR_IA32_VMX_MISC 0x00000485 699#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 700#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 701#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 702#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 703#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 704#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 705#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 706#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 707#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 708#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 709#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 710#define MSR_IA32_VMX_VMFUNC 0x00000491 711 712/* VMX_BASIC bits and bitmasks */ 713#define VMX_BASIC_VMCS_SIZE_SHIFT 32 714#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 715#define VMX_BASIC_64 0x0001000000000000LLU 716#define VMX_BASIC_MEM_TYPE_SHIFT 50 717#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 718#define VMX_BASIC_MEM_TYPE_WB 6LLU 719#define VMX_BASIC_INOUT 0x0040000000000000LLU 720 721/* MSR_IA32_VMX_MISC bits */ 722#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 723#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 724/* AMD-V MSRs */ 725 726#define MSR_VM_CR 0xc0010114 727#define MSR_VM_IGNNE 0xc0010115 728#define MSR_VM_HSAVE_PA 0xc0010117 729 730#endif /* _ASM_X86_MSR_INDEX_H */ 731