1
2#ifndef __MACH_MMP_CLK_H
3#define __MACH_MMP_CLK_H
4
5#include <linux/clk-provider.h>
6#include <linux/clkdev.h>
7
8#define APBC_NO_BUS_CTRL BIT(0)
9#define APBC_POWER_CTRL BIT(1)
10
11
12
13struct mmp_clk_factor_masks {
14 unsigned int factor;
15 unsigned int num_mask;
16 unsigned int den_mask;
17 unsigned int num_shift;
18 unsigned int den_shift;
19};
20
21struct mmp_clk_factor_tbl {
22 unsigned int num;
23 unsigned int den;
24};
25
26struct mmp_clk_factor {
27 struct clk_hw hw;
28 void __iomem *base;
29 struct mmp_clk_factor_masks *masks;
30 struct mmp_clk_factor_tbl *ftbl;
31 unsigned int ftbl_cnt;
32 spinlock_t *lock;
33};
34
35extern struct clk *mmp_clk_register_factor(const char *name,
36 const char *parent_name, unsigned long flags,
37 void __iomem *base, struct mmp_clk_factor_masks *masks,
38 struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
39 spinlock_t *lock);
40
41
42#define MMP_CLK_BITS_MASK(width, shift) \
43 (((1 << (width)) - 1) << (shift))
44#define MMP_CLK_BITS_GET_VAL(data, width, shift) \
45 ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
46#define MMP_CLK_BITS_SET_VAL(val, width, shift) \
47 (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
48
49enum {
50 MMP_CLK_MIX_TYPE_V1,
51 MMP_CLK_MIX_TYPE_V2,
52 MMP_CLK_MIX_TYPE_V3,
53};
54
55
56struct mmp_clk_mix_reg_info {
57 void __iomem *reg_clk_ctrl;
58 void __iomem *reg_clk_sel;
59 u8 width_div;
60 u8 shift_div;
61 u8 width_mux;
62 u8 shift_mux;
63 u8 bit_fc;
64};
65
66
67struct mmp_clk_mix_clk_table {
68 unsigned long rate;
69 u8 parent_index;
70 unsigned int divisor;
71 unsigned int valid;
72};
73
74struct mmp_clk_mix_config {
75 struct mmp_clk_mix_reg_info reg_info;
76 struct mmp_clk_mix_clk_table *table;
77 unsigned int table_size;
78 u32 *mux_table;
79 struct clk_div_table *div_table;
80 u8 div_flags;
81 u8 mux_flags;
82};
83
84struct mmp_clk_mix {
85 struct clk_hw hw;
86 struct mmp_clk_mix_reg_info reg_info;
87 struct mmp_clk_mix_clk_table *table;
88 u32 *mux_table;
89 struct clk_div_table *div_table;
90 unsigned int table_size;
91 u8 div_flags;
92 u8 mux_flags;
93 unsigned int type;
94 spinlock_t *lock;
95};
96
97extern const struct clk_ops mmp_clk_mix_ops;
98extern struct clk *mmp_clk_register_mix(struct device *dev,
99 const char *name,
100 const char **parent_names,
101 u8 num_parents,
102 unsigned long flags,
103 struct mmp_clk_mix_config *config,
104 spinlock_t *lock);
105
106
107
108#define MMP_CLK_GATE_NEED_DELAY BIT(0)
109
110struct mmp_clk_gate {
111 struct clk_hw hw;
112 void __iomem *reg;
113 u32 mask;
114 u32 val_enable;
115 u32 val_disable;
116 unsigned int flags;
117 spinlock_t *lock;
118};
119
120extern const struct clk_ops mmp_clk_gate_ops;
121extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
122 const char *parent_name, unsigned long flags,
123 void __iomem *reg, u32 mask, u32 val_enable,
124 u32 val_disable, unsigned int gate_flags,
125 spinlock_t *lock);
126
127
128extern struct clk *mmp_clk_register_pll2(const char *name,
129 const char *parent_name, unsigned long flags);
130extern struct clk *mmp_clk_register_apbc(const char *name,
131 const char *parent_name, void __iomem *base,
132 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
133extern struct clk *mmp_clk_register_apmu(const char *name,
134 const char *parent_name, void __iomem *base, u32 enable_mask,
135 spinlock_t *lock);
136
137struct mmp_clk_unit {
138 unsigned int nr_clks;
139 struct clk **clk_table;
140 struct clk_onecell_data clk_data;
141};
142
143struct mmp_param_fixed_rate_clk {
144 unsigned int id;
145 char *name;
146 const char *parent_name;
147 unsigned long flags;
148 unsigned long fixed_rate;
149};
150void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
151 struct mmp_param_fixed_rate_clk *clks,
152 int size);
153
154struct mmp_param_fixed_factor_clk {
155 unsigned int id;
156 char *name;
157 const char *parent_name;
158 unsigned long mult;
159 unsigned long div;
160 unsigned long flags;
161};
162void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
163 struct mmp_param_fixed_factor_clk *clks,
164 int size);
165
166struct mmp_param_general_gate_clk {
167 unsigned int id;
168 const char *name;
169 const char *parent_name;
170 unsigned long flags;
171 unsigned long offset;
172 u8 bit_idx;
173 u8 gate_flags;
174 spinlock_t *lock;
175};
176void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
177 struct mmp_param_general_gate_clk *clks,
178 void __iomem *base, int size);
179
180struct mmp_param_gate_clk {
181 unsigned int id;
182 char *name;
183 const char *parent_name;
184 unsigned long flags;
185 unsigned long offset;
186 u32 mask;
187 u32 val_enable;
188 u32 val_disable;
189 unsigned int gate_flags;
190 spinlock_t *lock;
191};
192void mmp_register_gate_clks(struct mmp_clk_unit *unit,
193 struct mmp_param_gate_clk *clks,
194 void __iomem *base, int size);
195
196struct mmp_param_mux_clk {
197 unsigned int id;
198 char *name;
199 const char **parent_name;
200 u8 num_parents;
201 unsigned long flags;
202 unsigned long offset;
203 u8 shift;
204 u8 width;
205 u8 mux_flags;
206 spinlock_t *lock;
207};
208void mmp_register_mux_clks(struct mmp_clk_unit *unit,
209 struct mmp_param_mux_clk *clks,
210 void __iomem *base, int size);
211
212struct mmp_param_div_clk {
213 unsigned int id;
214 char *name;
215 const char *parent_name;
216 unsigned long flags;
217 unsigned long offset;
218 u8 shift;
219 u8 width;
220 u8 div_flags;
221 spinlock_t *lock;
222};
223void mmp_register_div_clks(struct mmp_clk_unit *unit,
224 struct mmp_param_div_clk *clks,
225 void __iomem *base, int size);
226
227#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
228{ \
229 .width_div = (w_d), \
230 .shift_div = (s_d), \
231 .width_mux = (w_m), \
232 .shift_mux = (s_m), \
233 .bit_fc = (fc), \
234}
235
236void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
237 int nr_clks);
238void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
239 struct clk *clk);
240#endif
241
