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32#include <drm/ttm/ttm_bo_api.h>
33#include <drm/ttm/ttm_bo_driver.h>
34#include <drm/ttm/ttm_placement.h>
35#include <drm/ttm/ttm_module.h>
36#include <drm/ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/amdgpu_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include <linux/swiotlb.h>
42#include <linux/swap.h>
43#include <linux/pagemap.h>
44#include <linux/debugfs.h>
45#include "amdgpu.h"
46#include "amdgpu_trace.h"
47#include "bif/bif_4_1_d.h"
48
49#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
50
51static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
52 struct ttm_mem_reg *mem, unsigned num_pages,
53 uint64_t offset, unsigned window,
54 struct amdgpu_ring *ring,
55 uint64_t *addr);
56
57static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
58static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
59
60
61
62
63static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
64{
65 return ttm_mem_global_init(ref->object);
66}
67
68static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
69{
70 ttm_mem_global_release(ref->object);
71}
72
73static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
74{
75 struct drm_global_reference *global_ref;
76 struct amdgpu_ring *ring;
77 struct amd_sched_rq *rq;
78 int r;
79
80 adev->mman.mem_global_referenced = false;
81 global_ref = &adev->mman.mem_global_ref;
82 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
83 global_ref->size = sizeof(struct ttm_mem_global);
84 global_ref->init = &amdgpu_ttm_mem_global_init;
85 global_ref->release = &amdgpu_ttm_mem_global_release;
86 r = drm_global_item_ref(global_ref);
87 if (r) {
88 DRM_ERROR("Failed setting up TTM memory accounting "
89 "subsystem.\n");
90 goto error_mem;
91 }
92
93 adev->mman.bo_global_ref.mem_glob =
94 adev->mman.mem_global_ref.object;
95 global_ref = &adev->mman.bo_global_ref.ref;
96 global_ref->global_type = DRM_GLOBAL_TTM_BO;
97 global_ref->size = sizeof(struct ttm_bo_global);
98 global_ref->init = &ttm_bo_global_init;
99 global_ref->release = &ttm_bo_global_release;
100 r = drm_global_item_ref(global_ref);
101 if (r) {
102 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
103 goto error_bo;
104 }
105
106 mutex_init(&adev->mman.gtt_window_lock);
107
108 ring = adev->mman.buffer_funcs_ring;
109 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
110 r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
111 rq, amdgpu_sched_jobs);
112 if (r) {
113 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
114 goto error_entity;
115 }
116
117 adev->mman.mem_global_referenced = true;
118
119 return 0;
120
121error_entity:
122 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
123error_bo:
124 drm_global_item_unref(&adev->mman.mem_global_ref);
125error_mem:
126 return r;
127}
128
129static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
130{
131 if (adev->mman.mem_global_referenced) {
132 amd_sched_entity_fini(adev->mman.entity.sched,
133 &adev->mman.entity);
134 mutex_destroy(&adev->mman.gtt_window_lock);
135 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
136 drm_global_item_unref(&adev->mman.mem_global_ref);
137 adev->mman.mem_global_referenced = false;
138 }
139}
140
141static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
142{
143 return 0;
144}
145
146static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
147 struct ttm_mem_type_manager *man)
148{
149 struct amdgpu_device *adev;
150
151 adev = amdgpu_ttm_adev(bdev);
152
153 switch (type) {
154 case TTM_PL_SYSTEM:
155
156 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
157 man->available_caching = TTM_PL_MASK_CACHING;
158 man->default_caching = TTM_PL_FLAG_CACHED;
159 break;
160 case TTM_PL_TT:
161 man->func = &amdgpu_gtt_mgr_func;
162 man->gpu_offset = adev->mc.gart_start;
163 man->available_caching = TTM_PL_MASK_CACHING;
164 man->default_caching = TTM_PL_FLAG_CACHED;
165 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
166 break;
167 case TTM_PL_VRAM:
168
169 man->func = &amdgpu_vram_mgr_func;
170 man->gpu_offset = adev->mc.vram_start;
171 man->flags = TTM_MEMTYPE_FLAG_FIXED |
172 TTM_MEMTYPE_FLAG_MAPPABLE;
173 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
174 man->default_caching = TTM_PL_FLAG_WC;
175 break;
176 case AMDGPU_PL_GDS:
177 case AMDGPU_PL_GWS:
178 case AMDGPU_PL_OA:
179
180 man->func = &ttm_bo_manager_func;
181 man->gpu_offset = 0;
182 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
183 man->available_caching = TTM_PL_FLAG_UNCACHED;
184 man->default_caching = TTM_PL_FLAG_UNCACHED;
185 break;
186 default:
187 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
188 return -EINVAL;
189 }
190 return 0;
191}
192
193static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
194 struct ttm_placement *placement)
195{
196 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
197 struct amdgpu_bo *abo;
198 static const struct ttm_place placements = {
199 .fpfn = 0,
200 .lpfn = 0,
201 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
202 };
203
204 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
205 placement->placement = &placements;
206 placement->busy_placement = &placements;
207 placement->num_placement = 1;
208 placement->num_busy_placement = 1;
209 return;
210 }
211 abo = container_of(bo, struct amdgpu_bo, tbo);
212 switch (bo->mem.mem_type) {
213 case TTM_PL_VRAM:
214 if (adev->mman.buffer_funcs &&
215 adev->mman.buffer_funcs_ring &&
216 adev->mman.buffer_funcs_ring->ready == false) {
217 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
218 } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
219 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
220 unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
221 struct drm_mm_node *node = bo->mem.mm_node;
222 unsigned long pages_left;
223
224 for (pages_left = bo->mem.num_pages;
225 pages_left;
226 pages_left -= node->size, node++) {
227 if (node->start < fpfn)
228 break;
229 }
230
231 if (!pages_left)
232 goto gtt;
233
234
235
236
237
238
239 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
240 AMDGPU_GEM_DOMAIN_GTT);
241 abo->placements[0].fpfn = fpfn;
242 abo->placements[0].lpfn = 0;
243 abo->placement.busy_placement = &abo->placements[1];
244 abo->placement.num_busy_placement = 1;
245 } else {
246gtt:
247 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
248 }
249 break;
250 case TTM_PL_TT:
251 default:
252 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
253 }
254 *placement = abo->placement;
255}
256
257static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
258{
259 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
260
261 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
262 return -EPERM;
263 return drm_vma_node_verify_access(&abo->gem_base.vma_node,
264 filp->private_data);
265}
266
267static void amdgpu_move_null(struct ttm_buffer_object *bo,
268 struct ttm_mem_reg *new_mem)
269{
270 struct ttm_mem_reg *old_mem = &bo->mem;
271
272 BUG_ON(old_mem->mm_node != NULL);
273 *old_mem = *new_mem;
274 new_mem->mm_node = NULL;
275}
276
277static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
278 struct drm_mm_node *mm_node,
279 struct ttm_mem_reg *mem)
280{
281 uint64_t addr = 0;
282
283 if (mem->mem_type != TTM_PL_TT ||
284 amdgpu_gtt_mgr_is_allocated(mem)) {
285 addr = mm_node->start << PAGE_SHIFT;
286 addr += bo->bdev->man[mem->mem_type].gpu_offset;
287 }
288 return addr;
289}
290
291static int amdgpu_move_blit(struct ttm_buffer_object *bo,
292 bool evict, bool no_wait_gpu,
293 struct ttm_mem_reg *new_mem,
294 struct ttm_mem_reg *old_mem)
295{
296 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
297 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
298
299 struct drm_mm_node *old_mm, *new_mm;
300 uint64_t old_start, old_size, new_start, new_size;
301 unsigned long num_pages;
302 struct dma_fence *fence = NULL;
303 int r;
304
305 BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
306
307 if (!ring->ready) {
308 DRM_ERROR("Trying to move memory with ring turned off.\n");
309 return -EINVAL;
310 }
311
312 old_mm = old_mem->mm_node;
313 old_size = old_mm->size;
314 old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
315
316 new_mm = new_mem->mm_node;
317 new_size = new_mm->size;
318 new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
319
320 num_pages = new_mem->num_pages;
321 mutex_lock(&adev->mman.gtt_window_lock);
322 while (num_pages) {
323 unsigned long cur_pages = min(min(old_size, new_size),
324 (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
325 uint64_t from = old_start, to = new_start;
326 struct dma_fence *next;
327
328 if (old_mem->mem_type == TTM_PL_TT &&
329 !amdgpu_gtt_mgr_is_allocated(old_mem)) {
330 r = amdgpu_map_buffer(bo, old_mem, cur_pages,
331 old_start, 0, ring, &from);
332 if (r)
333 goto error;
334 }
335
336 if (new_mem->mem_type == TTM_PL_TT &&
337 !amdgpu_gtt_mgr_is_allocated(new_mem)) {
338 r = amdgpu_map_buffer(bo, new_mem, cur_pages,
339 new_start, 1, ring, &to);
340 if (r)
341 goto error;
342 }
343
344 r = amdgpu_copy_buffer(ring, from, to,
345 cur_pages * PAGE_SIZE,
346 bo->resv, &next, false, true);
347 if (r)
348 goto error;
349
350 dma_fence_put(fence);
351 fence = next;
352
353 num_pages -= cur_pages;
354 if (!num_pages)
355 break;
356
357 old_size -= cur_pages;
358 if (!old_size) {
359 old_start = amdgpu_mm_node_addr(bo, ++old_mm, old_mem);
360 old_size = old_mm->size;
361 } else {
362 old_start += cur_pages * PAGE_SIZE;
363 }
364
365 new_size -= cur_pages;
366 if (!new_size) {
367 new_start = amdgpu_mm_node_addr(bo, ++new_mm, new_mem);
368 new_size = new_mm->size;
369 } else {
370 new_start += cur_pages * PAGE_SIZE;
371 }
372 }
373 mutex_unlock(&adev->mman.gtt_window_lock);
374
375 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
376 dma_fence_put(fence);
377 return r;
378
379error:
380 mutex_unlock(&adev->mman.gtt_window_lock);
381
382 if (fence)
383 dma_fence_wait(fence, false);
384 dma_fence_put(fence);
385 return r;
386}
387
388static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
389 bool evict, bool interruptible,
390 bool no_wait_gpu,
391 struct ttm_mem_reg *new_mem)
392{
393 struct amdgpu_device *adev;
394 struct ttm_mem_reg *old_mem = &bo->mem;
395 struct ttm_mem_reg tmp_mem;
396 struct ttm_place placements;
397 struct ttm_placement placement;
398 int r;
399
400 adev = amdgpu_ttm_adev(bo->bdev);
401 tmp_mem = *new_mem;
402 tmp_mem.mm_node = NULL;
403 placement.num_placement = 1;
404 placement.placement = &placements;
405 placement.num_busy_placement = 1;
406 placement.busy_placement = &placements;
407 placements.fpfn = 0;
408 placements.lpfn = 0;
409 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
410 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
411 interruptible, no_wait_gpu);
412 if (unlikely(r)) {
413 return r;
414 }
415
416 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
417 if (unlikely(r)) {
418 goto out_cleanup;
419 }
420
421 r = ttm_tt_bind(bo->ttm, &tmp_mem);
422 if (unlikely(r)) {
423 goto out_cleanup;
424 }
425 r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
426 if (unlikely(r)) {
427 goto out_cleanup;
428 }
429 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
430out_cleanup:
431 ttm_bo_mem_put(bo, &tmp_mem);
432 return r;
433}
434
435static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
436 bool evict, bool interruptible,
437 bool no_wait_gpu,
438 struct ttm_mem_reg *new_mem)
439{
440 struct amdgpu_device *adev;
441 struct ttm_mem_reg *old_mem = &bo->mem;
442 struct ttm_mem_reg tmp_mem;
443 struct ttm_placement placement;
444 struct ttm_place placements;
445 int r;
446
447 adev = amdgpu_ttm_adev(bo->bdev);
448 tmp_mem = *new_mem;
449 tmp_mem.mm_node = NULL;
450 placement.num_placement = 1;
451 placement.placement = &placements;
452 placement.num_busy_placement = 1;
453 placement.busy_placement = &placements;
454 placements.fpfn = 0;
455 placements.lpfn = 0;
456 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
457 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
458 interruptible, no_wait_gpu);
459 if (unlikely(r)) {
460 return r;
461 }
462 r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
463 if (unlikely(r)) {
464 goto out_cleanup;
465 }
466 r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
467 if (unlikely(r)) {
468 goto out_cleanup;
469 }
470out_cleanup:
471 ttm_bo_mem_put(bo, &tmp_mem);
472 return r;
473}
474
475static int amdgpu_bo_move(struct ttm_buffer_object *bo,
476 bool evict, bool interruptible,
477 bool no_wait_gpu,
478 struct ttm_mem_reg *new_mem)
479{
480 struct amdgpu_device *adev;
481 struct amdgpu_bo *abo;
482 struct ttm_mem_reg *old_mem = &bo->mem;
483 int r;
484
485
486 abo = container_of(bo, struct amdgpu_bo, tbo);
487 if (WARN_ON_ONCE(abo->pin_count > 0))
488 return -EINVAL;
489
490 adev = amdgpu_ttm_adev(bo->bdev);
491
492 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
493 amdgpu_move_null(bo, new_mem);
494 return 0;
495 }
496 if ((old_mem->mem_type == TTM_PL_TT &&
497 new_mem->mem_type == TTM_PL_SYSTEM) ||
498 (old_mem->mem_type == TTM_PL_SYSTEM &&
499 new_mem->mem_type == TTM_PL_TT)) {
500
501 amdgpu_move_null(bo, new_mem);
502 return 0;
503 }
504 if (adev->mman.buffer_funcs == NULL ||
505 adev->mman.buffer_funcs_ring == NULL ||
506 !adev->mman.buffer_funcs_ring->ready) {
507
508 goto memcpy;
509 }
510
511 if (old_mem->mem_type == TTM_PL_VRAM &&
512 new_mem->mem_type == TTM_PL_SYSTEM) {
513 r = amdgpu_move_vram_ram(bo, evict, interruptible,
514 no_wait_gpu, new_mem);
515 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
516 new_mem->mem_type == TTM_PL_VRAM) {
517 r = amdgpu_move_ram_vram(bo, evict, interruptible,
518 no_wait_gpu, new_mem);
519 } else {
520 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
521 }
522
523 if (r) {
524memcpy:
525 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
526 if (r) {
527 return r;
528 }
529 }
530
531 if (bo->type == ttm_bo_type_device &&
532 new_mem->mem_type == TTM_PL_VRAM &&
533 old_mem->mem_type != TTM_PL_VRAM) {
534
535
536
537 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
538 }
539
540
541 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
542 return 0;
543}
544
545static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
546{
547 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
548 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
549
550 mem->bus.addr = NULL;
551 mem->bus.offset = 0;
552 mem->bus.size = mem->num_pages << PAGE_SHIFT;
553 mem->bus.base = 0;
554 mem->bus.is_iomem = false;
555 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
556 return -EINVAL;
557 switch (mem->mem_type) {
558 case TTM_PL_SYSTEM:
559
560 return 0;
561 case TTM_PL_TT:
562 break;
563 case TTM_PL_VRAM:
564 mem->bus.offset = mem->start << PAGE_SHIFT;
565
566 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
567 return -EINVAL;
568 mem->bus.base = adev->mc.aper_base;
569 mem->bus.is_iomem = true;
570 break;
571 default:
572 return -EINVAL;
573 }
574 return 0;
575}
576
577static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
578{
579}
580
581static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
582 unsigned long page_offset)
583{
584 struct drm_mm_node *mm = bo->mem.mm_node;
585 uint64_t size = mm->size;
586 uint64_t offset = page_offset;
587
588 page_offset = do_div(offset, size);
589 mm += offset;
590 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start + page_offset;
591}
592
593
594
595
596struct amdgpu_ttm_gup_task_list {
597 struct list_head list;
598 struct task_struct *task;
599};
600
601struct amdgpu_ttm_tt {
602 struct ttm_dma_tt ttm;
603 struct amdgpu_device *adev;
604 u64 offset;
605 uint64_t userptr;
606 struct mm_struct *usermm;
607 uint32_t userflags;
608 spinlock_t guptasklock;
609 struct list_head guptasks;
610 atomic_t mmu_invalidations;
611 struct list_head list;
612};
613
614int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
615{
616 struct amdgpu_ttm_tt *gtt = (void *)ttm;
617 unsigned int flags = 0;
618 unsigned pinned = 0;
619 int r;
620
621 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
622 flags |= FOLL_WRITE;
623
624 if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
625
626
627 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
628 struct vm_area_struct *vma;
629
630 vma = find_vma(gtt->usermm, gtt->userptr);
631 if (!vma || vma->vm_file || vma->vm_end < end)
632 return -EPERM;
633 }
634
635 do {
636 unsigned num_pages = ttm->num_pages - pinned;
637 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
638 struct page **p = pages + pinned;
639 struct amdgpu_ttm_gup_task_list guptask;
640
641 guptask.task = current;
642 spin_lock(>t->guptasklock);
643 list_add(&guptask.list, >t->guptasks);
644 spin_unlock(>t->guptasklock);
645
646 r = get_user_pages(userptr, num_pages, flags, p, NULL);
647
648 spin_lock(>t->guptasklock);
649 list_del(&guptask.list);
650 spin_unlock(>t->guptasklock);
651
652 if (r < 0)
653 goto release_pages;
654
655 pinned += r;
656
657 } while (pinned < ttm->num_pages);
658
659 return 0;
660
661release_pages:
662 release_pages(pages, pinned, 0);
663 return r;
664}
665
666static void amdgpu_trace_dma_map(struct ttm_tt *ttm)
667{
668 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
669 struct amdgpu_ttm_tt *gtt = (void *)ttm;
670 unsigned i;
671
672 if (unlikely(trace_amdgpu_ttm_tt_populate_enabled())) {
673 for (i = 0; i < ttm->num_pages; i++) {
674 trace_amdgpu_ttm_tt_populate(
675 adev,
676 gtt->ttm.dma_address[i],
677 page_to_phys(ttm->pages[i]));
678 }
679 }
680}
681
682static void amdgpu_trace_dma_unmap(struct ttm_tt *ttm)
683{
684 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
685 struct amdgpu_ttm_tt *gtt = (void *)ttm;
686 unsigned i;
687
688 if (unlikely(trace_amdgpu_ttm_tt_unpopulate_enabled())) {
689 for (i = 0; i < ttm->num_pages; i++) {
690 trace_amdgpu_ttm_tt_unpopulate(
691 adev,
692 gtt->ttm.dma_address[i],
693 page_to_phys(ttm->pages[i]));
694 }
695 }
696}
697
698
699static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
700{
701 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
702 struct amdgpu_ttm_tt *gtt = (void *)ttm;
703 unsigned nents;
704 int r;
705
706 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
707 enum dma_data_direction direction = write ?
708 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
709
710 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
711 ttm->num_pages << PAGE_SHIFT,
712 GFP_KERNEL);
713 if (r)
714 goto release_sg;
715
716 r = -ENOMEM;
717 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
718 if (nents != ttm->sg->nents)
719 goto release_sg;
720
721 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
722 gtt->ttm.dma_address, ttm->num_pages);
723
724 amdgpu_trace_dma_map(ttm);
725
726 return 0;
727
728release_sg:
729 kfree(ttm->sg);
730 return r;
731}
732
733static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
734{
735 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
736 struct amdgpu_ttm_tt *gtt = (void *)ttm;
737 struct sg_page_iter sg_iter;
738
739 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
740 enum dma_data_direction direction = write ?
741 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
742
743
744 if (!ttm->sg->sgl)
745 return;
746
747
748 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
749
750 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
751 struct page *page = sg_page_iter_page(&sg_iter);
752 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
753 set_page_dirty(page);
754
755 mark_page_accessed(page);
756 put_page(page);
757 }
758
759 amdgpu_trace_dma_unmap(ttm);
760
761 sg_free_table(ttm->sg);
762}
763
764static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
765 struct ttm_mem_reg *bo_mem)
766{
767 struct amdgpu_ttm_tt *gtt = (void*)ttm;
768 uint64_t flags;
769 int r = 0;
770
771 if (gtt->userptr) {
772 r = amdgpu_ttm_tt_pin_userptr(ttm);
773 if (r) {
774 DRM_ERROR("failed to pin userptr\n");
775 return r;
776 }
777 }
778 if (!ttm->num_pages) {
779 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
780 ttm->num_pages, bo_mem, ttm);
781 }
782
783 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
784 bo_mem->mem_type == AMDGPU_PL_GWS ||
785 bo_mem->mem_type == AMDGPU_PL_OA)
786 return -EINVAL;
787
788 if (!amdgpu_gtt_mgr_is_allocated(bo_mem))
789 return 0;
790
791 spin_lock(>t->adev->gtt_list_lock);
792 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
793 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
794 r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
795 ttm->pages, gtt->ttm.dma_address, flags);
796
797 if (r) {
798 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
799 ttm->num_pages, gtt->offset);
800 goto error_gart_bind;
801 }
802
803 list_add_tail(>t->list, >t->adev->gtt_list);
804error_gart_bind:
805 spin_unlock(>t->adev->gtt_list_lock);
806 return r;
807}
808
809bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
810{
811 struct amdgpu_ttm_tt *gtt = (void *)ttm;
812
813 return gtt && !list_empty(>t->list);
814}
815
816int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
817{
818 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
819 struct ttm_tt *ttm = bo->ttm;
820 struct ttm_mem_reg tmp;
821
822 struct ttm_placement placement;
823 struct ttm_place placements;
824 int r;
825
826 if (!ttm || amdgpu_ttm_is_bound(ttm))
827 return 0;
828
829 tmp = bo->mem;
830 tmp.mm_node = NULL;
831 placement.num_placement = 1;
832 placement.placement = &placements;
833 placement.num_busy_placement = 1;
834 placement.busy_placement = &placements;
835 placements.fpfn = 0;
836 placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
837 placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
838
839 r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
840 if (unlikely(r))
841 return r;
842
843 r = ttm_bo_move_ttm(bo, true, false, &tmp);
844 if (unlikely(r))
845 ttm_bo_mem_put(bo, &tmp);
846 else
847 bo->offset = (bo->mem.start << PAGE_SHIFT) +
848 bo->bdev->man[bo->mem.mem_type].gpu_offset;
849
850 return r;
851}
852
853int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
854{
855 struct amdgpu_ttm_tt *gtt, *tmp;
856 struct ttm_mem_reg bo_mem;
857 uint64_t flags;
858 int r;
859
860 bo_mem.mem_type = TTM_PL_TT;
861 spin_lock(&adev->gtt_list_lock);
862 list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
863 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >t->ttm.ttm, &bo_mem);
864 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
865 gtt->ttm.ttm.pages, gtt->ttm.dma_address,
866 flags);
867 if (r) {
868 spin_unlock(&adev->gtt_list_lock);
869 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
870 gtt->ttm.ttm.num_pages, gtt->offset);
871 return r;
872 }
873 }
874 spin_unlock(&adev->gtt_list_lock);
875 return 0;
876}
877
878static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
879{
880 struct amdgpu_ttm_tt *gtt = (void *)ttm;
881 int r;
882
883 if (gtt->userptr)
884 amdgpu_ttm_tt_unpin_userptr(ttm);
885
886 if (!amdgpu_ttm_is_bound(ttm))
887 return 0;
888
889
890 spin_lock(>t->adev->gtt_list_lock);
891 r = amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
892 if (r) {
893 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
894 gtt->ttm.ttm.num_pages, gtt->offset);
895 goto error_unbind;
896 }
897 list_del_init(>t->list);
898error_unbind:
899 spin_unlock(>t->adev->gtt_list_lock);
900 return r;
901}
902
903static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
904{
905 struct amdgpu_ttm_tt *gtt = (void *)ttm;
906
907 ttm_dma_tt_fini(>t->ttm);
908 kfree(gtt);
909}
910
911static struct ttm_backend_func amdgpu_backend_func = {
912 .bind = &amdgpu_ttm_backend_bind,
913 .unbind = &amdgpu_ttm_backend_unbind,
914 .destroy = &amdgpu_ttm_backend_destroy,
915};
916
917static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
918 unsigned long size, uint32_t page_flags,
919 struct page *dummy_read_page)
920{
921 struct amdgpu_device *adev;
922 struct amdgpu_ttm_tt *gtt;
923
924 adev = amdgpu_ttm_adev(bdev);
925
926 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
927 if (gtt == NULL) {
928 return NULL;
929 }
930 gtt->ttm.ttm.func = &amdgpu_backend_func;
931 gtt->adev = adev;
932 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
933 kfree(gtt);
934 return NULL;
935 }
936 INIT_LIST_HEAD(>t->list);
937 return >t->ttm.ttm;
938}
939
940static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
941{
942 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
943 struct amdgpu_ttm_tt *gtt = (void *)ttm;
944 unsigned i;
945 int r;
946 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
947
948 if (ttm->state != tt_unpopulated)
949 return 0;
950
951 if (gtt && gtt->userptr) {
952 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
953 if (!ttm->sg)
954 return -ENOMEM;
955
956 ttm->page_flags |= TTM_PAGE_FLAG_SG;
957 ttm->state = tt_unbound;
958 return 0;
959 }
960
961 if (slave && ttm->sg) {
962 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
963 gtt->ttm.dma_address, ttm->num_pages);
964 ttm->state = tt_unbound;
965 r = 0;
966 goto trace_mappings;
967 }
968
969#ifdef CONFIG_SWIOTLB
970 if (swiotlb_nr_tbl()) {
971 r = ttm_dma_populate(>t->ttm, adev->dev);
972 goto trace_mappings;
973 }
974#endif
975
976 r = ttm_pool_populate(ttm);
977 if (r) {
978 return r;
979 }
980
981 for (i = 0; i < ttm->num_pages; i++) {
982 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
983 0, PAGE_SIZE,
984 PCI_DMA_BIDIRECTIONAL);
985 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
986 while (i--) {
987 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
988 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
989 gtt->ttm.dma_address[i] = 0;
990 }
991 ttm_pool_unpopulate(ttm);
992 return -EFAULT;
993 }
994 }
995
996 r = 0;
997trace_mappings:
998 if (likely(!r))
999 amdgpu_trace_dma_map(ttm);
1000 return r;
1001}
1002
1003static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1004{
1005 struct amdgpu_device *adev;
1006 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1007 unsigned i;
1008 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1009
1010 if (gtt && gtt->userptr) {
1011 kfree(ttm->sg);
1012 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1013 return;
1014 }
1015
1016 if (slave)
1017 return;
1018
1019 adev = amdgpu_ttm_adev(ttm->bdev);
1020
1021 amdgpu_trace_dma_unmap(ttm);
1022
1023#ifdef CONFIG_SWIOTLB
1024 if (swiotlb_nr_tbl()) {
1025 ttm_dma_unpopulate(>t->ttm, adev->dev);
1026 return;
1027 }
1028#endif
1029
1030 for (i = 0; i < ttm->num_pages; i++) {
1031 if (gtt->ttm.dma_address[i]) {
1032 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
1033 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1034 }
1035 }
1036
1037 ttm_pool_unpopulate(ttm);
1038}
1039
1040int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1041 uint32_t flags)
1042{
1043 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1044
1045 if (gtt == NULL)
1046 return -EINVAL;
1047
1048 gtt->userptr = addr;
1049 gtt->usermm = current->mm;
1050 gtt->userflags = flags;
1051 spin_lock_init(>t->guptasklock);
1052 INIT_LIST_HEAD(>t->guptasks);
1053 atomic_set(>t->mmu_invalidations, 0);
1054
1055 return 0;
1056}
1057
1058struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1059{
1060 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1061
1062 if (gtt == NULL)
1063 return NULL;
1064
1065 return gtt->usermm;
1066}
1067
1068bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1069 unsigned long end)
1070{
1071 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1072 struct amdgpu_ttm_gup_task_list *entry;
1073 unsigned long size;
1074
1075 if (gtt == NULL || !gtt->userptr)
1076 return false;
1077
1078 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1079 if (gtt->userptr > end || gtt->userptr + size <= start)
1080 return false;
1081
1082 spin_lock(>t->guptasklock);
1083 list_for_each_entry(entry, >t->guptasks, list) {
1084 if (entry->task == current) {
1085 spin_unlock(>t->guptasklock);
1086 return false;
1087 }
1088 }
1089 spin_unlock(>t->guptasklock);
1090
1091 atomic_inc(>t->mmu_invalidations);
1092
1093 return true;
1094}
1095
1096bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1097 int *last_invalidated)
1098{
1099 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1100 int prev_invalidated = *last_invalidated;
1101
1102 *last_invalidated = atomic_read(>t->mmu_invalidations);
1103 return prev_invalidated != *last_invalidated;
1104}
1105
1106bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1107{
1108 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1109
1110 if (gtt == NULL)
1111 return false;
1112
1113 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1114}
1115
1116uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1117 struct ttm_mem_reg *mem)
1118{
1119 uint64_t flags = 0;
1120
1121 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1122 flags |= AMDGPU_PTE_VALID;
1123
1124 if (mem && mem->mem_type == TTM_PL_TT) {
1125 flags |= AMDGPU_PTE_SYSTEM;
1126
1127 if (ttm->caching_state == tt_cached)
1128 flags |= AMDGPU_PTE_SNOOPED;
1129 }
1130
1131 flags |= adev->gart.gart_pte_flags;
1132 flags |= AMDGPU_PTE_READABLE;
1133
1134 if (!amdgpu_ttm_tt_is_readonly(ttm))
1135 flags |= AMDGPU_PTE_WRITEABLE;
1136
1137 return flags;
1138}
1139
1140static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1141 const struct ttm_place *place)
1142{
1143 unsigned long num_pages = bo->mem.num_pages;
1144 struct drm_mm_node *node = bo->mem.mm_node;
1145
1146 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1147 return ttm_bo_eviction_valuable(bo, place);
1148
1149 switch (bo->mem.mem_type) {
1150 case TTM_PL_TT:
1151 return true;
1152
1153 case TTM_PL_VRAM:
1154
1155 while (num_pages) {
1156 if (place->fpfn < (node->start + node->size) &&
1157 !(place->lpfn && place->lpfn <= node->start))
1158 return true;
1159
1160 num_pages -= node->size;
1161 ++node;
1162 }
1163 break;
1164
1165 default:
1166 break;
1167 }
1168
1169 return ttm_bo_eviction_valuable(bo, place);
1170}
1171
1172static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1173 unsigned long offset,
1174 void *buf, int len, int write)
1175{
1176 struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
1177 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1178 struct drm_mm_node *nodes = abo->tbo.mem.mm_node;
1179 uint32_t value = 0;
1180 int ret = 0;
1181 uint64_t pos;
1182 unsigned long flags;
1183
1184 if (bo->mem.mem_type != TTM_PL_VRAM)
1185 return -EIO;
1186
1187 while (offset >= (nodes->size << PAGE_SHIFT)) {
1188 offset -= nodes->size << PAGE_SHIFT;
1189 ++nodes;
1190 }
1191 pos = (nodes->start << PAGE_SHIFT) + offset;
1192
1193 while (len && pos < adev->mc.mc_vram_size) {
1194 uint64_t aligned_pos = pos & ~(uint64_t)3;
1195 uint32_t bytes = 4 - (pos & 3);
1196 uint32_t shift = (pos & 3) * 8;
1197 uint32_t mask = 0xffffffff << shift;
1198
1199 if (len < bytes) {
1200 mask &= 0xffffffff >> (bytes - len) * 8;
1201 bytes = len;
1202 }
1203
1204 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1205 WREG32(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1206 WREG32(mmMM_INDEX_HI, aligned_pos >> 31);
1207 if (!write || mask != 0xffffffff)
1208 value = RREG32(mmMM_DATA);
1209 if (write) {
1210 value &= ~mask;
1211 value |= (*(uint32_t *)buf << shift) & mask;
1212 WREG32(mmMM_DATA, value);
1213 }
1214 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1215 if (!write) {
1216 value = (value & mask) >> shift;
1217 memcpy(buf, &value, bytes);
1218 }
1219
1220 ret += bytes;
1221 buf = (uint8_t *)buf + bytes;
1222 pos += bytes;
1223 len -= bytes;
1224 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1225 ++nodes;
1226 pos = (nodes->start << PAGE_SHIFT);
1227 }
1228 }
1229
1230 return ret;
1231}
1232
1233static struct ttm_bo_driver amdgpu_bo_driver = {
1234 .ttm_tt_create = &amdgpu_ttm_tt_create,
1235 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1236 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1237 .invalidate_caches = &amdgpu_invalidate_caches,
1238 .init_mem_type = &amdgpu_init_mem_type,
1239 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1240 .evict_flags = &amdgpu_evict_flags,
1241 .move = &amdgpu_bo_move,
1242 .verify_access = &amdgpu_verify_access,
1243 .move_notify = &amdgpu_bo_move_notify,
1244 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1245 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1246 .io_mem_free = &amdgpu_ttm_io_mem_free,
1247 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1248 .access_memory = &amdgpu_ttm_access_memory
1249};
1250
1251int amdgpu_ttm_init(struct amdgpu_device *adev)
1252{
1253 uint64_t gtt_size;
1254 int r;
1255 u64 vis_vram_limit;
1256
1257 r = amdgpu_ttm_global_init(adev);
1258 if (r) {
1259 return r;
1260 }
1261
1262 r = ttm_bo_device_init(&adev->mman.bdev,
1263 adev->mman.bo_global_ref.ref.object,
1264 &amdgpu_bo_driver,
1265 adev->ddev->anon_inode->i_mapping,
1266 DRM_FILE_PAGE_OFFSET,
1267 adev->need_dma32);
1268 if (r) {
1269 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1270 return r;
1271 }
1272 adev->mman.initialized = true;
1273 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1274 adev->mc.real_vram_size >> PAGE_SHIFT);
1275 if (r) {
1276 DRM_ERROR("Failed initializing VRAM heap.\n");
1277 return r;
1278 }
1279
1280
1281 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1282 if (amdgpu_vis_vram_limit > 0 &&
1283 vis_vram_limit <= adev->mc.visible_vram_size)
1284 adev->mc.visible_vram_size = vis_vram_limit;
1285
1286
1287 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1288
1289 r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE,
1290 AMDGPU_GEM_DOMAIN_VRAM,
1291 &adev->stolen_vga_memory,
1292 NULL, NULL);
1293 if (r)
1294 return r;
1295 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1296 (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1297
1298 if (amdgpu_gtt_size == -1)
1299 gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1300 adev->mc.mc_vram_size);
1301 else
1302 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1303 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1304 if (r) {
1305 DRM_ERROR("Failed initializing GTT heap.\n");
1306 return r;
1307 }
1308 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1309 (unsigned)(gtt_size / (1024 * 1024)));
1310
1311 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1312 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1313 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1314 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1315 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1316 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1317 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1318 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1319 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1320
1321 if (adev->gds.mem.total_size) {
1322 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1323 adev->gds.mem.total_size >> PAGE_SHIFT);
1324 if (r) {
1325 DRM_ERROR("Failed initializing GDS heap.\n");
1326 return r;
1327 }
1328 }
1329
1330
1331 if (adev->gds.gws.total_size) {
1332 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1333 adev->gds.gws.total_size >> PAGE_SHIFT);
1334 if (r) {
1335 DRM_ERROR("Failed initializing gws heap.\n");
1336 return r;
1337 }
1338 }
1339
1340
1341 if (adev->gds.oa.total_size) {
1342 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1343 adev->gds.oa.total_size >> PAGE_SHIFT);
1344 if (r) {
1345 DRM_ERROR("Failed initializing oa heap.\n");
1346 return r;
1347 }
1348 }
1349
1350 r = amdgpu_ttm_debugfs_init(adev);
1351 if (r) {
1352 DRM_ERROR("Failed to init debugfs\n");
1353 return r;
1354 }
1355 return 0;
1356}
1357
1358void amdgpu_ttm_fini(struct amdgpu_device *adev)
1359{
1360 int r;
1361
1362 if (!adev->mman.initialized)
1363 return;
1364 amdgpu_ttm_debugfs_fini(adev);
1365 if (adev->stolen_vga_memory) {
1366 r = amdgpu_bo_reserve(adev->stolen_vga_memory, true);
1367 if (r == 0) {
1368 amdgpu_bo_unpin(adev->stolen_vga_memory);
1369 amdgpu_bo_unreserve(adev->stolen_vga_memory);
1370 }
1371 amdgpu_bo_unref(&adev->stolen_vga_memory);
1372 }
1373 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1374 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1375 if (adev->gds.mem.total_size)
1376 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1377 if (adev->gds.gws.total_size)
1378 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1379 if (adev->gds.oa.total_size)
1380 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1381 ttm_bo_device_release(&adev->mman.bdev);
1382 amdgpu_gart_fini(adev);
1383 amdgpu_ttm_global_fini(adev);
1384 adev->mman.initialized = false;
1385 DRM_INFO("amdgpu: ttm finalized\n");
1386}
1387
1388
1389
1390void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1391{
1392 struct ttm_mem_type_manager *man;
1393
1394 if (!adev->mman.initialized)
1395 return;
1396
1397 man = &adev->mman.bdev.man[TTM_PL_VRAM];
1398
1399 man->size = size >> PAGE_SHIFT;
1400}
1401
1402int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1403{
1404 struct drm_file *file_priv;
1405 struct amdgpu_device *adev;
1406
1407 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1408 return -EINVAL;
1409
1410 file_priv = filp->private_data;
1411 adev = file_priv->minor->dev->dev_private;
1412 if (adev == NULL)
1413 return -EINVAL;
1414
1415 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1416}
1417
1418static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1419 struct ttm_mem_reg *mem, unsigned num_pages,
1420 uint64_t offset, unsigned window,
1421 struct amdgpu_ring *ring,
1422 uint64_t *addr)
1423{
1424 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1425 struct amdgpu_device *adev = ring->adev;
1426 struct ttm_tt *ttm = bo->ttm;
1427 struct amdgpu_job *job;
1428 unsigned num_dw, num_bytes;
1429 dma_addr_t *dma_address;
1430 struct dma_fence *fence;
1431 uint64_t src_addr, dst_addr;
1432 uint64_t flags;
1433 int r;
1434
1435 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1436 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1437
1438 *addr = adev->mc.gart_start;
1439 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1440 AMDGPU_GPU_PAGE_SIZE;
1441
1442 num_dw = adev->mman.buffer_funcs->copy_num_dw;
1443 while (num_dw & 0x7)
1444 num_dw++;
1445
1446 num_bytes = num_pages * 8;
1447
1448 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1449 if (r)
1450 return r;
1451
1452 src_addr = num_dw * 4;
1453 src_addr += job->ibs[0].gpu_addr;
1454
1455 dst_addr = adev->gart.table_addr;
1456 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1457 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1458 dst_addr, num_bytes);
1459
1460 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1461 WARN_ON(job->ibs[0].length_dw > num_dw);
1462
1463 dma_address = >t->ttm.dma_address[offset >> PAGE_SHIFT];
1464 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1465 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1466 &job->ibs[0].ptr[num_dw]);
1467 if (r)
1468 goto error_free;
1469
1470 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1471 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1472 if (r)
1473 goto error_free;
1474
1475 dma_fence_put(fence);
1476
1477 return r;
1478
1479error_free:
1480 amdgpu_job_free(job);
1481 return r;
1482}
1483
1484int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1485 uint64_t dst_offset, uint32_t byte_count,
1486 struct reservation_object *resv,
1487 struct dma_fence **fence, bool direct_submit,
1488 bool vm_needs_flush)
1489{
1490 struct amdgpu_device *adev = ring->adev;
1491 struct amdgpu_job *job;
1492
1493 uint32_t max_bytes;
1494 unsigned num_loops, num_dw;
1495 unsigned i;
1496 int r;
1497
1498 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1499 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1500 num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1501
1502
1503 while (num_dw & 0x7)
1504 num_dw++;
1505
1506 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1507 if (r)
1508 return r;
1509
1510 job->vm_needs_flush = vm_needs_flush;
1511 if (resv) {
1512 r = amdgpu_sync_resv(adev, &job->sync, resv,
1513 AMDGPU_FENCE_OWNER_UNDEFINED);
1514 if (r) {
1515 DRM_ERROR("sync failed (%d).\n", r);
1516 goto error_free;
1517 }
1518 }
1519
1520 for (i = 0; i < num_loops; i++) {
1521 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1522
1523 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1524 dst_offset, cur_size_in_bytes);
1525
1526 src_offset += cur_size_in_bytes;
1527 dst_offset += cur_size_in_bytes;
1528 byte_count -= cur_size_in_bytes;
1529 }
1530
1531 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1532 WARN_ON(job->ibs[0].length_dw > num_dw);
1533 if (direct_submit) {
1534 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1535 NULL, fence);
1536 job->fence = dma_fence_get(*fence);
1537 if (r)
1538 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1539 amdgpu_job_free(job);
1540 } else {
1541 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1542 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1543 if (r)
1544 goto error_free;
1545 }
1546
1547 return r;
1548
1549error_free:
1550 amdgpu_job_free(job);
1551 return r;
1552}
1553
1554int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1555 uint64_t src_data,
1556 struct reservation_object *resv,
1557 struct dma_fence **fence)
1558{
1559 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1560
1561 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1562 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1563
1564 struct drm_mm_node *mm_node;
1565 unsigned long num_pages;
1566 unsigned int num_loops, num_dw;
1567
1568 struct amdgpu_job *job;
1569 int r;
1570
1571 if (!ring->ready) {
1572 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1573 return -EINVAL;
1574 }
1575
1576 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1577 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1578 if (r)
1579 return r;
1580 }
1581
1582 num_pages = bo->tbo.num_pages;
1583 mm_node = bo->tbo.mem.mm_node;
1584 num_loops = 0;
1585 while (num_pages) {
1586 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1587
1588 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1589 num_pages -= mm_node->size;
1590 ++mm_node;
1591 }
1592
1593
1594 num_dw = num_loops * 10;
1595
1596
1597 num_dw += 64;
1598
1599 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1600 if (r)
1601 return r;
1602
1603 if (resv) {
1604 r = amdgpu_sync_resv(adev, &job->sync, resv,
1605 AMDGPU_FENCE_OWNER_UNDEFINED);
1606 if (r) {
1607 DRM_ERROR("sync failed (%d).\n", r);
1608 goto error_free;
1609 }
1610 }
1611
1612 num_pages = bo->tbo.num_pages;
1613 mm_node = bo->tbo.mem.mm_node;
1614
1615 while (num_pages) {
1616 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1617 uint64_t dst_addr;
1618
1619 WARN_ONCE(byte_count & 0x7, "size should be a multiple of 8");
1620
1621 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
1622 while (byte_count) {
1623 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1624
1625 amdgpu_vm_set_pte_pde(adev, &job->ibs[0],
1626 dst_addr, 0,
1627 cur_size_in_bytes >> 3, 0,
1628 src_data);
1629
1630 dst_addr += cur_size_in_bytes;
1631 byte_count -= cur_size_in_bytes;
1632 }
1633
1634 num_pages -= mm_node->size;
1635 ++mm_node;
1636 }
1637
1638 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1639 WARN_ON(job->ibs[0].length_dw > num_dw);
1640 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1641 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1642 if (r)
1643 goto error_free;
1644
1645 return 0;
1646
1647error_free:
1648 amdgpu_job_free(job);
1649 return r;
1650}
1651
1652#if defined(CONFIG_DEBUG_FS)
1653
1654static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1655{
1656 struct drm_info_node *node = (struct drm_info_node *)m->private;
1657 unsigned ttm_pl = *(int *)node->info_ent->data;
1658 struct drm_device *dev = node->minor->dev;
1659 struct amdgpu_device *adev = dev->dev_private;
1660 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
1661 struct drm_printer p = drm_seq_file_printer(m);
1662
1663 man->func->debug(man, &p);
1664 return 0;
1665}
1666
1667static int ttm_pl_vram = TTM_PL_VRAM;
1668static int ttm_pl_tt = TTM_PL_TT;
1669
1670static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1671 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1672 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1673 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1674#ifdef CONFIG_SWIOTLB
1675 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1676#endif
1677};
1678
1679static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1680 size_t size, loff_t *pos)
1681{
1682 struct amdgpu_device *adev = file_inode(f)->i_private;
1683 ssize_t result = 0;
1684 int r;
1685
1686 if (size & 0x3 || *pos & 0x3)
1687 return -EINVAL;
1688
1689 if (*pos >= adev->mc.mc_vram_size)
1690 return -ENXIO;
1691
1692 while (size) {
1693 unsigned long flags;
1694 uint32_t value;
1695
1696 if (*pos >= adev->mc.mc_vram_size)
1697 return result;
1698
1699 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1700 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1701 WREG32(mmMM_INDEX_HI, *pos >> 31);
1702 value = RREG32(mmMM_DATA);
1703 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1704
1705 r = put_user(value, (uint32_t *)buf);
1706 if (r)
1707 return r;
1708
1709 result += 4;
1710 buf += 4;
1711 *pos += 4;
1712 size -= 4;
1713 }
1714
1715 return result;
1716}
1717
1718static const struct file_operations amdgpu_ttm_vram_fops = {
1719 .owner = THIS_MODULE,
1720 .read = amdgpu_ttm_vram_read,
1721 .llseek = default_llseek
1722};
1723
1724#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1725
1726static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1727 size_t size, loff_t *pos)
1728{
1729 struct amdgpu_device *adev = file_inode(f)->i_private;
1730 ssize_t result = 0;
1731 int r;
1732
1733 while (size) {
1734 loff_t p = *pos / PAGE_SIZE;
1735 unsigned off = *pos & ~PAGE_MASK;
1736 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1737 struct page *page;
1738 void *ptr;
1739
1740 if (p >= adev->gart.num_cpu_pages)
1741 return result;
1742
1743 page = adev->gart.pages[p];
1744 if (page) {
1745 ptr = kmap(page);
1746 ptr += off;
1747
1748 r = copy_to_user(buf, ptr, cur_size);
1749 kunmap(adev->gart.pages[p]);
1750 } else
1751 r = clear_user(buf, cur_size);
1752
1753 if (r)
1754 return -EFAULT;
1755
1756 result += cur_size;
1757 buf += cur_size;
1758 *pos += cur_size;
1759 size -= cur_size;
1760 }
1761
1762 return result;
1763}
1764
1765static const struct file_operations amdgpu_ttm_gtt_fops = {
1766 .owner = THIS_MODULE,
1767 .read = amdgpu_ttm_gtt_read,
1768 .llseek = default_llseek
1769};
1770
1771#endif
1772
1773#endif
1774
1775static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1776{
1777#if defined(CONFIG_DEBUG_FS)
1778 unsigned count;
1779
1780 struct drm_minor *minor = adev->ddev->primary;
1781 struct dentry *ent, *root = minor->debugfs_root;
1782
1783 ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1784 adev, &amdgpu_ttm_vram_fops);
1785 if (IS_ERR(ent))
1786 return PTR_ERR(ent);
1787 i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1788 adev->mman.vram = ent;
1789
1790#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1791 ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1792 adev, &amdgpu_ttm_gtt_fops);
1793 if (IS_ERR(ent))
1794 return PTR_ERR(ent);
1795 i_size_write(ent->d_inode, adev->mc.gart_size);
1796 adev->mman.gtt = ent;
1797
1798#endif
1799 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1800
1801#ifdef CONFIG_SWIOTLB
1802 if (!swiotlb_nr_tbl())
1803 --count;
1804#endif
1805
1806 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1807#else
1808
1809 return 0;
1810#endif
1811}
1812
1813static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1814{
1815#if defined(CONFIG_DEBUG_FS)
1816
1817 debugfs_remove(adev->mman.vram);
1818 adev->mman.vram = NULL;
1819
1820#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1821 debugfs_remove(adev->mman.gtt);
1822 adev->mman.gtt = NULL;
1823#endif
1824
1825#endif
1826}
1827
