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9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_gpio.h>
15#include <linux/pinctrl/pinconf-generic.h>
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/platform_device.h>
19#include <linux/reset.h>
20#include <linux/regulator/consumer.h>
21#include <linux/workqueue.h>
22
23#include <drm/drm_dp_helper.h>
24#include <drm/drm_panel.h>
25
26#include "dpaux.h"
27#include "drm.h"
28#include "trace.h"
29
30static DEFINE_MUTEX(dpaux_lock);
31static LIST_HEAD(dpaux_list);
32
33struct tegra_dpaux {
34 struct drm_dp_aux aux;
35 struct device *dev;
36
37 void __iomem *regs;
38 int irq;
39
40 struct tegra_output *output;
41
42 struct reset_control *rst;
43 struct clk *clk_parent;
44 struct clk *clk;
45
46 struct regulator *vdd;
47
48 struct completion complete;
49 struct work_struct work;
50 struct list_head list;
51
52#ifdef CONFIG_GENERIC_PINCONF
53 struct pinctrl_dev *pinctrl;
54 struct pinctrl_desc desc;
55#endif
56};
57
58static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
59{
60 return container_of(aux, struct tegra_dpaux, aux);
61}
62
63static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
64{
65 return container_of(work, struct tegra_dpaux, work);
66}
67
68static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
69 unsigned int offset)
70{
71 u32 value = readl(dpaux->regs + (offset << 2));
72
73 trace_dpaux_readl(dpaux->dev, offset, value);
74
75 return value;
76}
77
78static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
79 u32 value, unsigned int offset)
80{
81 trace_dpaux_writel(dpaux->dev, offset, value);
82 writel(value, dpaux->regs + (offset << 2));
83}
84
85static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
86 size_t size)
87{
88 size_t i, j;
89
90 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
91 size_t num = min_t(size_t, size - i * 4, 4);
92 u32 value = 0;
93
94 for (j = 0; j < num; j++)
95 value |= buffer[i * 4 + j] << (j * 8);
96
97 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
98 }
99}
100
101static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
102 size_t size)
103{
104 size_t i, j;
105
106 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
107 size_t num = min_t(size_t, size - i * 4, 4);
108 u32 value;
109
110 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
111
112 for (j = 0; j < num; j++)
113 buffer[i * 4 + j] = value >> (j * 8);
114 }
115}
116
117static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
118 struct drm_dp_aux_msg *msg)
119{
120 unsigned long timeout = msecs_to_jiffies(250);
121 struct tegra_dpaux *dpaux = to_dpaux(aux);
122 unsigned long status;
123 ssize_t ret = 0;
124 u32 value;
125
126
127 if (msg->size > 16)
128 return -EINVAL;
129
130
131
132
133
134 if (msg->size < 1) {
135 switch (msg->request & ~DP_AUX_I2C_MOT) {
136 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
137 case DP_AUX_I2C_WRITE:
138 case DP_AUX_I2C_READ:
139 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
140 break;
141
142 default:
143 return -EINVAL;
144 }
145 } else {
146
147 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
148 }
149
150 switch (msg->request & ~DP_AUX_I2C_MOT) {
151 case DP_AUX_I2C_WRITE:
152 if (msg->request & DP_AUX_I2C_MOT)
153 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
154 else
155 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
156
157 break;
158
159 case DP_AUX_I2C_READ:
160 if (msg->request & DP_AUX_I2C_MOT)
161 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
162 else
163 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
164
165 break;
166
167 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
168 if (msg->request & DP_AUX_I2C_MOT)
169 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
170 else
171 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
172
173 break;
174
175 case DP_AUX_NATIVE_WRITE:
176 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
177 break;
178
179 case DP_AUX_NATIVE_READ:
180 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
181 break;
182
183 default:
184 return -EINVAL;
185 }
186
187 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
188 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
189
190 if ((msg->request & DP_AUX_I2C_READ) == 0) {
191 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
192 ret = msg->size;
193 }
194
195
196 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
197 value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
198 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
199
200 status = wait_for_completion_timeout(&dpaux->complete, timeout);
201 if (!status)
202 return -ETIMEDOUT;
203
204
205 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
206 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
207
208 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
209 return -ETIMEDOUT;
210
211 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
212 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
213 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
214 return -EIO;
215
216 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
217 case 0x00:
218 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
219 break;
220
221 case 0x01:
222 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
223 break;
224
225 case 0x02:
226 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
227 break;
228
229 case 0x04:
230 msg->reply = DP_AUX_I2C_REPLY_NACK;
231 break;
232
233 case 0x08:
234 msg->reply = DP_AUX_I2C_REPLY_DEFER;
235 break;
236 }
237
238 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
239 if (msg->request & DP_AUX_I2C_READ) {
240 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
241
242 if (WARN_ON(count != msg->size))
243 count = min_t(size_t, count, msg->size);
244
245 tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
246 ret = count;
247 }
248 }
249
250 return ret;
251}
252
253static void tegra_dpaux_hotplug(struct work_struct *work)
254{
255 struct tegra_dpaux *dpaux = work_to_dpaux(work);
256
257 if (dpaux->output)
258 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
259}
260
261static irqreturn_t tegra_dpaux_irq(int irq, void *data)
262{
263 struct tegra_dpaux *dpaux = data;
264 irqreturn_t ret = IRQ_HANDLED;
265 u32 value;
266
267
268 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
269 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
270
271 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
272 schedule_work(&dpaux->work);
273
274 if (value & DPAUX_INTR_IRQ_EVENT) {
275
276 }
277
278 if (value & DPAUX_INTR_AUX_DONE)
279 complete(&dpaux->complete);
280
281 return ret;
282}
283
284enum tegra_dpaux_functions {
285 DPAUX_PADCTL_FUNC_AUX,
286 DPAUX_PADCTL_FUNC_I2C,
287 DPAUX_PADCTL_FUNC_OFF,
288};
289
290static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
291{
292 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
293
294 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
295
296 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
297}
298
299static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
300{
301 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
302
303 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
304
305 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
306}
307
308static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
309{
310 u32 value;
311
312 switch (function) {
313 case DPAUX_PADCTL_FUNC_AUX:
314 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
315 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
316 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
317 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
318 DPAUX_HYBRID_PADCTL_MODE_AUX;
319 break;
320
321 case DPAUX_PADCTL_FUNC_I2C:
322 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
323 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
324 DPAUX_HYBRID_PADCTL_MODE_I2C;
325 break;
326
327 case DPAUX_PADCTL_FUNC_OFF:
328 tegra_dpaux_pad_power_down(dpaux);
329 return 0;
330
331 default:
332 return -ENOTSUPP;
333 }
334
335 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
336 tegra_dpaux_pad_power_up(dpaux);
337
338 return 0;
339}
340
341#ifdef CONFIG_GENERIC_PINCONF
342static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
343 PINCTRL_PIN(0, "DP_AUX_CHx_P"),
344 PINCTRL_PIN(1, "DP_AUX_CHx_N"),
345};
346
347static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
348
349static const char * const tegra_dpaux_groups[] = {
350 "dpaux-io",
351};
352
353static const char * const tegra_dpaux_functions[] = {
354 "aux",
355 "i2c",
356 "off",
357};
358
359static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
360{
361 return ARRAY_SIZE(tegra_dpaux_groups);
362}
363
364static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
365 unsigned int group)
366{
367 return tegra_dpaux_groups[group];
368}
369
370static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
371 unsigned group, const unsigned **pins,
372 unsigned *num_pins)
373{
374 *pins = tegra_dpaux_pin_numbers;
375 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
376
377 return 0;
378}
379
380static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
381 .get_groups_count = tegra_dpaux_get_groups_count,
382 .get_group_name = tegra_dpaux_get_group_name,
383 .get_group_pins = tegra_dpaux_get_group_pins,
384 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
385 .dt_free_map = pinconf_generic_dt_free_map,
386};
387
388static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
389{
390 return ARRAY_SIZE(tegra_dpaux_functions);
391}
392
393static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
394 unsigned int function)
395{
396 return tegra_dpaux_functions[function];
397}
398
399static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
400 unsigned int function,
401 const char * const **groups,
402 unsigned * const num_groups)
403{
404 *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
405 *groups = tegra_dpaux_groups;
406
407 return 0;
408}
409
410static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
411 unsigned int function, unsigned int group)
412{
413 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
414
415 return tegra_dpaux_pad_config(dpaux, function);
416}
417
418static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
419 .get_functions_count = tegra_dpaux_get_functions_count,
420 .get_function_name = tegra_dpaux_get_function_name,
421 .get_function_groups = tegra_dpaux_get_function_groups,
422 .set_mux = tegra_dpaux_set_mux,
423};
424#endif
425
426static int tegra_dpaux_probe(struct platform_device *pdev)
427{
428 struct tegra_dpaux *dpaux;
429 struct resource *regs;
430 u32 value;
431 int err;
432
433 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
434 if (!dpaux)
435 return -ENOMEM;
436
437 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
438 init_completion(&dpaux->complete);
439 INIT_LIST_HEAD(&dpaux->list);
440 dpaux->dev = &pdev->dev;
441
442 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
444 if (IS_ERR(dpaux->regs))
445 return PTR_ERR(dpaux->regs);
446
447 dpaux->irq = platform_get_irq(pdev, 0);
448 if (dpaux->irq < 0) {
449 dev_err(&pdev->dev, "failed to get IRQ\n");
450 return -ENXIO;
451 }
452
453 if (!pdev->dev.pm_domain) {
454 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
455 if (IS_ERR(dpaux->rst)) {
456 dev_err(&pdev->dev,
457 "failed to get reset control: %ld\n",
458 PTR_ERR(dpaux->rst));
459 return PTR_ERR(dpaux->rst);
460 }
461 }
462
463 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
464 if (IS_ERR(dpaux->clk)) {
465 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
466 PTR_ERR(dpaux->clk));
467 return PTR_ERR(dpaux->clk);
468 }
469
470 err = clk_prepare_enable(dpaux->clk);
471 if (err < 0) {
472 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
473 err);
474 return err;
475 }
476
477 if (dpaux->rst)
478 reset_control_deassert(dpaux->rst);
479
480 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
481 if (IS_ERR(dpaux->clk_parent)) {
482 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
483 PTR_ERR(dpaux->clk_parent));
484 err = PTR_ERR(dpaux->clk_parent);
485 goto assert_reset;
486 }
487
488 err = clk_prepare_enable(dpaux->clk_parent);
489 if (err < 0) {
490 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
491 err);
492 goto assert_reset;
493 }
494
495 err = clk_set_rate(dpaux->clk_parent, 270000000);
496 if (err < 0) {
497 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
498 err);
499 goto disable_parent_clk;
500 }
501
502 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
503 if (IS_ERR(dpaux->vdd)) {
504 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
505 PTR_ERR(dpaux->vdd));
506 err = PTR_ERR(dpaux->vdd);
507 goto disable_parent_clk;
508 }
509
510 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
511 dev_name(dpaux->dev), dpaux);
512 if (err < 0) {
513 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
514 dpaux->irq, err);
515 goto disable_parent_clk;
516 }
517
518 disable_irq(dpaux->irq);
519
520 dpaux->aux.transfer = tegra_dpaux_transfer;
521 dpaux->aux.dev = &pdev->dev;
522
523 err = drm_dp_aux_register(&dpaux->aux);
524 if (err < 0)
525 goto disable_parent_clk;
526
527
528
529
530
531
532
533
534
535 err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C);
536 if (err < 0)
537 return err;
538
539#ifdef CONFIG_GENERIC_PINCONF
540 dpaux->desc.name = dev_name(&pdev->dev);
541 dpaux->desc.pins = tegra_dpaux_pins;
542 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
543 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
544 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
545 dpaux->desc.owner = THIS_MODULE;
546
547 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
548 if (IS_ERR(dpaux->pinctrl)) {
549 dev_err(&pdev->dev, "failed to register pincontrol\n");
550 return PTR_ERR(dpaux->pinctrl);
551 }
552#endif
553
554 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
555 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
556 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
557 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
558
559 mutex_lock(&dpaux_lock);
560 list_add_tail(&dpaux->list, &dpaux_list);
561 mutex_unlock(&dpaux_lock);
562
563 platform_set_drvdata(pdev, dpaux);
564
565 return 0;
566
567disable_parent_clk:
568 clk_disable_unprepare(dpaux->clk_parent);
569assert_reset:
570 if (dpaux->rst)
571 reset_control_assert(dpaux->rst);
572
573 clk_disable_unprepare(dpaux->clk);
574
575 return err;
576}
577
578static int tegra_dpaux_remove(struct platform_device *pdev)
579{
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
581
582
583 tegra_dpaux_pad_power_down(dpaux);
584
585 drm_dp_aux_unregister(&dpaux->aux);
586
587 mutex_lock(&dpaux_lock);
588 list_del(&dpaux->list);
589 mutex_unlock(&dpaux_lock);
590
591 cancel_work_sync(&dpaux->work);
592
593 clk_disable_unprepare(dpaux->clk_parent);
594
595 if (dpaux->rst)
596 reset_control_assert(dpaux->rst);
597
598 clk_disable_unprepare(dpaux->clk);
599
600 return 0;
601}
602
603static const struct of_device_id tegra_dpaux_of_match[] = {
604 { .compatible = "nvidia,tegra210-dpaux", },
605 { .compatible = "nvidia,tegra124-dpaux", },
606 { },
607};
608MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
609
610struct platform_driver tegra_dpaux_driver = {
611 .driver = {
612 .name = "tegra-dpaux",
613 .of_match_table = tegra_dpaux_of_match,
614 },
615 .probe = tegra_dpaux_probe,
616 .remove = tegra_dpaux_remove,
617};
618
619struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
620{
621 struct tegra_dpaux *dpaux;
622
623 mutex_lock(&dpaux_lock);
624
625 list_for_each_entry(dpaux, &dpaux_list, list)
626 if (np == dpaux->dev->of_node) {
627 mutex_unlock(&dpaux_lock);
628 return &dpaux->aux;
629 }
630
631 mutex_unlock(&dpaux_lock);
632
633 return NULL;
634}
635
636int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
637{
638 struct tegra_dpaux *dpaux = to_dpaux(aux);
639 unsigned long timeout;
640 int err;
641
642 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
643 dpaux->output = output;
644
645 err = regulator_enable(dpaux->vdd);
646 if (err < 0)
647 return err;
648
649 timeout = jiffies + msecs_to_jiffies(250);
650
651 while (time_before(jiffies, timeout)) {
652 enum drm_connector_status status;
653
654 status = drm_dp_aux_detect(aux);
655 if (status == connector_status_connected) {
656 enable_irq(dpaux->irq);
657 return 0;
658 }
659
660 usleep_range(1000, 2000);
661 }
662
663 return -ETIMEDOUT;
664}
665
666int drm_dp_aux_detach(struct drm_dp_aux *aux)
667{
668 struct tegra_dpaux *dpaux = to_dpaux(aux);
669 unsigned long timeout;
670 int err;
671
672 disable_irq(dpaux->irq);
673
674 err = regulator_disable(dpaux->vdd);
675 if (err < 0)
676 return err;
677
678 timeout = jiffies + msecs_to_jiffies(250);
679
680 while (time_before(jiffies, timeout)) {
681 enum drm_connector_status status;
682
683 status = drm_dp_aux_detect(aux);
684 if (status == connector_status_disconnected) {
685 dpaux->output = NULL;
686 return 0;
687 }
688
689 usleep_range(1000, 2000);
690 }
691
692 return -ETIMEDOUT;
693}
694
695enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
696{
697 struct tegra_dpaux *dpaux = to_dpaux(aux);
698 u32 value;
699
700 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
701
702 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
703 return connector_status_connected;
704
705 return connector_status_disconnected;
706}
707
708int drm_dp_aux_enable(struct drm_dp_aux *aux)
709{
710 struct tegra_dpaux *dpaux = to_dpaux(aux);
711
712 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
713}
714
715int drm_dp_aux_disable(struct drm_dp_aux *aux)
716{
717 struct tegra_dpaux *dpaux = to_dpaux(aux);
718
719 tegra_dpaux_pad_power_down(dpaux);
720
721 return 0;
722}
723
724int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
725{
726 int err;
727
728 err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
729 encoding);
730 if (err < 0)
731 return err;
732
733 return 0;
734}
735
736int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
737 u8 pattern)
738{
739 u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
740 u8 status[DP_LINK_STATUS_SIZE], values[4];
741 unsigned int i;
742 int err;
743
744 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
745 if (err < 0)
746 return err;
747
748 if (tp == DP_TRAINING_PATTERN_DISABLE)
749 return 0;
750
751 for (i = 0; i < link->num_lanes; i++)
752 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
753 DP_TRAIN_PRE_EMPH_LEVEL_0 |
754 DP_TRAIN_MAX_SWING_REACHED |
755 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
756
757 err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
758 link->num_lanes);
759 if (err < 0)
760 return err;
761
762 usleep_range(500, 1000);
763
764 err = drm_dp_dpcd_read_link_status(aux, status);
765 if (err < 0)
766 return err;
767
768 switch (tp) {
769 case DP_TRAINING_PATTERN_1:
770 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
771 return -EAGAIN;
772
773 break;
774
775 case DP_TRAINING_PATTERN_2:
776 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
777 return -EAGAIN;
778
779 break;
780
781 default:
782 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
783 return -EINVAL;
784 }
785
786 err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
787 if (err < 0)
788 return err;
789
790 return 0;
791}
792
