linux/drivers/net/ethernet/cavium/liquidio/octeon_device.c
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   1/**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2016 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17 ***********************************************************************/
  18#include <linux/pci.h>
  19#include <linux/netdevice.h>
  20#include <linux/vmalloc.h>
  21#include "liquidio_common.h"
  22#include "octeon_droq.h"
  23#include "octeon_iq.h"
  24#include "response_manager.h"
  25#include "octeon_device.h"
  26#include "octeon_main.h"
  27#include "octeon_network.h"
  28#include "cn66xx_regs.h"
  29#include "cn66xx_device.h"
  30#include "cn23xx_pf_device.h"
  31#include "cn23xx_vf_device.h"
  32
  33/** Default configuration
  34 *  for CN66XX OCTEON Models.
  35 */
  36static struct octeon_config default_cn66xx_conf = {
  37        .card_type                              = LIO_210SV,
  38        .card_name                              = LIO_210SV_NAME,
  39
  40        /** IQ attributes */
  41        .iq                                     = {
  42                .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
  43                .pending_list_size              =
  44                        (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
  45                .instr_type                     = OCTEON_64BYTE_INSTR,
  46                .db_min                         = CN6XXX_DB_MIN,
  47                .db_timeout                     = CN6XXX_DB_TIMEOUT,
  48        }
  49        ,
  50
  51        /** OQ attributes */
  52        .oq                                     = {
  53                .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
  54                .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
  55                .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
  56                .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
  57                .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
  58        }
  59        ,
  60
  61        .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_66XX,
  62        .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
  63        .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
  64        .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
  65
  66        /* For ethernet interface 0:  Port cfg Attributes */
  67        .nic_if_cfg[0] = {
  68                /* Max Txqs: Half for each of the two ports :max_iq/2 */
  69                .max_txqs                       = MAX_TXQS_PER_INTF,
  70
  71                /* Actual configured value. Range could be: 1...max_txqs */
  72                .num_txqs                       = DEF_TXQS_PER_INTF,
  73
  74                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
  75                .max_rxqs                       = MAX_RXQS_PER_INTF,
  76
  77                /* Actual configured value. Range could be: 1...max_rxqs */
  78                .num_rxqs                       = DEF_RXQS_PER_INTF,
  79
  80                /* Num of desc for rx rings */
  81                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
  82
  83                /* Num of desc for tx rings */
  84                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
  85
  86                /* SKB size, We need not change buf size even for Jumbo frames.
  87                 * Octeon can send jumbo frames in 4 consecutive descriptors,
  88                 */
  89                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
  90
  91                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
  92
  93                .gmx_port_id                    = 0,
  94        },
  95
  96        .nic_if_cfg[1] = {
  97                /* Max Txqs: Half for each of the two ports :max_iq/2 */
  98                .max_txqs                       = MAX_TXQS_PER_INTF,
  99
 100                /* Actual configured value. Range could be: 1...max_txqs */
 101                .num_txqs                       = DEF_TXQS_PER_INTF,
 102
 103                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 104                .max_rxqs                       = MAX_RXQS_PER_INTF,
 105
 106                /* Actual configured value. Range could be: 1...max_rxqs */
 107                .num_rxqs                       = DEF_RXQS_PER_INTF,
 108
 109                /* Num of desc for rx rings */
 110                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 111
 112                /* Num of desc for tx rings */
 113                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 114
 115                /* SKB size, We need not change buf size even for Jumbo frames.
 116                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 117                 */
 118                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 119
 120                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 121
 122                .gmx_port_id                    = 1,
 123        },
 124
 125        /** Miscellaneous attributes */
 126        .misc                                   = {
 127                /* Host driver link query interval */
 128                .oct_link_query_interval        = 100,
 129
 130                /* Octeon link query interval */
 131                .host_link_query_interval       = 500,
 132
 133                .enable_sli_oq_bp               = 0,
 134
 135                /* Control queue group */
 136                .ctrlq_grp                      = 1,
 137        }
 138        ,
 139};
 140
 141/** Default configuration
 142 *  for CN68XX OCTEON Model.
 143 */
 144
 145static struct octeon_config default_cn68xx_conf = {
 146        .card_type                              = LIO_410NV,
 147        .card_name                              = LIO_410NV_NAME,
 148
 149        /** IQ attributes */
 150        .iq                                     = {
 151                .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 152                .pending_list_size              =
 153                        (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 154                .instr_type                     = OCTEON_64BYTE_INSTR,
 155                .db_min                         = CN6XXX_DB_MIN,
 156                .db_timeout                     = CN6XXX_DB_TIMEOUT,
 157        }
 158        ,
 159
 160        /** OQ attributes */
 161        .oq                                     = {
 162                .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 163                .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 164                .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 165                .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 166                .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 167        }
 168        ,
 169
 170        .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_68XX,
 171        .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
 172        .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
 173        .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
 174
 175        .nic_if_cfg[0] = {
 176                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 177                .max_txqs                       = MAX_TXQS_PER_INTF,
 178
 179                /* Actual configured value. Range could be: 1...max_txqs */
 180                .num_txqs                       = DEF_TXQS_PER_INTF,
 181
 182                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 183                .max_rxqs                       = MAX_RXQS_PER_INTF,
 184
 185                /* Actual configured value. Range could be: 1...max_rxqs */
 186                .num_rxqs                       = DEF_RXQS_PER_INTF,
 187
 188                /* Num of desc for rx rings */
 189                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 190
 191                /* Num of desc for tx rings */
 192                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 193
 194                /* SKB size, We need not change buf size even for Jumbo frames.
 195                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 196                 */
 197                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 198
 199                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 200
 201                .gmx_port_id                    = 0,
 202        },
 203
 204        .nic_if_cfg[1] = {
 205                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 206                .max_txqs                       = MAX_TXQS_PER_INTF,
 207
 208                /* Actual configured value. Range could be: 1...max_txqs */
 209                .num_txqs                       = DEF_TXQS_PER_INTF,
 210
 211                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 212                .max_rxqs                       = MAX_RXQS_PER_INTF,
 213
 214                /* Actual configured value. Range could be: 1...max_rxqs */
 215                .num_rxqs                       = DEF_RXQS_PER_INTF,
 216
 217                /* Num of desc for rx rings */
 218                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 219
 220                /* Num of desc for tx rings */
 221                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 222
 223                /* SKB size, We need not change buf size even for Jumbo frames.
 224                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 225                 */
 226                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 227
 228                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 229
 230                .gmx_port_id                    = 1,
 231        },
 232
 233        .nic_if_cfg[2] = {
 234                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 235                .max_txqs                       = MAX_TXQS_PER_INTF,
 236
 237                /* Actual configured value. Range could be: 1...max_txqs */
 238                .num_txqs                       = DEF_TXQS_PER_INTF,
 239
 240                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 241                .max_rxqs                       = MAX_RXQS_PER_INTF,
 242
 243                /* Actual configured value. Range could be: 1...max_rxqs */
 244                .num_rxqs                       = DEF_RXQS_PER_INTF,
 245
 246                /* Num of desc for rx rings */
 247                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 248
 249                /* Num of desc for tx rings */
 250                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 251
 252                /* SKB size, We need not change buf size even for Jumbo frames.
 253                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 254                 */
 255                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 256
 257                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 258
 259                .gmx_port_id                    = 2,
 260        },
 261
 262        .nic_if_cfg[3] = {
 263                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 264                .max_txqs                       = MAX_TXQS_PER_INTF,
 265
 266                /* Actual configured value. Range could be: 1...max_txqs */
 267                .num_txqs                       = DEF_TXQS_PER_INTF,
 268
 269                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 270                .max_rxqs                       = MAX_RXQS_PER_INTF,
 271
 272                /* Actual configured value. Range could be: 1...max_rxqs */
 273                .num_rxqs                       = DEF_RXQS_PER_INTF,
 274
 275                /* Num of desc for rx rings */
 276                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 277
 278                /* Num of desc for tx rings */
 279                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 280
 281                /* SKB size, We need not change buf size even for Jumbo frames.
 282                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 283                 */
 284                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 285
 286                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 287
 288                .gmx_port_id                    = 3,
 289        },
 290
 291        /** Miscellaneous attributes */
 292        .misc                                   = {
 293                /* Host driver link query interval */
 294                .oct_link_query_interval        = 100,
 295
 296                /* Octeon link query interval */
 297                .host_link_query_interval       = 500,
 298
 299                .enable_sli_oq_bp               = 0,
 300
 301                /* Control queue group */
 302                .ctrlq_grp                      = 1,
 303        }
 304        ,
 305};
 306
 307/** Default configuration
 308 *  for CN68XX OCTEON Model.
 309 */
 310static struct octeon_config default_cn68xx_210nv_conf = {
 311        .card_type                              = LIO_210NV,
 312        .card_name                              = LIO_210NV_NAME,
 313
 314        /** IQ attributes */
 315
 316        .iq                                     = {
 317                .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 318                .pending_list_size              =
 319                        (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 320                .instr_type                     = OCTEON_64BYTE_INSTR,
 321                .db_min                         = CN6XXX_DB_MIN,
 322                .db_timeout                     = CN6XXX_DB_TIMEOUT,
 323        }
 324        ,
 325
 326        /** OQ attributes */
 327        .oq                                     = {
 328                .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 329                .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 330                .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 331                .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 332                .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 333        }
 334        ,
 335
 336        .num_nic_ports                  = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
 337        .num_def_rx_descs               = CN6XXX_MAX_OQ_DESCRIPTORS,
 338        .num_def_tx_descs               = CN6XXX_MAX_IQ_DESCRIPTORS,
 339        .def_rx_buf_size                = CN6XXX_OQ_BUF_SIZE,
 340
 341        .nic_if_cfg[0] = {
 342                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 343                .max_txqs                       = MAX_TXQS_PER_INTF,
 344
 345                /* Actual configured value. Range could be: 1...max_txqs */
 346                .num_txqs                       = DEF_TXQS_PER_INTF,
 347
 348                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 349                .max_rxqs                       = MAX_RXQS_PER_INTF,
 350
 351                /* Actual configured value. Range could be: 1...max_rxqs */
 352                .num_rxqs                       = DEF_RXQS_PER_INTF,
 353
 354                /* Num of desc for rx rings */
 355                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 356
 357                /* Num of desc for tx rings */
 358                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 359
 360                /* SKB size, We need not change buf size even for Jumbo frames.
 361                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 362                 */
 363                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 364
 365                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 366
 367                .gmx_port_id                    = 0,
 368        },
 369
 370        .nic_if_cfg[1] = {
 371                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 372                .max_txqs                       = MAX_TXQS_PER_INTF,
 373
 374                /* Actual configured value. Range could be: 1...max_txqs */
 375                .num_txqs                       = DEF_TXQS_PER_INTF,
 376
 377                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 378                .max_rxqs                       = MAX_RXQS_PER_INTF,
 379
 380                /* Actual configured value. Range could be: 1...max_rxqs */
 381                .num_rxqs                       = DEF_RXQS_PER_INTF,
 382
 383                /* Num of desc for rx rings */
 384                .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 385
 386                /* Num of desc for tx rings */
 387                .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 388
 389                /* SKB size, We need not change buf size even for Jumbo frames.
 390                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 391                 */
 392                .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 393
 394                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 395
 396                .gmx_port_id                    = 1,
 397        },
 398
 399        /** Miscellaneous attributes */
 400        .misc                                   = {
 401                /* Host driver link query interval */
 402                .oct_link_query_interval        = 100,
 403
 404                /* Octeon link query interval */
 405                .host_link_query_interval       = 500,
 406
 407                .enable_sli_oq_bp               = 0,
 408
 409                /* Control queue group */
 410                .ctrlq_grp                      = 1,
 411        }
 412        ,
 413};
 414
 415static struct octeon_config default_cn23xx_conf = {
 416        .card_type                              = LIO_23XX,
 417        .card_name                              = LIO_23XX_NAME,
 418        /** IQ attributes */
 419        .iq = {
 420                .max_iqs                = CN23XX_CFG_IO_QUEUES,
 421                .pending_list_size      = (CN23XX_DEFAULT_IQ_DESCRIPTORS *
 422                                           CN23XX_CFG_IO_QUEUES),
 423                .instr_type             = OCTEON_64BYTE_INSTR,
 424                .db_min                 = CN23XX_DB_MIN,
 425                .db_timeout             = CN23XX_DB_TIMEOUT,
 426                .iq_intr_pkt            = CN23XX_DEF_IQ_INTR_THRESHOLD,
 427        },
 428
 429        /** OQ attributes */
 430        .oq = {
 431                .max_oqs                = CN23XX_CFG_IO_QUEUES,
 432                .pkts_per_intr  = CN23XX_OQ_PKTSPER_INTR,
 433                .refill_threshold       = CN23XX_OQ_REFIL_THRESHOLD,
 434                .oq_intr_pkt    = CN23XX_OQ_INTR_PKT,
 435                .oq_intr_time   = CN23XX_OQ_INTR_TIME,
 436        },
 437
 438        .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_23XX,
 439        .num_def_rx_descs                       = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 440        .num_def_tx_descs                       = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 441        .def_rx_buf_size                        = CN23XX_OQ_BUF_SIZE,
 442
 443        /* For ethernet interface 0:  Port cfg Attributes */
 444        .nic_if_cfg[0] = {
 445                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 446                .max_txqs                       = MAX_TXQS_PER_INTF,
 447
 448                /* Actual configured value. Range could be: 1...max_txqs */
 449                .num_txqs                       = DEF_TXQS_PER_INTF,
 450
 451                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 452                .max_rxqs                       = MAX_RXQS_PER_INTF,
 453
 454                /* Actual configured value. Range could be: 1...max_rxqs */
 455                .num_rxqs                       = DEF_RXQS_PER_INTF,
 456
 457                /* Num of desc for rx rings */
 458                .num_rx_descs                   = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 459
 460                /* Num of desc for tx rings */
 461                .num_tx_descs                   = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 462
 463                /* SKB size, We need not change buf size even for Jumbo frames.
 464                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 465                 */
 466                .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 467
 468                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 469
 470                .gmx_port_id                    = 0,
 471        },
 472
 473        .nic_if_cfg[1] = {
 474                /* Max Txqs: Half for each of the two ports :max_iq/2 */
 475                .max_txqs                       = MAX_TXQS_PER_INTF,
 476
 477                /* Actual configured value. Range could be: 1...max_txqs */
 478                .num_txqs                       = DEF_TXQS_PER_INTF,
 479
 480                /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 481                .max_rxqs                       = MAX_RXQS_PER_INTF,
 482
 483                /* Actual configured value. Range could be: 1...max_rxqs */
 484                .num_rxqs                       = DEF_RXQS_PER_INTF,
 485
 486                /* Num of desc for rx rings */
 487                .num_rx_descs                   = CN23XX_DEFAULT_OQ_DESCRIPTORS,
 488
 489                /* Num of desc for tx rings */
 490                .num_tx_descs                   = CN23XX_DEFAULT_IQ_DESCRIPTORS,
 491
 492                /* SKB size, We need not change buf size even for Jumbo frames.
 493                 * Octeon can send jumbo frames in 4 consecutive descriptors,
 494                 */
 495                .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 496
 497                .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 498
 499                .gmx_port_id                    = 1,
 500        },
 501
 502        .misc                                   = {
 503                /* Host driver link query interval */
 504                .oct_link_query_interval        = 100,
 505
 506                /* Octeon link query interval */
 507                .host_link_query_interval       = 500,
 508
 509                .enable_sli_oq_bp               = 0,
 510
 511                /* Control queue group */
 512                .ctrlq_grp                      = 1,
 513        }
 514};
 515
 516static struct octeon_config_ptr {
 517        u32 conf_type;
 518} oct_conf_info[MAX_OCTEON_DEVICES] = {
 519        {
 520                OCTEON_CONFIG_TYPE_DEFAULT,
 521        }, {
 522                OCTEON_CONFIG_TYPE_DEFAULT,
 523        }, {
 524                OCTEON_CONFIG_TYPE_DEFAULT,
 525        }, {
 526                OCTEON_CONFIG_TYPE_DEFAULT,
 527        },
 528};
 529
 530static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
 531        "BEGIN", "PCI-ENABLE-DONE", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
 532        "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
 533        "DROQ-INIT-DONE", "MBOX-SETUP-DONE", "MSIX-ALLOC-VECTOR-DONE",
 534        "INTR-SET-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
 535        "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
 536        "INVALID"
 537};
 538
 539static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
 540        "BASE", "NIC", "UNKNOWN"};
 541
 542static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
 543static atomic_t adapter_refcounts[MAX_OCTEON_DEVICES];
 544
 545static u32 octeon_device_count;
 546/* locks device array (i.e. octeon_device[]) */
 547static spinlock_t octeon_devices_lock;
 548
 549static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
 550
 551static void oct_set_config_info(int oct_id, int conf_type)
 552{
 553        if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
 554                conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
 555        oct_conf_info[oct_id].conf_type = conf_type;
 556}
 557
 558void octeon_init_device_list(int conf_type)
 559{
 560        int i;
 561
 562        memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
 563        for (i = 0; i <  MAX_OCTEON_DEVICES; i++)
 564                oct_set_config_info(i, conf_type);
 565        spin_lock_init(&octeon_devices_lock);
 566}
 567
 568static void *__retrieve_octeon_config_info(struct octeon_device *oct,
 569                                           u16 card_type)
 570{
 571        u32 oct_id = oct->octeon_id;
 572        void *ret = NULL;
 573
 574        switch (oct_conf_info[oct_id].conf_type) {
 575        case OCTEON_CONFIG_TYPE_DEFAULT:
 576                if (oct->chip_id == OCTEON_CN66XX) {
 577                        ret = &default_cn66xx_conf;
 578                } else if ((oct->chip_id == OCTEON_CN68XX) &&
 579                           (card_type == LIO_210NV)) {
 580                        ret = &default_cn68xx_210nv_conf;
 581                } else if ((oct->chip_id == OCTEON_CN68XX) &&
 582                           (card_type == LIO_410NV)) {
 583                        ret = &default_cn68xx_conf;
 584                } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 585                        ret = &default_cn23xx_conf;
 586                } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
 587                        ret = &default_cn23xx_conf;
 588                }
 589                break;
 590        default:
 591                break;
 592        }
 593        return ret;
 594}
 595
 596static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
 597{
 598        switch (oct->chip_id) {
 599        case OCTEON_CN66XX:
 600        case OCTEON_CN68XX:
 601                return lio_validate_cn6xxx_config_info(oct, conf);
 602        case OCTEON_CN23XX_PF_VID:
 603        case OCTEON_CN23XX_VF_VID:
 604                return 0;
 605        default:
 606                break;
 607        }
 608
 609        return 1;
 610}
 611
 612void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
 613{
 614        void *conf = NULL;
 615
 616        conf = __retrieve_octeon_config_info(oct, card_type);
 617        if (!conf)
 618                return NULL;
 619
 620        if (__verify_octeon_config_info(oct, conf)) {
 621                dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
 622                return NULL;
 623        }
 624
 625        return conf;
 626}
 627
 628char *lio_get_state_string(atomic_t *state_ptr)
 629{
 630        s32 istate = (s32)atomic_read(state_ptr);
 631
 632        if (istate > OCT_DEV_STATES || istate < 0)
 633                return oct_dev_state_str[OCT_DEV_STATE_INVALID];
 634        return oct_dev_state_str[istate];
 635}
 636
 637static char *get_oct_app_string(u32 app_mode)
 638{
 639        if (app_mode <= CVM_DRV_APP_END)
 640                return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
 641        return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
 642}
 643
 644void octeon_free_device_mem(struct octeon_device *oct)
 645{
 646        int i;
 647
 648        for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
 649                if (oct->io_qmask.oq & BIT_ULL(i))
 650                        vfree(oct->droq[i]);
 651        }
 652
 653        for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
 654                if (oct->io_qmask.iq & BIT_ULL(i))
 655                        vfree(oct->instr_queue[i]);
 656        }
 657
 658        i = oct->octeon_id;
 659        vfree(oct);
 660
 661        octeon_device[i] = NULL;
 662        octeon_device_count--;
 663}
 664
 665static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
 666                                                        u32 priv_size)
 667{
 668        struct octeon_device *oct;
 669        u8 *buf = NULL;
 670        u32 octdevsize = 0, configsize = 0, size;
 671
 672        switch (pci_id) {
 673        case OCTEON_CN68XX:
 674        case OCTEON_CN66XX:
 675                configsize = sizeof(struct octeon_cn6xxx);
 676                break;
 677
 678        case OCTEON_CN23XX_PF_VID:
 679                configsize = sizeof(struct octeon_cn23xx_pf);
 680                break;
 681        case OCTEON_CN23XX_VF_VID:
 682                configsize = sizeof(struct octeon_cn23xx_vf);
 683                break;
 684        default:
 685                pr_err("%s: Unknown PCI Device: 0x%x\n",
 686                       __func__,
 687                       pci_id);
 688                return NULL;
 689        }
 690
 691        if (configsize & 0x7)
 692                configsize += (8 - (configsize & 0x7));
 693
 694        octdevsize = sizeof(struct octeon_device);
 695        if (octdevsize & 0x7)
 696                octdevsize += (8 - (octdevsize & 0x7));
 697
 698        if (priv_size & 0x7)
 699                priv_size += (8 - (priv_size & 0x7));
 700
 701        size = octdevsize + priv_size + configsize +
 702                (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
 703
 704        buf = vmalloc(size);
 705        if (!buf)
 706                return NULL;
 707
 708        memset(buf, 0, size);
 709
 710        oct = (struct octeon_device *)buf;
 711        oct->priv = (void *)(buf + octdevsize);
 712        oct->chip = (void *)(buf + octdevsize + priv_size);
 713        oct->dispatch.dlist = (struct octeon_dispatch *)
 714                (buf + octdevsize + priv_size + configsize);
 715
 716        return oct;
 717}
 718
 719struct octeon_device *octeon_allocate_device(u32 pci_id,
 720                                             u32 priv_size)
 721{
 722        u32 oct_idx = 0;
 723        struct octeon_device *oct = NULL;
 724
 725        spin_lock(&octeon_devices_lock);
 726
 727        for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
 728                if (!octeon_device[oct_idx])
 729                        break;
 730
 731        if (oct_idx < MAX_OCTEON_DEVICES) {
 732                oct = octeon_allocate_device_mem(pci_id, priv_size);
 733                if (oct) {
 734                        octeon_device_count++;
 735                        octeon_device[oct_idx] = oct;
 736                }
 737        }
 738
 739        spin_unlock(&octeon_devices_lock);
 740        if (!oct)
 741                return NULL;
 742
 743        spin_lock_init(&oct->pci_win_lock);
 744        spin_lock_init(&oct->mem_access_lock);
 745
 746        oct->octeon_id = oct_idx;
 747        snprintf(oct->device_name, sizeof(oct->device_name),
 748                 "LiquidIO%d", (oct->octeon_id));
 749
 750        return oct;
 751}
 752
 753/** Register a device's bus location at initialization time.
 754 *  @param octeon_dev - pointer to the octeon device structure.
 755 *  @param bus        - PCIe bus #
 756 *  @param dev        - PCIe device #
 757 *  @param func       - PCIe function #
 758 *  @param is_pf      - TRUE for PF, FALSE for VF
 759 *  @return reference count of device's adapter
 760 */
 761int octeon_register_device(struct octeon_device *oct,
 762                           int bus, int dev, int func, int is_pf)
 763{
 764        int idx, refcount;
 765
 766        oct->loc.bus = bus;
 767        oct->loc.dev = dev;
 768        oct->loc.func = func;
 769
 770        oct->adapter_refcount = &adapter_refcounts[oct->octeon_id];
 771        atomic_set(oct->adapter_refcount, 0);
 772
 773        spin_lock(&octeon_devices_lock);
 774        for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) {
 775                if (!octeon_device[idx]) {
 776                        dev_err(&oct->pci_dev->dev,
 777                                "%s: Internal driver error, missing dev",
 778                                __func__);
 779                        spin_unlock(&octeon_devices_lock);
 780                        atomic_inc(oct->adapter_refcount);
 781                        return 1; /* here, refcount is guaranteed to be 1 */
 782                }
 783                /* if another device is at same bus/dev, use its refcounter */
 784                if ((octeon_device[idx]->loc.bus == bus) &&
 785                    (octeon_device[idx]->loc.dev == dev)) {
 786                        oct->adapter_refcount =
 787                                octeon_device[idx]->adapter_refcount;
 788                        break;
 789                }
 790        }
 791        spin_unlock(&octeon_devices_lock);
 792
 793        atomic_inc(oct->adapter_refcount);
 794        refcount = atomic_read(oct->adapter_refcount);
 795
 796        dev_dbg(&oct->pci_dev->dev, "%s: %02x:%02x:%d refcount %u", __func__,
 797                oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
 798
 799        return refcount;
 800}
 801
 802/** Deregister a device at de-initialization time.
 803 *  @param octeon_dev - pointer to the octeon device structure.
 804 *  @return reference count of device's adapter
 805 */
 806int octeon_deregister_device(struct octeon_device *oct)
 807{
 808        int refcount;
 809
 810        atomic_dec(oct->adapter_refcount);
 811        refcount = atomic_read(oct->adapter_refcount);
 812
 813        dev_dbg(&oct->pci_dev->dev, "%s: %04d:%02d:%d refcount %u", __func__,
 814                oct->loc.bus, oct->loc.dev, oct->loc.func, refcount);
 815
 816        return refcount;
 817}
 818
 819int
 820octeon_allocate_ioq_vector(struct octeon_device  *oct)
 821{
 822        int i, num_ioqs = 0;
 823        struct octeon_ioq_vector *ioq_vector;
 824        int cpu_num;
 825        int size;
 826
 827        if (OCTEON_CN23XX_PF(oct))
 828                num_ioqs = oct->sriov_info.num_pf_rings;
 829        else if (OCTEON_CN23XX_VF(oct))
 830                num_ioqs = oct->sriov_info.rings_per_vf;
 831
 832        size = sizeof(struct octeon_ioq_vector) * num_ioqs;
 833
 834        oct->ioq_vector = vmalloc(size);
 835        if (!oct->ioq_vector)
 836                return 1;
 837        memset(oct->ioq_vector, 0, size);
 838        for (i = 0; i < num_ioqs; i++) {
 839                ioq_vector              = &oct->ioq_vector[i];
 840                ioq_vector->oct_dev     = oct;
 841                ioq_vector->iq_index    = i;
 842                ioq_vector->droq_index  = i;
 843                ioq_vector->mbox        = oct->mbox[i];
 844
 845                cpu_num = i % num_online_cpus();
 846                cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask);
 847
 848                if (oct->chip_id == OCTEON_CN23XX_PF_VID)
 849                        ioq_vector->ioq_num     = i + oct->sriov_info.pf_srn;
 850                else
 851                        ioq_vector->ioq_num     = i;
 852        }
 853        return 0;
 854}
 855
 856void
 857octeon_free_ioq_vector(struct octeon_device *oct)
 858{
 859        vfree(oct->ioq_vector);
 860}
 861
 862/* this function is only for setting up the first queue */
 863int octeon_setup_instr_queues(struct octeon_device *oct)
 864{
 865        u32 num_descs = 0;
 866        u32 iq_no = 0;
 867        union oct_txpciq txpciq;
 868        int numa_node = dev_to_node(&oct->pci_dev->dev);
 869
 870        if (OCTEON_CN6XXX(oct))
 871                num_descs =
 872                        CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
 873        else if (OCTEON_CN23XX_PF(oct))
 874                num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 875        else if (OCTEON_CN23XX_VF(oct))
 876                num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf));
 877
 878        oct->num_iqs = 0;
 879
 880        oct->instr_queue[0] = vzalloc_node(sizeof(*oct->instr_queue[0]),
 881                                numa_node);
 882        if (!oct->instr_queue[0])
 883                oct->instr_queue[0] =
 884                        vzalloc(sizeof(struct octeon_instr_queue));
 885        if (!oct->instr_queue[0])
 886                return 1;
 887        memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
 888        oct->instr_queue[0]->q_index = 0;
 889        oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
 890        oct->instr_queue[0]->ifidx = 0;
 891        txpciq.u64 = 0;
 892        txpciq.s.q_no = iq_no;
 893        txpciq.s.pkind = oct->pfvf_hsword.pkind;
 894        txpciq.s.use_qpg = 0;
 895        txpciq.s.qpg = 0;
 896        if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
 897                /* prevent memory leak */
 898                vfree(oct->instr_queue[0]);
 899                oct->instr_queue[0] = NULL;
 900                return 1;
 901        }
 902
 903        oct->num_iqs++;
 904        return 0;
 905}
 906
 907int octeon_setup_output_queues(struct octeon_device *oct)
 908{
 909        u32 num_descs = 0;
 910        u32 desc_size = 0;
 911        u32 oq_no = 0;
 912        int numa_node = dev_to_node(&oct->pci_dev->dev);
 913
 914        if (OCTEON_CN6XXX(oct)) {
 915                num_descs =
 916                        CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx));
 917                desc_size =
 918                        CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx));
 919        } else if (OCTEON_CN23XX_PF(oct)) {
 920                num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 921                desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
 922        } else if (OCTEON_CN23XX_VF(oct)) {
 923                num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf));
 924                desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf));
 925        }
 926        oct->num_oqs = 0;
 927        oct->droq[0] = vzalloc_node(sizeof(*oct->droq[0]), numa_node);
 928        if (!oct->droq[0])
 929                oct->droq[0] = vzalloc(sizeof(*oct->droq[0]));
 930        if (!oct->droq[0])
 931                return 1;
 932
 933        if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
 934                vfree(oct->droq[oq_no]);
 935                oct->droq[oq_no] = NULL;
 936                return 1;
 937        }
 938        oct->num_oqs++;
 939
 940        return 0;
 941}
 942
 943int octeon_set_io_queues_off(struct octeon_device *oct)
 944{
 945        int loop = BUSY_READING_REG_VF_LOOP_COUNT;
 946
 947        if (OCTEON_CN6XXX(oct)) {
 948                octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
 949                octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
 950        } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) {
 951                u32 q_no;
 952
 953                /* IOQs will already be in reset.
 954                 * If RST bit is set, wait for quiet bit to be set.
 955                 * Once quiet bit is set, clear the RST bit.
 956                 */
 957                for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
 958                        u64 reg_val = octeon_read_csr64(
 959                                oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no));
 960
 961                        while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
 962                               !(reg_val &  CN23XX_PKT_INPUT_CTL_QUIET) &&
 963                               loop) {
 964                                reg_val = octeon_read_csr64(
 965                                        oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 966                                loop--;
 967                        }
 968                        if (!loop) {
 969                                dev_err(&oct->pci_dev->dev,
 970                                        "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
 971                                        q_no);
 972                                return -1;
 973                        }
 974
 975                        reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
 976                        octeon_write_csr64(oct,
 977                                           CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
 978                                           reg_val);
 979
 980                        reg_val = octeon_read_csr64(
 981                                        oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
 982                        if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
 983                                dev_err(&oct->pci_dev->dev,
 984                                        "unable to reset qno %u\n", q_no);
 985                                return -1;
 986                        }
 987                }
 988        }
 989        return 0;
 990}
 991
 992void octeon_set_droq_pkt_op(struct octeon_device *oct,
 993                            u32 q_no,
 994                            u32 enable)
 995{
 996        u32 reg_val = 0;
 997
 998        /* Disable the i/p and o/p queues for this Octeon. */
 999        if (OCTEON_CN6XXX(oct)) {
1000                reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
1001
1002                if (enable)
1003                        reg_val = reg_val | (1 << q_no);
1004                else
1005                        reg_val = reg_val & (~(1 << q_no));
1006
1007                octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
1008        }
1009}
1010
1011int octeon_init_dispatch_list(struct octeon_device *oct)
1012{
1013        u32 i;
1014
1015        oct->dispatch.count = 0;
1016
1017        for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1018                oct->dispatch.dlist[i].opcode = 0;
1019                INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
1020        }
1021
1022        for (i = 0; i <= REQTYPE_LAST; i++)
1023                octeon_register_reqtype_free_fn(oct, i, NULL);
1024
1025        spin_lock_init(&oct->dispatch.lock);
1026
1027        return 0;
1028}
1029
1030void octeon_delete_dispatch_list(struct octeon_device *oct)
1031{
1032        u32 i;
1033        struct list_head freelist, *temp, *tmp2;
1034
1035        INIT_LIST_HEAD(&freelist);
1036
1037        spin_lock_bh(&oct->dispatch.lock);
1038
1039        for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
1040                struct list_head *dispatch;
1041
1042                dispatch = &oct->dispatch.dlist[i].list;
1043                while (dispatch->next != dispatch) {
1044                        temp = dispatch->next;
1045                        list_del(temp);
1046                        list_add_tail(temp, &freelist);
1047                }
1048
1049                oct->dispatch.dlist[i].opcode = 0;
1050        }
1051
1052        oct->dispatch.count = 0;
1053
1054        spin_unlock_bh(&oct->dispatch.lock);
1055
1056        list_for_each_safe(temp, tmp2, &freelist) {
1057                list_del(temp);
1058                vfree(temp);
1059        }
1060}
1061
1062octeon_dispatch_fn_t
1063octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
1064                    u16 subcode)
1065{
1066        u32 idx;
1067        struct list_head *dispatch;
1068        octeon_dispatch_fn_t fn = NULL;
1069        u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1070
1071        idx = combined_opcode & OCTEON_OPCODE_MASK;
1072
1073        spin_lock_bh(&octeon_dev->dispatch.lock);
1074
1075        if (octeon_dev->dispatch.count == 0) {
1076                spin_unlock_bh(&octeon_dev->dispatch.lock);
1077                return NULL;
1078        }
1079
1080        if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
1081                spin_unlock_bh(&octeon_dev->dispatch.lock);
1082                return NULL;
1083        }
1084
1085        if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
1086                fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
1087        } else {
1088                list_for_each(dispatch,
1089                              &octeon_dev->dispatch.dlist[idx].list) {
1090                        if (((struct octeon_dispatch *)dispatch)->opcode ==
1091                            combined_opcode) {
1092                                fn = ((struct octeon_dispatch *)
1093                                      dispatch)->dispatch_fn;
1094                                break;
1095                        }
1096                }
1097        }
1098
1099        spin_unlock_bh(&octeon_dev->dispatch.lock);
1100        return fn;
1101}
1102
1103/* octeon_register_dispatch_fn
1104 * Parameters:
1105 *   octeon_id - id of the octeon device.
1106 *   opcode    - opcode for which driver should call the registered function
1107 *   subcode   - subcode for which driver should call the registered function
1108 *   fn        - The function to call when a packet with "opcode" arrives in
1109 *                octeon output queues.
1110 *   fn_arg    - The argument to be passed when calling function "fn".
1111 * Description:
1112 *   Registers a function and its argument to be called when a packet
1113 *   arrives in Octeon output queues with "opcode".
1114 * Returns:
1115 *   Success: 0
1116 *   Failure: 1
1117 * Locks:
1118 *   No locks are held.
1119 */
1120int
1121octeon_register_dispatch_fn(struct octeon_device *oct,
1122                            u16 opcode,
1123                            u16 subcode,
1124                            octeon_dispatch_fn_t fn, void *fn_arg)
1125{
1126        u32 idx;
1127        octeon_dispatch_fn_t pfn;
1128        u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1129
1130        idx = combined_opcode & OCTEON_OPCODE_MASK;
1131
1132        spin_lock_bh(&oct->dispatch.lock);
1133        /* Add dispatch function to first level of lookup table */
1134        if (oct->dispatch.dlist[idx].opcode == 0) {
1135                oct->dispatch.dlist[idx].opcode = combined_opcode;
1136                oct->dispatch.dlist[idx].dispatch_fn = fn;
1137                oct->dispatch.dlist[idx].arg = fn_arg;
1138                oct->dispatch.count++;
1139                spin_unlock_bh(&oct->dispatch.lock);
1140                return 0;
1141        }
1142
1143        spin_unlock_bh(&oct->dispatch.lock);
1144
1145        /* Check if there was a function already registered for this
1146         * opcode/subcode.
1147         */
1148        pfn = octeon_get_dispatch(oct, opcode, subcode);
1149        if (!pfn) {
1150                struct octeon_dispatch *dispatch;
1151
1152                dev_dbg(&oct->pci_dev->dev,
1153                        "Adding opcode to dispatch list linked list\n");
1154                dispatch = (struct octeon_dispatch *)
1155                           vmalloc(sizeof(struct octeon_dispatch));
1156                if (!dispatch) {
1157                        dev_err(&oct->pci_dev->dev,
1158                                "No memory to add dispatch function\n");
1159                        return 1;
1160                }
1161                dispatch->opcode = combined_opcode;
1162                dispatch->dispatch_fn = fn;
1163                dispatch->arg = fn_arg;
1164
1165                /* Add dispatch function to linked list of fn ptrs
1166                 * at the hashed index.
1167                 */
1168                spin_lock_bh(&oct->dispatch.lock);
1169                list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
1170                oct->dispatch.count++;
1171                spin_unlock_bh(&oct->dispatch.lock);
1172
1173        } else {
1174                dev_err(&oct->pci_dev->dev,
1175                        "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1176                        opcode, subcode);
1177                return 1;
1178        }
1179
1180        return 0;
1181}
1182
1183int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1184{
1185        u32 i;
1186        char app_name[16];
1187        struct octeon_device *oct = (struct octeon_device *)buf;
1188        struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1189        struct octeon_core_setup *cs = NULL;
1190        u32 num_nic_ports = 0;
1191
1192        if (OCTEON_CN6XXX(oct))
1193                num_nic_ports =
1194                        CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx));
1195        else if (OCTEON_CN23XX_PF(oct))
1196                num_nic_ports =
1197                        CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf));
1198
1199        if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1200                dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1201                        atomic_read(&oct->status));
1202                goto core_drv_init_err;
1203        }
1204
1205        strncpy(app_name,
1206                get_oct_app_string(
1207                (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1208                sizeof(app_name) - 1);
1209        oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1210        if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1211                oct->fw_info.max_nic_ports =
1212                        (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1213                oct->fw_info.num_gmx_ports =
1214                        (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
1215        }
1216
1217        if (oct->fw_info.max_nic_ports < num_nic_ports) {
1218                dev_err(&oct->pci_dev->dev,
1219                        "Config has more ports than firmware allows (%d > %d).\n",
1220                        num_nic_ports, oct->fw_info.max_nic_ports);
1221                goto core_drv_init_err;
1222        }
1223        oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1224        oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1225        oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1226
1227        oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
1228
1229        for (i = 0; i < oct->num_iqs; i++)
1230                oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
1231
1232        atomic_set(&oct->status, OCT_DEV_CORE_OK);
1233
1234        cs = &core_setup[oct->octeon_id];
1235
1236        if (recv_pkt->buffer_size[0] != (sizeof(*cs) + OCT_DROQ_INFO_SIZE)) {
1237                dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1238                        (u32)sizeof(*cs),
1239                        recv_pkt->buffer_size[0]);
1240        }
1241
1242        memcpy(cs, get_rbd(
1243               recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE, sizeof(*cs));
1244
1245        strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME);
1246        strncpy(oct->boardinfo.serial_number, cs->board_serial_number,
1247                OCT_SERIAL_LEN);
1248
1249        octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1250
1251        oct->boardinfo.major = cs->board_rev_major;
1252        oct->boardinfo.minor = cs->board_rev_minor;
1253
1254        dev_info(&oct->pci_dev->dev,
1255                 "Running %s (%llu Hz)\n",
1256                 app_name, CVM_CAST64(cs->corefreq));
1257
1258core_drv_init_err:
1259        for (i = 0; i < recv_pkt->buffer_count; i++)
1260                recv_buffer_free(recv_pkt->buffer_ptr[i]);
1261        octeon_free_recv_info(recv_info);
1262        return 0;
1263}
1264
1265int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1266
1267{
1268        if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) &&
1269            (oct->io_qmask.iq & BIT_ULL(q_no)))
1270                return oct->instr_queue[q_no]->max_count;
1271
1272        return -1;
1273}
1274
1275int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1276{
1277        if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) &&
1278            (oct->io_qmask.oq & BIT_ULL(q_no)))
1279                return oct->droq[q_no]->max_count;
1280        return -1;
1281}
1282
1283/* Retruns the host firmware handshake OCTEON specific configuration */
1284struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1285{
1286        struct octeon_config *default_oct_conf = NULL;
1287
1288        /* check the OCTEON Device model & return the corresponding octeon
1289         * configuration
1290         */
1291
1292        if (OCTEON_CN6XXX(oct)) {
1293                default_oct_conf =
1294                        (struct octeon_config *)(CHIP_CONF(oct, cn6xxx));
1295        } else if (OCTEON_CN23XX_PF(oct)) {
1296                default_oct_conf = (struct octeon_config *)
1297                        (CHIP_CONF(oct, cn23xx_pf));
1298        } else if (OCTEON_CN23XX_VF(oct)) {
1299                default_oct_conf = (struct octeon_config *)
1300                        (CHIP_CONF(oct, cn23xx_vf));
1301        }
1302        return default_oct_conf;
1303}
1304
1305/* scratch register address is same in all the OCT-II and CN70XX models */
1306#define CNXX_SLI_SCRATCH1   0x3C0
1307
1308/** Get the octeon device pointer.
1309 *  @param octeon_id  - The id for which the octeon device pointer is required.
1310 *  @return Success: Octeon device pointer.
1311 *  @return Failure: NULL.
1312 */
1313struct octeon_device *lio_get_device(u32 octeon_id)
1314{
1315        if (octeon_id >= MAX_OCTEON_DEVICES)
1316                return NULL;
1317        else
1318                return octeon_device[octeon_id];
1319}
1320
1321u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1322{
1323        u64 val64;
1324        unsigned long flags;
1325        u32 val32, addrhi;
1326
1327        spin_lock_irqsave(&oct->pci_win_lock, flags);
1328
1329        /* The windowed read happens when the LSB of the addr is written.
1330         * So write MSB first
1331         */
1332        addrhi = (addr >> 32);
1333        if ((oct->chip_id == OCTEON_CN66XX) ||
1334            (oct->chip_id == OCTEON_CN68XX) ||
1335            (oct->chip_id == OCTEON_CN23XX_PF_VID))
1336                addrhi |= 0x00060000;
1337        writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1338
1339        /* Read back to preserve ordering of writes */
1340        val32 = readl(oct->reg_list.pci_win_rd_addr_hi);
1341
1342        writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1343        val32 = readl(oct->reg_list.pci_win_rd_addr_lo);
1344
1345        val64 = readq(oct->reg_list.pci_win_rd_data);
1346
1347        spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1348
1349        return val64;
1350}
1351
1352void lio_pci_writeq(struct octeon_device *oct,
1353                    u64 val,
1354                    u64 addr)
1355{
1356        u32 val32;
1357        unsigned long flags;
1358
1359        spin_lock_irqsave(&oct->pci_win_lock, flags);
1360
1361        writeq(addr, oct->reg_list.pci_win_wr_addr);
1362
1363        /* The write happens when the LSB is written. So write MSB first. */
1364        writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1365        /* Read the MSB to ensure ordering of writes. */
1366        val32 = readl(oct->reg_list.pci_win_wr_data_hi);
1367
1368        writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1369
1370        spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1371}
1372
1373int octeon_mem_access_ok(struct octeon_device *oct)
1374{
1375        u64 access_okay = 0;
1376        u64 lmc0_reset_ctl;
1377
1378        /* Check to make sure a DDR interface is enabled */
1379        if (OCTEON_CN23XX_PF(oct)) {
1380                lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
1381                access_okay =
1382                        (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
1383        } else {
1384                lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1385                access_okay =
1386                        (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1387        }
1388
1389        return access_okay ? 0 : 1;
1390}
1391
1392int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1393{
1394        int ret = 1;
1395        u32 ms;
1396
1397        if (!timeout)
1398                return ret;
1399
1400        for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1401             ms += HZ / 10) {
1402                ret = octeon_mem_access_ok(oct);
1403
1404                /* wait 100 ms */
1405                if (ret)
1406                        schedule_timeout_uninterruptible(HZ / 10);
1407        }
1408
1409        return ret;
1410}
1411
1412/** Get the octeon id assigned to the octeon device passed as argument.
1413 *  This function is exported to other modules.
1414 *  @param dev - octeon device pointer passed as a void *.
1415 *  @return octeon device id
1416 */
1417int lio_get_device_id(void *dev)
1418{
1419        struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1420        u32 i;
1421
1422        for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1423                if (octeon_device[i] == octeon_dev)
1424                        return octeon_dev->octeon_id;
1425        return -1;
1426}
1427
1428void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq)
1429{
1430        u64 instr_cnt;
1431        u32 pkts_pend;
1432        struct octeon_device *oct = NULL;
1433
1434        /* the whole thing needs to be atomic, ideally */
1435        if (droq) {
1436                pkts_pend = (u32)atomic_read(&droq->pkts_pending);
1437                spin_lock_bh(&droq->lock);
1438                writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg);
1439                droq->pkt_count = pkts_pend;
1440                /* this write needs to be flushed before we release the lock */
1441                mmiowb();
1442                spin_unlock_bh(&droq->lock);
1443                oct = droq->oct_dev;
1444        }
1445        if (iq) {
1446                spin_lock_bh(&iq->lock);
1447                writel(iq->pkt_in_done, iq->inst_cnt_reg);
1448                iq->pkt_in_done = 0;
1449                /* this write needs to be flushed before we release the lock */
1450                mmiowb();
1451                spin_unlock_bh(&iq->lock);
1452                oct = iq->oct_dev;
1453        }
1454        /*write resend. Writing RESEND in SLI_PKTX_CNTS should be enough
1455         *to trigger tx interrupts as well, if they are pending.
1456         */
1457        if (oct && (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))) {
1458                if (droq)
1459                        writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);
1460                /*we race with firmrware here. read and write the IN_DONE_CNTS*/
1461                else if (iq) {
1462                        instr_cnt =  readq(iq->inst_cnt_reg);
1463                        writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |
1464                                CN23XX_INTR_RESEND),
1465                               iq->inst_cnt_reg);
1466                }
1467        }
1468}
1469