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23#ifndef _OCTEON_MAIN_H_
24#define _OCTEON_MAIN_H_
25
26#include <linux/sched/signal.h>
27
28#if BITS_PER_LONG == 32
29#define CVM_CAST64(v) ((long long)(v))
30#elif BITS_PER_LONG == 64
31#define CVM_CAST64(v) ((long long)(long)(v))
32#else
33#error "Unknown system architecture"
34#endif
35
36#define DRV_NAME "LiquidIO"
37
38struct octeon_device_priv {
39
40 struct tasklet_struct droq_tasklet;
41 unsigned long napi_mask;
42};
43
44
45
46
47
48struct octnet_buf_free_info {
49
50 struct lio *lio;
51
52
53 struct sk_buff *skb;
54
55
56 struct octnic_gather *g;
57
58
59 u64 dptr;
60
61
62 struct octeon_soft_command *sc;
63};
64
65
66void octeon_report_sent_bytes_to_bql(void *buf, int reqtype);
67void octeon_update_tx_completion_counters(void *buf, int reqtype,
68 unsigned int *pkts_compl,
69 unsigned int *bytes_compl);
70void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
71 unsigned int bytes_compl);
72void octeon_pf_changed_vf_macaddr(struct octeon_device *oct, u8 *mac);
73
74static inline void octeon_swap_8B_data(u64 *data, u32 blocks)
75{
76 while (blocks) {
77 cpu_to_be64s(data);
78 blocks--;
79 data++;
80 }
81}
82
83
84
85
86
87
88static inline void octeon_unmap_pci_barx(struct octeon_device *oct, int baridx)
89{
90 dev_dbg(&oct->pci_dev->dev, "Freeing PCI mapped regions for Bar%d\n",
91 baridx);
92
93 if (oct->mmio[baridx].done)
94 iounmap(oct->mmio[baridx].hw_addr);
95
96 if (oct->mmio[baridx].start)
97 pci_release_region(oct->pci_dev, baridx * 2);
98}
99
100
101
102
103
104
105
106static inline int octeon_map_pci_barx(struct octeon_device *oct,
107 int baridx, int max_map_len)
108{
109 u32 mapped_len = 0;
110
111 if (pci_request_region(oct->pci_dev, baridx * 2, DRV_NAME)) {
112 dev_err(&oct->pci_dev->dev, "pci_request_region failed for bar %d\n",
113 baridx);
114 return 1;
115 }
116
117 oct->mmio[baridx].start = pci_resource_start(oct->pci_dev, baridx * 2);
118 oct->mmio[baridx].len = pci_resource_len(oct->pci_dev, baridx * 2);
119
120 mapped_len = oct->mmio[baridx].len;
121 if (!mapped_len)
122 goto err_release_region;
123
124 if (max_map_len && (mapped_len > max_map_len))
125 mapped_len = max_map_len;
126
127 oct->mmio[baridx].hw_addr =
128 ioremap(oct->mmio[baridx].start, mapped_len);
129 oct->mmio[baridx].mapped_len = mapped_len;
130
131 dev_dbg(&oct->pci_dev->dev, "BAR%d start: 0x%llx mapped %u of %u bytes\n",
132 baridx, oct->mmio[baridx].start, mapped_len,
133 oct->mmio[baridx].len);
134
135 if (!oct->mmio[baridx].hw_addr) {
136 dev_err(&oct->pci_dev->dev, "error ioremap for bar %d\n",
137 baridx);
138 goto err_release_region;
139 }
140 oct->mmio[baridx].done = 1;
141
142 return 0;
143
144err_release_region:
145 pci_release_region(oct->pci_dev, baridx * 2);
146 return 1;
147}
148
149static inline int
150sleep_cond(wait_queue_head_t *wait_queue, int *condition)
151{
152 int errno = 0;
153 wait_queue_entry_t we;
154
155 init_waitqueue_entry(&we, current);
156 add_wait_queue(wait_queue, &we);
157 while (!(READ_ONCE(*condition))) {
158 set_current_state(TASK_INTERRUPTIBLE);
159 if (signal_pending(current)) {
160 errno = -EINTR;
161 goto out;
162 }
163 schedule();
164 }
165out:
166 set_current_state(TASK_RUNNING);
167 remove_wait_queue(wait_queue, &we);
168 return errno;
169}
170
171
172
173
174
175static inline void
176sleep_timeout_cond(wait_queue_head_t *wait_queue,
177 int *condition,
178 int timeout)
179{
180 wait_queue_entry_t we;
181
182 init_waitqueue_entry(&we, current);
183 add_wait_queue(wait_queue, &we);
184 set_current_state(TASK_INTERRUPTIBLE);
185 if (!(*condition))
186 schedule_timeout(timeout);
187 set_current_state(TASK_RUNNING);
188 remove_wait_queue(wait_queue, &we);
189}
190
191#ifndef ROUNDUP4
192#define ROUNDUP4(val) (((val) + 3) & 0xfffffffc)
193#endif
194
195#ifndef ROUNDUP8
196#define ROUNDUP8(val) (((val) + 7) & 0xfffffff8)
197#endif
198
199#ifndef ROUNDUP16
200#define ROUNDUP16(val) (((val) + 15) & 0xfffffff0)
201#endif
202
203#ifndef ROUNDUP128
204#define ROUNDUP128(val) (((val) + 127) & 0xffffff80)
205#endif
206
207#endif
208