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9#ifndef NICVF_QUEUES_H
10#define NICVF_QUEUES_H
11
12#include <linux/netdevice.h>
13#include <linux/iommu.h>
14#include "q_struct.h"
15
16#define MAX_QUEUE_SET 128
17#define MAX_RCV_QUEUES_PER_QS 8
18#define MAX_RCV_BUF_DESC_RINGS_PER_QS 2
19#define MAX_SND_QUEUES_PER_QS 8
20#define MAX_CMP_QUEUES_PER_QS 8
21
22
23#define NICVF_INTR_ID_CQ 0
24#define NICVF_INTR_ID_SQ 8
25#define NICVF_INTR_ID_RBDR 16
26#define NICVF_INTR_ID_MISC 18
27#define NICVF_INTR_ID_QS_ERR 19
28
29#define for_each_cq_irq(irq) \
30 for (irq = NICVF_INTR_ID_CQ; irq < NICVF_INTR_ID_SQ; irq++)
31#define for_each_sq_irq(irq) \
32 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_RBDR; irq++)
33#define for_each_rbdr_irq(irq) \
34 for (irq = NICVF_INTR_ID_RBDR; irq < NICVF_INTR_ID_MISC; irq++)
35
36#define RBDR_SIZE0 0ULL
37#define RBDR_SIZE1 1ULL
38#define RBDR_SIZE2 2ULL
39#define RBDR_SIZE3 3ULL
40#define RBDR_SIZE4 4ULL
41#define RBDR_SIZE5 5ULL
42#define RBDR_SIZE6 6ULL
43
44#define SND_QUEUE_SIZE0 0ULL
45#define SND_QUEUE_SIZE1 1ULL
46#define SND_QUEUE_SIZE2 2ULL
47#define SND_QUEUE_SIZE3 3ULL
48#define SND_QUEUE_SIZE4 4ULL
49#define SND_QUEUE_SIZE5 5ULL
50#define SND_QUEUE_SIZE6 6ULL
51
52#define CMP_QUEUE_SIZE0 0ULL
53#define CMP_QUEUE_SIZE1 1ULL
54#define CMP_QUEUE_SIZE2 2ULL
55#define CMP_QUEUE_SIZE3 3ULL
56#define CMP_QUEUE_SIZE4 4ULL
57#define CMP_QUEUE_SIZE5 5ULL
58#define CMP_QUEUE_SIZE6 6ULL
59
60
61#define DEFAULT_RBDR_CNT 1
62
63#define SND_QSIZE SND_QUEUE_SIZE0
64#define SND_QUEUE_LEN (1ULL << (SND_QSIZE + 10))
65#define MIN_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE0 + 10))
66#define MAX_SND_QUEUE_LEN (1ULL << (SND_QUEUE_SIZE6 + 10))
67#define SND_QUEUE_THRESH 2ULL
68#define MIN_SQ_DESC_PER_PKT_XMIT 2
69
70#define MAX_CQE_PER_PKT_XMIT 1
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74
75#define CMP_QSIZE CMP_QUEUE_SIZE0
76#define CMP_QUEUE_LEN (1ULL << (CMP_QSIZE + 10))
77#define MIN_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE0 + 10))
78#define MAX_CMP_QUEUE_LEN (1ULL << (CMP_QUEUE_SIZE6 + 10))
79#define CMP_QUEUE_CQE_THRESH (NAPI_POLL_WEIGHT / 2)
80#define CMP_QUEUE_TIMER_THRESH 80
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84
85#define CMP_QUEUE_PIPELINE_RSVD 544
86
87#define RBDR_SIZE RBDR_SIZE0
88#define RCV_BUF_COUNT (1ULL << (RBDR_SIZE + 13))
89#define MAX_RCV_BUF_COUNT (1ULL << (RBDR_SIZE6 + 13))
90#define RBDR_THRESH (RCV_BUF_COUNT / 2)
91#define DMA_BUFFER_LEN 1536
92#define RCV_FRAG_LEN (SKB_DATA_ALIGN(DMA_BUFFER_LEN + NET_SKB_PAD) + \
93 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
94
95#define MAX_CQES_FOR_TX ((SND_QUEUE_LEN / MIN_SQ_DESC_PER_PKT_XMIT) * \
96 MAX_CQE_PER_PKT_XMIT)
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104
105#define RQ_PASS_CQ_LVL 192ULL
106#define RQ_DROP_CQ_LVL 184ULL
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114
115#define RQ_PASS_RBDR_LVL 8ULL
116#define RQ_DROP_RBDR_LVL 0ULL
117
118
119#define SND_QUEUE_DESC_SIZE 16
120#define CMP_QUEUE_DESC_SIZE 512
121
122
123#define NICVF_RCV_BUF_ALIGN 7
124#define NICVF_RCV_BUF_ALIGN_BYTES (1ULL << NICVF_RCV_BUF_ALIGN)
125#define NICVF_CQ_BASE_ALIGN_BYTES 512
126#define NICVF_SQ_BASE_ALIGN_BYTES 128
127
128#define NICVF_ALIGNED_ADDR(ADDR, ALIGN_BYTES) ALIGN(ADDR, ALIGN_BYTES)
129
130
131#define NICVF_SQ_EN BIT_ULL(19)
132
133
134#define NICVF_CQ_RESET BIT_ULL(41)
135#define NICVF_SQ_RESET BIT_ULL(17)
136#define NICVF_RBDR_RESET BIT_ULL(43)
137
138enum CQ_RX_ERRLVL_E {
139 CQ_ERRLVL_MAC,
140 CQ_ERRLVL_L2,
141 CQ_ERRLVL_L3,
142 CQ_ERRLVL_L4,
143};
144
145enum CQ_RX_ERROP_E {
146 CQ_RX_ERROP_RE_NONE = 0x0,
147 CQ_RX_ERROP_RE_PARTIAL = 0x1,
148 CQ_RX_ERROP_RE_JABBER = 0x2,
149 CQ_RX_ERROP_RE_FCS = 0x7,
150 CQ_RX_ERROP_RE_TERMINATE = 0x9,
151 CQ_RX_ERROP_RE_RX_CTL = 0xb,
152 CQ_RX_ERROP_PREL2_ERR = 0x1f,
153 CQ_RX_ERROP_L2_FRAGMENT = 0x20,
154 CQ_RX_ERROP_L2_OVERRUN = 0x21,
155 CQ_RX_ERROP_L2_PFCS = 0x22,
156 CQ_RX_ERROP_L2_PUNY = 0x23,
157 CQ_RX_ERROP_L2_MAL = 0x24,
158 CQ_RX_ERROP_L2_OVERSIZE = 0x25,
159 CQ_RX_ERROP_L2_UNDERSIZE = 0x26,
160 CQ_RX_ERROP_L2_LENMISM = 0x27,
161 CQ_RX_ERROP_L2_PCLP = 0x28,
162 CQ_RX_ERROP_IP_NOT = 0x41,
163 CQ_RX_ERROP_IP_CSUM_ERR = 0x42,
164 CQ_RX_ERROP_IP_MAL = 0x43,
165 CQ_RX_ERROP_IP_MALD = 0x44,
166 CQ_RX_ERROP_IP_HOP = 0x45,
167 CQ_RX_ERROP_L3_ICRC = 0x46,
168 CQ_RX_ERROP_L3_PCLP = 0x47,
169 CQ_RX_ERROP_L4_MAL = 0x61,
170 CQ_RX_ERROP_L4_CHK = 0x62,
171 CQ_RX_ERROP_UDP_LEN = 0x63,
172 CQ_RX_ERROP_L4_PORT = 0x64,
173 CQ_RX_ERROP_TCP_FLAG = 0x65,
174 CQ_RX_ERROP_TCP_OFFSET = 0x66,
175 CQ_RX_ERROP_L4_PCLP = 0x67,
176 CQ_RX_ERROP_RBDR_TRUNC = 0x70,
177};
178
179enum CQ_TX_ERROP_E {
180 CQ_TX_ERROP_GOOD = 0x0,
181 CQ_TX_ERROP_DESC_FAULT = 0x10,
182 CQ_TX_ERROP_HDR_CONS_ERR = 0x11,
183 CQ_TX_ERROP_SUBDC_ERR = 0x12,
184 CQ_TX_ERROP_MAX_SIZE_VIOL = 0x13,
185 CQ_TX_ERROP_IMM_SIZE_OFLOW = 0x80,
186 CQ_TX_ERROP_DATA_SEQUENCE_ERR = 0x81,
187 CQ_TX_ERROP_MEM_SEQUENCE_ERR = 0x82,
188 CQ_TX_ERROP_LOCK_VIOL = 0x83,
189 CQ_TX_ERROP_DATA_FAULT = 0x84,
190 CQ_TX_ERROP_TSTMP_CONFLICT = 0x85,
191 CQ_TX_ERROP_TSTMP_TIMEOUT = 0x86,
192 CQ_TX_ERROP_MEM_FAULT = 0x87,
193 CQ_TX_ERROP_CK_OVERLAP = 0x88,
194 CQ_TX_ERROP_CK_OFLOW = 0x89,
195 CQ_TX_ERROP_ENUM_LAST = 0x8a,
196};
197
198enum RQ_SQ_STATS {
199 RQ_SQ_STATS_OCTS,
200 RQ_SQ_STATS_PKTS,
201};
202
203struct rx_tx_queue_stats {
204 u64 bytes;
205 u64 pkts;
206} ____cacheline_aligned_in_smp;
207
208struct q_desc_mem {
209 dma_addr_t dma;
210 u64 size;
211 u16 q_len;
212 dma_addr_t phys_base;
213 void *base;
214 void *unalign_base;
215};
216
217struct pgcache {
218 struct page *page;
219 int ref_count;
220 u64 dma_addr;
221};
222
223struct rbdr {
224 bool enable;
225 u32 dma_size;
226 u32 frag_len;
227 u32 thresh;
228 void *desc;
229 u32 head;
230 u32 tail;
231 struct q_desc_mem dmem;
232 bool is_xdp;
233
234
235 int pgidx;
236 int pgcnt;
237 int pgalloc;
238 struct pgcache *pgcache;
239} ____cacheline_aligned_in_smp;
240
241struct rcv_queue {
242 bool enable;
243 struct rbdr *rbdr_start;
244 struct rbdr *rbdr_cont;
245 bool en_tcp_reassembly;
246 u8 cq_qs;
247 u8 cq_idx;
248 u8 cont_rbdr_qs;
249 u8 cont_qs_rbdr_idx;
250 u8 start_rbdr_qs;
251 u8 start_qs_rbdr_idx;
252 u8 caching;
253 struct rx_tx_queue_stats stats;
254} ____cacheline_aligned_in_smp;
255
256struct cmp_queue {
257 bool enable;
258 u16 thresh;
259 spinlock_t lock;
260 void *desc;
261 struct q_desc_mem dmem;
262 int irq;
263} ____cacheline_aligned_in_smp;
264
265struct snd_queue {
266 bool enable;
267 u8 cq_qs;
268 u8 cq_idx;
269 u16 thresh;
270 atomic_t free_cnt;
271 u32 head;
272 u32 tail;
273 u64 *skbuff;
274 void *desc;
275 u64 *xdp_page;
276 u16 xdp_desc_cnt;
277 u16 xdp_free_cnt;
278 bool is_xdp;
279
280
281 char *tso_hdrs;
282 dma_addr_t tso_hdrs_phys;
283
284 cpumask_t affinity_mask;
285 struct q_desc_mem dmem;
286 struct rx_tx_queue_stats stats;
287} ____cacheline_aligned_in_smp;
288
289struct queue_set {
290 bool enable;
291 bool be_en;
292 u8 vnic_id;
293 u8 rq_cnt;
294 u8 cq_cnt;
295 u64 cq_len;
296 u8 sq_cnt;
297 u64 sq_len;
298 u8 rbdr_cnt;
299 u64 rbdr_len;
300 struct rcv_queue rq[MAX_RCV_QUEUES_PER_QS];
301 struct cmp_queue cq[MAX_CMP_QUEUES_PER_QS];
302 struct snd_queue sq[MAX_SND_QUEUES_PER_QS];
303 struct rbdr rbdr[MAX_RCV_BUF_DESC_RINGS_PER_QS];
304} ____cacheline_aligned_in_smp;
305
306#define GET_RBDR_DESC(RING, idx)\
307 (&(((struct rbdr_entry_t *)((RING)->desc))[idx]))
308#define GET_SQ_DESC(RING, idx)\
309 (&(((struct sq_hdr_subdesc *)((RING)->desc))[idx]))
310#define GET_CQ_DESC(RING, idx)\
311 (&(((union cq_desc_t *)((RING)->desc))[idx]))
312
313
314#define CQ_WR_FULL BIT(26)
315#define CQ_WR_DISABLE BIT(25)
316#define CQ_WR_FAULT BIT(24)
317#define CQ_CQE_COUNT (0xFFFF << 0)
318
319#define CQ_ERR_MASK (CQ_WR_FULL | CQ_WR_DISABLE | CQ_WR_FAULT)
320
321static inline u64 nicvf_iova_to_phys(struct nicvf *nic, dma_addr_t dma_addr)
322{
323
324 if (nic->iommu_domain)
325 return iommu_iova_to_phys(nic->iommu_domain, dma_addr);
326 return dma_addr;
327}
328
329void nicvf_unmap_sndq_buffers(struct nicvf *nic, struct snd_queue *sq,
330 int hdr_sqe, u8 subdesc_cnt);
331void nicvf_config_vlan_stripping(struct nicvf *nic,
332 netdev_features_t features);
333int nicvf_set_qset_resources(struct nicvf *nic);
334int nicvf_config_data_transfer(struct nicvf *nic, bool enable);
335void nicvf_qset_config(struct nicvf *nic, bool enable);
336void nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs,
337 int qidx, bool enable);
338
339void nicvf_sq_enable(struct nicvf *nic, struct snd_queue *sq, int qidx);
340void nicvf_sq_disable(struct nicvf *nic, int qidx);
341void nicvf_put_sq_desc(struct snd_queue *sq, int desc_cnt);
342void nicvf_sq_free_used_descs(struct net_device *netdev,
343 struct snd_queue *sq, int qidx);
344int nicvf_sq_append_skb(struct nicvf *nic, struct snd_queue *sq,
345 struct sk_buff *skb, u8 sq_num);
346int nicvf_xdp_sq_append_pkt(struct nicvf *nic, struct snd_queue *sq,
347 u64 bufaddr, u64 dma_addr, u16 len);
348void nicvf_xdp_sq_doorbell(struct nicvf *nic, struct snd_queue *sq, int sq_num);
349
350struct sk_buff *nicvf_get_rcv_skb(struct nicvf *nic,
351 struct cqe_rx_t *cqe_rx, bool xdp);
352void nicvf_rbdr_task(unsigned long data);
353void nicvf_rbdr_work(struct work_struct *work);
354
355void nicvf_enable_intr(struct nicvf *nic, int int_type, int q_idx);
356void nicvf_disable_intr(struct nicvf *nic, int int_type, int q_idx);
357void nicvf_clear_intr(struct nicvf *nic, int int_type, int q_idx);
358int nicvf_is_intr_enabled(struct nicvf *nic, int int_type, int q_idx);
359
360
361void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val);
362u64 nicvf_reg_read(struct nicvf *nic, u64 offset);
363void nicvf_qset_reg_write(struct nicvf *nic, u64 offset, u64 val);
364u64 nicvf_qset_reg_read(struct nicvf *nic, u64 offset);
365void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
366 u64 qidx, u64 val);
367u64 nicvf_queue_reg_read(struct nicvf *nic,
368 u64 offset, u64 qidx);
369
370
371void nicvf_update_rq_stats(struct nicvf *nic, int rq_idx);
372void nicvf_update_sq_stats(struct nicvf *nic, int sq_idx);
373int nicvf_check_cqe_rx_errs(struct nicvf *nic, struct cqe_rx_t *cqe_rx);
374int nicvf_check_cqe_tx_errs(struct nicvf *nic, struct cqe_send_t *cqe_tx);
375#endif
376