1/* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef REG_ADDR_H 34#define REG_ADDR_H 35 36#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 37 0 38 39#define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 40 0xfff << 0) 41 42#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 43 12 44 45#define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 46 0xfff << 12) 47 48#define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 49 24 50 51#define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 52 0xff << 24) 53 54#define CDU_REG_SEGMENT0_PARAMS \ 55 0x580904UL 56#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 57 (0xfff << 0) 58#define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 59 0 60#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 61 (0xff << 16) 62#define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 63 16 64#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 65 (0xff << 24) 66#define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 67 24 68#define CDU_REG_SEGMENT1_PARAMS \ 69 0x580908UL 70#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 71 (0xfff << 0) 72#define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 73 0 74#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 75 (0xff << 16) 76#define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 77 16 78#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 79 (0xff << 24) 80#define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 81 24 82 83#define XSDM_REG_OPERATION_GEN \ 84 0xf80408UL 85#define NIG_REG_RX_BRB_OUT_EN \ 86 0x500e18UL 87#define NIG_REG_STORM_OUT_EN \ 88 0x500e08UL 89#define PSWRQ2_REG_L2P_VALIDATE_VFID \ 90 0x240c50UL 91#define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 92 0x2aae04UL 93#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 94 0x2aa16cUL 95#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 96 0x2aa118UL 97#define PSWHST_REG_ZONE_PERMISSION_TABLE \ 98 0x2a0800UL 99#define BAR0_MAP_REG_MSDM_RAM \ 100 0x1d00000UL 101#define BAR0_MAP_REG_USDM_RAM \ 102 0x1d80000UL 103#define BAR0_MAP_REG_PSDM_RAM \ 104 0x1f00000UL 105#define BAR0_MAP_REG_TSDM_RAM \ 106 0x1c80000UL 107#define BAR0_MAP_REG_XSDM_RAM \ 108 0x1e00000UL 109#define BAR0_MAP_REG_YSDM_RAM \ 110 0x1e80000UL 111#define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 112 0x5011f4UL 113#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ 114 0x1f0164UL 115#define PRS_REG_SEARCH_TCP \ 116 0x1f0400UL 117#define PRS_REG_SEARCH_UDP \ 118 0x1f0404UL 119#define PRS_REG_SEARCH_FCOE \ 120 0x1f0408UL 121#define PRS_REG_SEARCH_ROCE \ 122 0x1f040cUL 123#define PRS_REG_SEARCH_OPENFLOW \ 124 0x1f0434UL 125#define PRS_REG_SEARCH_TAG1 \ 126 0x1f0444UL 127#define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ 128 0x1f0a0cUL 129#define PRS_REG_SEARCH_TCP_FIRST_FRAG \ 130 0x1f0410UL 131#define TM_REG_PF_ENABLE_CONN \ 132 0x2c043cUL 133#define TM_REG_PF_ENABLE_TASK \ 134 0x2c0444UL 135#define TM_REG_PF_SCAN_ACTIVE_CONN \ 136 0x2c04fcUL 137#define TM_REG_PF_SCAN_ACTIVE_TASK \ 138 0x2c0500UL 139#define IGU_REG_LEADING_EDGE_LATCH \ 140 0x18082cUL 141#define IGU_REG_TRAILING_EDGE_LATCH \ 142 0x180830UL 143#define QM_REG_USG_CNT_PF_TX \ 144 0x2f2eacUL 145#define QM_REG_USG_CNT_PF_OTHER \ 146 0x2f2eb0UL 147#define DORQ_REG_PF_DB_ENABLE \ 148 0x100508UL 149#define DORQ_REG_VF_USAGE_CNT \ 150 0x1009c4UL 151#define QM_REG_PF_EN \ 152 0x2f2ea4UL 153#define TCFC_REG_WEAK_ENABLE_VF \ 154 0x2d0704UL 155#define TCFC_REG_STRONG_ENABLE_PF \ 156 0x2d0708UL 157#define TCFC_REG_STRONG_ENABLE_VF \ 158 0x2d070cUL 159#define CCFC_REG_WEAK_ENABLE_VF \ 160 0x2e0704UL 161#define CCFC_REG_STRONG_ENABLE_PF \ 162 0x2e0708UL 163#define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ 164 0x2aa404UL 165#define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ 166 0x2aa408UL 167#define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ 168 0x2aa40cUL 169#define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ 170 0x2aa410UL 171#define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 172 0x2aa138UL 173#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 174 0x2aa174UL 175#define MISC_REG_GEN_PURP_CR0 \ 176 0x008c80UL 177#define MCP_REG_SCRATCH \ 178 0xe20000UL 179#define CNIG_REG_NW_PORT_MODE_BB_B0 \ 180 0x218200UL 181#define MISCS_REG_CHIP_NUM \ 182 0x00976cUL 183#define MISCS_REG_CHIP_REV \ 184 0x009770UL 185#define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 186 0x00971cUL 187#define MISCS_REG_CHIP_TEST_REG \ 188 0x009778UL 189#define MISCS_REG_CHIP_METAL \ 190 0x009774UL 191#define MISCS_REG_FUNCTION_HIDE \ 192 0x0096f0UL 193#define BRB_REG_HEADER_SIZE \ 194 0x340804UL 195#define BTB_REG_HEADER_SIZE \ 196 0xdb0804UL 197#define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 198 0x1c0708UL 199#define CCFC_REG_ACTIVITY_COUNTER \ 200 0x2e8800UL 201#define CCFC_REG_STRONG_ENABLE_VF \ 202 0x2e070cUL 203#define CDU_REG_CID_ADDR_PARAMS \ 204 0x580900UL 205#define DBG_REG_CLIENT_ENABLE \ 206 0x010004UL 207#define DMAE_REG_INIT \ 208 0x00c000UL 209#define DORQ_REG_IFEN \ 210 0x100040UL 211#define DORQ_REG_DB_DROP_REASON \ 212 0x100a2cUL 213#define DORQ_REG_DB_DROP_DETAILS \ 214 0x100a24UL 215#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 216 0x100a1cUL 217#define GRC_REG_TIMEOUT_EN \ 218 0x050404UL 219#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 220 0x050054UL 221#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 222 0x05004cUL 223#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 224 0x050050UL 225#define IGU_REG_BLOCK_CONFIGURATION \ 226 0x180040UL 227#define MCM_REG_INIT \ 228 0x1200000UL 229#define MCP2_REG_DBG_DWORD_ENABLE \ 230 0x052404UL 231#define MISC_REG_PORT_MODE \ 232 0x008c00UL 233#define MISCS_REG_CLK_100G_MODE \ 234 0x009070UL 235#define MSDM_REG_ENABLE_IN1 \ 236 0xfc0004UL 237#define MSEM_REG_ENABLE_IN \ 238 0x1800004UL 239#define NIG_REG_CM_HDR \ 240 0x500840UL 241#define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 242 0x50196cUL 243#define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 244 0x501964UL 245#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL 246#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL 247#define NIG_REG_LLH_FUNC_FILTER_VALUE \ 248 0x501a00UL 249#define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 250 32 251#define NIG_REG_LLH_FUNC_FILTER_EN \ 252 0x501a80UL 253#define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 254 16 255#define NIG_REG_LLH_FUNC_FILTER_MODE \ 256 0x501ac0UL 257#define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 258 16 259#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 260 0x501b00UL 261#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 262 16 263#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 264 0x501b40UL 265#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 266 16 267#define NCSI_REG_CONFIG \ 268 0x040200UL 269#define PBF_REG_INIT \ 270 0xd80000UL 271#define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 272 0xd806c8UL 273#define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 274 0xd806ccUL 275#define PTU_REG_ATC_INIT_ARRAY \ 276 0x560000UL 277#define PCM_REG_INIT \ 278 0x1100000UL 279#define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 280 0x2a9000UL 281#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 282 0x2aa150UL 283#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 284 0x2aa144UL 285#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 286 0x2aa148UL 287#define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 288 0x2aa14cUL 289#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 290 0x2aa154UL 291#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 292 0x2aa158UL 293#define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 294 0x2aa15cUL 295#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 296 0x2aa160UL 297#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 298 0x2aa164UL 299#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 300 0x2aa54cUL 301#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 302 0x2aa544UL 303#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 304 0x2aa548UL 305#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 306 0x2aae74UL 307#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 308 0x2aae78UL 309#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 310 0x2aae7cUL 311#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 312 0x2aae80UL 313#define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 314 0x2aa3bcUL 315#define PRM_REG_DISABLE_PRM \ 316 0x230000UL 317#define PRS_REG_SOFT_RST \ 318 0x1f0000UL 319#define PRS_REG_MSG_INFO \ 320 0x1f0a1cUL 321#define PRS_REG_ROCE_DEST_QP_MAX_PF \ 322 0x1f0430UL 323#define PRS_REG_USE_LIGHT_L2 \ 324 0x1f096cUL 325#define PSDM_REG_ENABLE_IN1 \ 326 0xfa0004UL 327#define PSEM_REG_ENABLE_IN \ 328 0x1600004UL 329#define PSWRQ_REG_DBG_SELECT \ 330 0x280020UL 331#define PSWRQ2_REG_CDUT_P_SIZE \ 332 0x24000cUL 333#define PSWRQ2_REG_ILT_MEMORY \ 334 0x260000UL 335#define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 336 0x2a0040UL 337#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 338 0x29e050UL 339#define PSWHST_REG_INCORRECT_ACCESS_VALID \ 340 0x2a0070UL 341#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 342 0x2a0074UL 343#define PSWHST_REG_INCORRECT_ACCESS_DATA \ 344 0x2a0068UL 345#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 346 0x2a006cUL 347#define PSWRD_REG_DBG_SELECT \ 348 0x29c040UL 349#define PSWRD2_REG_CONF11 \ 350 0x29d064UL 351#define PSWWR_REG_USDM_FULL_TH \ 352 0x29a040UL 353#define PSWWR2_REG_CDU_FULL_TH2 \ 354 0x29b040UL 355#define QM_REG_MAXPQSIZE_0 \ 356 0x2f0434UL 357#define RSS_REG_RSS_INIT_EN \ 358 0x238804UL 359#define RDIF_REG_STOP_ON_ERROR \ 360 0x300040UL 361#define RDIF_REG_DEBUG_ERROR_INFO \ 362 0x300400UL 363#define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ 364 64 365#define SRC_REG_SOFT_RST \ 366 0x23874cUL 367#define TCFC_REG_ACTIVITY_COUNTER \ 368 0x2d8800UL 369#define TCM_REG_INIT \ 370 0x1180000UL 371#define TM_REG_PXP_READ_DATA_FIFO_INIT \ 372 0x2c0014UL 373#define TSDM_REG_ENABLE_IN1 \ 374 0xfb0004UL 375#define TSEM_REG_ENABLE_IN \ 376 0x1700004UL 377#define TDIF_REG_STOP_ON_ERROR \ 378 0x310040UL 379#define TDIF_REG_DEBUG_ERROR_INFO \ 380 0x310400UL 381#define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ 382 64 383#define UCM_REG_INIT \ 384 0x1280000UL 385#define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 386 0x051004UL 387#define USDM_REG_ENABLE_IN1 \ 388 0xfd0004UL 389#define USEM_REG_ENABLE_IN \ 390 0x1900004UL 391#define XCM_REG_INIT \ 392 0x1000000UL 393#define XSDM_REG_ENABLE_IN1 \ 394 0xf80004UL 395#define XSEM_REG_ENABLE_IN \ 396 0x1400004UL 397#define YCM_REG_INIT \ 398 0x1080000UL 399#define YSDM_REG_ENABLE_IN1 \ 400 0xf90004UL 401#define YSEM_REG_ENABLE_IN \ 402 0x1500004UL 403#define XYLD_REG_SCBD_STRICT_PRIO \ 404 0x4c0000UL 405#define TMLD_REG_SCBD_STRICT_PRIO \ 406 0x4d0000UL 407#define MULD_REG_SCBD_STRICT_PRIO \ 408 0x4e0000UL 409#define YULD_REG_SCBD_STRICT_PRIO \ 410 0x4c8000UL 411#define MISC_REG_SHARED_MEM_ADDR \ 412 0x008c20UL 413#define DMAE_REG_GO_C0 \ 414 0x00c048UL 415#define DMAE_REG_GO_C1 \ 416 0x00c04cUL 417#define DMAE_REG_GO_C2 \ 418 0x00c050UL 419#define DMAE_REG_GO_C3 \ 420 0x00c054UL 421#define DMAE_REG_GO_C4 \ 422 0x00c058UL 423#define DMAE_REG_GO_C5 \ 424 0x00c05cUL 425#define DMAE_REG_GO_C6 \ 426 0x00c060UL 427#define DMAE_REG_GO_C7 \ 428 0x00c064UL 429#define DMAE_REG_GO_C8 \ 430 0x00c068UL 431#define DMAE_REG_GO_C9 \ 432 0x00c06cUL 433#define DMAE_REG_GO_C10 \ 434 0x00c070UL 435#define DMAE_REG_GO_C11 \ 436 0x00c074UL 437#define DMAE_REG_GO_C12 \ 438 0x00c078UL 439#define DMAE_REG_GO_C13 \ 440 0x00c07cUL 441#define DMAE_REG_GO_C14 \ 442 0x00c080UL 443#define DMAE_REG_GO_C15 \ 444 0x00c084UL 445#define DMAE_REG_GO_C16 \ 446 0x00c088UL 447#define DMAE_REG_GO_C17 \ 448 0x00c08cUL 449#define DMAE_REG_GO_C18 \ 450 0x00c090UL 451#define DMAE_REG_GO_C19 \ 452 0x00c094UL 453#define DMAE_REG_GO_C20 \ 454 0x00c098UL 455#define DMAE_REG_GO_C21 \ 456 0x00c09cUL 457#define DMAE_REG_GO_C22 \ 458 0x00c0a0UL 459#define DMAE_REG_GO_C23 \ 460 0x00c0a4UL 461#define DMAE_REG_GO_C24 \ 462 0x00c0a8UL 463#define DMAE_REG_GO_C25 \ 464 0x00c0acUL 465#define DMAE_REG_GO_C26 \ 466 0x00c0b0UL 467#define DMAE_REG_GO_C27 \ 468 0x00c0b4UL 469#define DMAE_REG_GO_C28 \ 470 0x00c0b8UL 471#define DMAE_REG_GO_C29 \ 472 0x00c0bcUL 473#define DMAE_REG_GO_C30 \ 474 0x00c0c0UL 475#define DMAE_REG_GO_C31 \ 476 0x00c0c4UL 477#define DMAE_REG_CMD_MEM \ 478 0x00c800UL 479#define QM_REG_MAXPQSIZETXSEL_0 \ 480 0x2f0440UL 481#define QM_REG_SDMCMDREADY \ 482 0x2f1e10UL 483#define QM_REG_SDMCMDADDR \ 484 0x2f1e04UL 485#define QM_REG_SDMCMDDATALSB \ 486 0x2f1e08UL 487#define QM_REG_SDMCMDDATAMSB \ 488 0x2f1e0cUL 489#define QM_REG_SDMCMDGO \ 490 0x2f1e14UL 491#define QM_REG_RLPFCRD \ 492 0x2f4d80UL 493#define QM_REG_RLPFINCVAL \ 494 0x2f4c80UL 495#define QM_REG_RLGLBLCRD \ 496 0x2f4400UL 497#define QM_REG_RLGLBLINCVAL \ 498 0x2f3400UL 499#define IGU_REG_ATTENTION_ENABLE \ 500 0x18083cUL 501#define IGU_REG_ATTN_MSG_ADDR_L \ 502 0x180820UL 503#define IGU_REG_ATTN_MSG_ADDR_H \ 504 0x180824UL 505#define MISC_REG_AEU_GENERAL_ATTN_0 \ 506 0x008400UL 507#define CAU_REG_SB_ADDR_MEMORY \ 508 0x1c8000UL 509#define CAU_REG_SB_VAR_MEMORY \ 510 0x1c6000UL 511#define CAU_REG_PI_MEMORY \ 512 0x1d0000UL 513#define IGU_REG_PF_CONFIGURATION \ 514 0x180800UL 515#define IGU_REG_VF_CONFIGURATION \ 516 0x180804UL 517#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 518 0x00849cUL 519#define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 520 0x0087b4UL 521#define MISC_REG_AEU_MASK_ATTN_IGU \ 522 0x008494UL 523#define IGU_REG_CLEANUP_STATUS_0 \ 524 0x180980UL 525#define IGU_REG_CLEANUP_STATUS_1 \ 526 0x180a00UL 527#define IGU_REG_CLEANUP_STATUS_2 \ 528 0x180a80UL 529#define IGU_REG_CLEANUP_STATUS_3 \ 530 0x180b00UL 531#define IGU_REG_CLEANUP_STATUS_4 \ 532 0x180b80UL 533#define IGU_REG_COMMAND_REG_32LSB_DATA \ 534 0x180840UL 535#define IGU_REG_COMMAND_REG_CTRL \ 536 0x180848UL 537#define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 538 0x1 << 1) 539#define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 540 0x1 << 0) 541#define IGU_REG_MAPPING_MEMORY \ 542 0x184000UL 543#define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 544 0x180408UL 545#define IGU_REG_WRITE_DONE_PENDING \ 546 0x180900UL 547#define MISCS_REG_GENERIC_POR_0 \ 548 0x0096d4UL 549#define MCP_REG_NVM_CFG4 \ 550 0xe0642cUL 551#define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 552 0x7 << 0) 553#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 554 0 555#define MCP_REG_CPU_STATE \ 556 0xe05004UL 557#define MCP_REG_CPU_EVENT_MASK \ 558 0xe05008UL 559#define PGLUE_B_REG_PF_BAR0_SIZE \ 560 0x2aae60UL 561#define PGLUE_B_REG_PF_BAR1_SIZE \ 562 0x2aae64UL 563#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL 564#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 565#define PRS_REG_GRE_PROTOCOL 0x1f0734UL 566#define PRS_REG_VXLAN_PORT 0x1f0738UL 567#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 568#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 569 570#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 571#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 572#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 573#define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 574#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 575#define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 576 577#define NIG_REG_VXLAN_CTRL 0x50105cUL 578#define PBF_REG_VXLAN_PORT 0xd80518UL 579#define PBF_REG_NGE_PORT 0xd8051cUL 580#define PRS_REG_NGE_PORT 0x1f086cUL 581#define NIG_REG_NGE_PORT 0x508b38UL 582 583#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 584#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 585#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 586#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 587#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 588 589#define NIG_REG_NGE_IP_ENABLE 0x508b28UL 590#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 591#define NIG_REG_NGE_COMP_VER 0x508b30UL 592#define PBF_REG_NGE_COMP_VER 0xd80524UL 593#define PRS_REG_NGE_COMP_VER 0x1f0878UL 594 595#define QM_REG_WFQPFWEIGHT 0x2f4e80UL 596#define QM_REG_WFQVPWEIGHT 0x2fa000UL 597 598#define PGLCS_REG_DBG_SELECT_K2 \ 599 0x001d14UL 600#define PGLCS_REG_DBG_DWORD_ENABLE_K2 \ 601 0x001d18UL 602#define PGLCS_REG_DBG_SHIFT_K2 \ 603 0x001d1cUL 604#define PGLCS_REG_DBG_FORCE_VALID_K2 \ 605 0x001d20UL 606#define PGLCS_REG_DBG_FORCE_FRAME_K2 \ 607 0x001d24UL 608#define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 609 0x008070UL 610#define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 611 0x008080UL 612#define MISC_REG_RESET_PL_PDA_VAUX \ 613 0x008090UL 614#define MISCS_REG_RESET_PL_UA \ 615 0x009050UL 616#define MISCS_REG_RESET_PL_HV \ 617 0x009060UL 618#define MISCS_REG_RESET_PL_HV_2_K2 \ 619 0x009150UL 620#define DMAE_REG_DBG_SELECT \ 621 0x00c510UL 622#define DMAE_REG_DBG_DWORD_ENABLE \ 623 0x00c514UL 624#define DMAE_REG_DBG_SHIFT \ 625 0x00c518UL 626#define DMAE_REG_DBG_FORCE_VALID \ 627 0x00c51cUL 628#define DMAE_REG_DBG_FORCE_FRAME \ 629 0x00c520UL 630#define NCSI_REG_DBG_SELECT \ 631 0x040474UL 632#define NCSI_REG_DBG_DWORD_ENABLE \ 633 0x040478UL 634#define NCSI_REG_DBG_SHIFT \ 635 0x04047cUL 636#define NCSI_REG_DBG_FORCE_VALID \ 637 0x040480UL 638#define NCSI_REG_DBG_FORCE_FRAME \ 639 0x040484UL 640#define GRC_REG_DBG_SELECT \ 641 0x0500a4UL 642#define GRC_REG_DBG_DWORD_ENABLE \ 643 0x0500a8UL 644#define GRC_REG_DBG_SHIFT \ 645 0x0500acUL 646#define GRC_REG_DBG_FORCE_VALID \ 647 0x0500b0UL 648#define GRC_REG_DBG_FORCE_FRAME \ 649 0x0500b4UL 650#define UMAC_REG_DBG_SELECT_K2 \ 651 0x051094UL 652#define UMAC_REG_DBG_DWORD_ENABLE_K2 \ 653 0x051098UL 654#define UMAC_REG_DBG_SHIFT_K2 \ 655 0x05109cUL 656#define UMAC_REG_DBG_FORCE_VALID_K2 \ 657 0x0510a0UL 658#define UMAC_REG_DBG_FORCE_FRAME_K2 \ 659 0x0510a4UL 660#define MCP2_REG_DBG_SELECT \ 661 0x052400UL 662#define MCP2_REG_DBG_DWORD_ENABLE \ 663 0x052404UL 664#define MCP2_REG_DBG_SHIFT \ 665 0x052408UL 666#define MCP2_REG_DBG_FORCE_VALID \ 667 0x052440UL 668#define MCP2_REG_DBG_FORCE_FRAME \ 669 0x052444UL 670#define PCIE_REG_DBG_SELECT \ 671 0x0547e8UL 672#define PCIE_REG_DBG_DWORD_ENABLE \ 673 0x0547ecUL 674#define PCIE_REG_DBG_SHIFT \ 675 0x0547f0UL 676#define PCIE_REG_DBG_FORCE_VALID \ 677 0x0547f4UL 678#define PCIE_REG_DBG_FORCE_FRAME \ 679 0x0547f8UL 680#define DORQ_REG_DBG_SELECT \ 681 0x100ad0UL 682#define DORQ_REG_DBG_DWORD_ENABLE \ 683 0x100ad4UL 684#define DORQ_REG_DBG_SHIFT \ 685 0x100ad8UL 686#define DORQ_REG_DBG_FORCE_VALID \ 687 0x100adcUL 688#define DORQ_REG_DBG_FORCE_FRAME \ 689 0x100ae0UL 690#define IGU_REG_DBG_SELECT \ 691 0x181578UL 692#define IGU_REG_DBG_DWORD_ENABLE \ 693 0x18157cUL 694#define IGU_REG_DBG_SHIFT \ 695 0x181580UL 696#define IGU_REG_DBG_FORCE_VALID \ 697 0x181584UL 698#define IGU_REG_DBG_FORCE_FRAME \ 699 0x181588UL 700#define CAU_REG_DBG_SELECT \ 701 0x1c0ea8UL 702#define CAU_REG_DBG_DWORD_ENABLE \ 703 0x1c0eacUL 704#define CAU_REG_DBG_SHIFT \ 705 0x1c0eb0UL 706#define CAU_REG_DBG_FORCE_VALID \ 707 0x1c0eb4UL 708#define CAU_REG_DBG_FORCE_FRAME \ 709 0x1c0eb8UL 710#define PRS_REG_DBG_SELECT \ 711 0x1f0b6cUL 712#define PRS_REG_DBG_DWORD_ENABLE \ 713 0x1f0b70UL 714#define PRS_REG_DBG_SHIFT \ 715 0x1f0b74UL 716#define PRS_REG_DBG_FORCE_VALID \ 717 0x1f0ba0UL 718#define PRS_REG_DBG_FORCE_FRAME \ 719 0x1f0ba4UL 720#define CNIG_REG_DBG_SELECT_K2 \ 721 0x218254UL 722#define CNIG_REG_DBG_DWORD_ENABLE_K2 \ 723 0x218258UL 724#define CNIG_REG_DBG_SHIFT_K2 \ 725 0x21825cUL 726#define CNIG_REG_DBG_FORCE_VALID_K2 \ 727 0x218260UL 728#define CNIG_REG_DBG_FORCE_FRAME_K2 \ 729 0x218264UL 730#define PRM_REG_DBG_SELECT \ 731 0x2306a8UL 732#define PRM_REG_DBG_DWORD_ENABLE \ 733 0x2306acUL 734#define PRM_REG_DBG_SHIFT \ 735 0x2306b0UL 736#define PRM_REG_DBG_FORCE_VALID \ 737 0x2306b4UL 738#define PRM_REG_DBG_FORCE_FRAME \ 739 0x2306b8UL 740#define SRC_REG_DBG_SELECT \ 741 0x238700UL 742#define SRC_REG_DBG_DWORD_ENABLE \ 743 0x238704UL 744#define SRC_REG_DBG_SHIFT \ 745 0x238708UL 746#define SRC_REG_DBG_FORCE_VALID \ 747 0x23870cUL 748#define SRC_REG_DBG_FORCE_FRAME \ 749 0x238710UL 750#define RSS_REG_DBG_SELECT \ 751 0x238c4cUL 752#define RSS_REG_DBG_DWORD_ENABLE \ 753 0x238c50UL 754#define RSS_REG_DBG_SHIFT \ 755 0x238c54UL 756#define RSS_REG_DBG_FORCE_VALID \ 757 0x238c58UL 758#define RSS_REG_DBG_FORCE_FRAME \ 759 0x238c5cUL 760#define RPB_REG_DBG_SELECT \ 761 0x23c728UL 762#define RPB_REG_DBG_DWORD_ENABLE \ 763 0x23c72cUL 764#define RPB_REG_DBG_SHIFT \ 765 0x23c730UL 766#define RPB_REG_DBG_FORCE_VALID \ 767 0x23c734UL 768#define RPB_REG_DBG_FORCE_FRAME \ 769 0x23c738UL 770#define PSWRQ2_REG_DBG_SELECT \ 771 0x240100UL 772#define PSWRQ2_REG_DBG_DWORD_ENABLE \ 773 0x240104UL 774#define PSWRQ2_REG_DBG_SHIFT \ 775 0x240108UL 776#define PSWRQ2_REG_DBG_FORCE_VALID \ 777 0x24010cUL 778#define PSWRQ2_REG_DBG_FORCE_FRAME \ 779 0x240110UL 780#define PSWRQ_REG_DBG_SELECT \ 781 0x280020UL 782#define PSWRQ_REG_DBG_DWORD_ENABLE \ 783 0x280024UL 784#define PSWRQ_REG_DBG_SHIFT \ 785 0x280028UL 786#define PSWRQ_REG_DBG_FORCE_VALID \ 787 0x28002cUL 788#define PSWRQ_REG_DBG_FORCE_FRAME \ 789 0x280030UL 790#define PSWWR_REG_DBG_SELECT \ 791 0x29a084UL 792#define PSWWR_REG_DBG_DWORD_ENABLE \ 793 0x29a088UL 794#define PSWWR_REG_DBG_SHIFT \ 795 0x29a08cUL 796#define PSWWR_REG_DBG_FORCE_VALID \ 797 0x29a090UL 798#define PSWWR_REG_DBG_FORCE_FRAME \ 799 0x29a094UL 800#define PSWRD_REG_DBG_SELECT \ 801 0x29c040UL 802#define PSWRD_REG_DBG_DWORD_ENABLE \ 803 0x29c044UL 804#define PSWRD_REG_DBG_SHIFT \ 805 0x29c048UL 806#define PSWRD_REG_DBG_FORCE_VALID \ 807 0x29c04cUL 808#define PSWRD_REG_DBG_FORCE_FRAME \ 809 0x29c050UL 810#define PSWRD2_REG_DBG_SELECT \ 811 0x29d400UL 812#define PSWRD2_REG_DBG_DWORD_ENABLE \ 813 0x29d404UL 814#define PSWRD2_REG_DBG_SHIFT \ 815 0x29d408UL 816#define PSWRD2_REG_DBG_FORCE_VALID \ 817 0x29d40cUL 818#define PSWRD2_REG_DBG_FORCE_FRAME \ 819 0x29d410UL 820#define PSWHST2_REG_DBG_SELECT \ 821 0x29e058UL 822#define PSWHST2_REG_DBG_DWORD_ENABLE \ 823 0x29e05cUL 824#define PSWHST2_REG_DBG_SHIFT \ 825 0x29e060UL 826#define PSWHST2_REG_DBG_FORCE_VALID \ 827 0x29e064UL 828#define PSWHST2_REG_DBG_FORCE_FRAME \ 829 0x29e068UL 830#define PSWHST_REG_DBG_SELECT \ 831 0x2a0100UL 832#define PSWHST_REG_DBG_DWORD_ENABLE \ 833 0x2a0104UL 834#define PSWHST_REG_DBG_SHIFT \ 835 0x2a0108UL 836#define PSWHST_REG_DBG_FORCE_VALID \ 837 0x2a010cUL 838#define PSWHST_REG_DBG_FORCE_FRAME \ 839 0x2a0110UL 840#define PGLUE_B_REG_DBG_SELECT \ 841 0x2a8400UL 842#define PGLUE_B_REG_DBG_DWORD_ENABLE \ 843 0x2a8404UL 844#define PGLUE_B_REG_DBG_SHIFT \ 845 0x2a8408UL 846#define PGLUE_B_REG_DBG_FORCE_VALID \ 847 0x2a840cUL 848#define PGLUE_B_REG_DBG_FORCE_FRAME \ 849 0x2a8410UL 850#define TM_REG_DBG_SELECT \ 851 0x2c07a8UL 852#define TM_REG_DBG_DWORD_ENABLE \ 853 0x2c07acUL 854#define TM_REG_DBG_SHIFT \ 855 0x2c07b0UL 856#define TM_REG_DBG_FORCE_VALID \ 857 0x2c07b4UL 858#define TM_REG_DBG_FORCE_FRAME \ 859 0x2c07b8UL 860#define TCFC_REG_DBG_SELECT \ 861 0x2d0500UL 862#define TCFC_REG_DBG_DWORD_ENABLE \ 863 0x2d0504UL 864#define TCFC_REG_DBG_SHIFT \ 865 0x2d0508UL 866#define TCFC_REG_DBG_FORCE_VALID \ 867 0x2d050cUL 868#define TCFC_REG_DBG_FORCE_FRAME \ 869 0x2d0510UL 870#define CCFC_REG_DBG_SELECT \ 871 0x2e0500UL 872#define CCFC_REG_DBG_DWORD_ENABLE \ 873 0x2e0504UL 874#define CCFC_REG_DBG_SHIFT \ 875 0x2e0508UL 876#define CCFC_REG_DBG_FORCE_VALID \ 877 0x2e050cUL 878#define CCFC_REG_DBG_FORCE_FRAME \ 879 0x2e0510UL 880#define QM_REG_DBG_SELECT \ 881 0x2f2e74UL 882#define QM_REG_DBG_DWORD_ENABLE \ 883 0x2f2e78UL 884#define QM_REG_DBG_SHIFT \ 885 0x2f2e7cUL 886#define QM_REG_DBG_FORCE_VALID \ 887 0x2f2e80UL 888#define QM_REG_DBG_FORCE_FRAME \ 889 0x2f2e84UL 890#define RDIF_REG_DBG_SELECT \ 891 0x300500UL 892#define RDIF_REG_DBG_DWORD_ENABLE \ 893 0x300504UL 894#define RDIF_REG_DBG_SHIFT \ 895 0x300508UL 896#define RDIF_REG_DBG_FORCE_VALID \ 897 0x30050cUL 898#define RDIF_REG_DBG_FORCE_FRAME \ 899 0x300510UL 900#define TDIF_REG_DBG_SELECT \ 901 0x310500UL 902#define TDIF_REG_DBG_DWORD_ENABLE \ 903 0x310504UL 904#define TDIF_REG_DBG_SHIFT \ 905 0x310508UL 906#define TDIF_REG_DBG_FORCE_VALID \ 907 0x31050cUL 908#define TDIF_REG_DBG_FORCE_FRAME \ 909 0x310510UL 910#define BRB_REG_DBG_SELECT \ 911 0x340ed0UL 912#define BRB_REG_DBG_DWORD_ENABLE \ 913 0x340ed4UL 914#define BRB_REG_DBG_SHIFT \ 915 0x340ed8UL 916#define BRB_REG_DBG_FORCE_VALID \ 917 0x340edcUL 918#define BRB_REG_DBG_FORCE_FRAME \ 919 0x340ee0UL 920#define XYLD_REG_DBG_SELECT \ 921 0x4c1600UL 922#define XYLD_REG_DBG_DWORD_ENABLE \ 923 0x4c1604UL 924#define XYLD_REG_DBG_SHIFT \ 925 0x4c1608UL 926#define XYLD_REG_DBG_FORCE_VALID \ 927 0x4c160cUL 928#define XYLD_REG_DBG_FORCE_FRAME \ 929 0x4c1610UL 930#define YULD_REG_DBG_SELECT_BB_K2 \ 931 0x4c9600UL 932#define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \ 933 0x4c9604UL 934#define YULD_REG_DBG_SHIFT_BB_K2 \ 935 0x4c9608UL 936#define YULD_REG_DBG_FORCE_VALID_BB_K2 \ 937 0x4c960cUL 938#define YULD_REG_DBG_FORCE_FRAME_BB_K2 \ 939 0x4c9610UL 940#define TMLD_REG_DBG_SELECT \ 941 0x4d1600UL 942#define TMLD_REG_DBG_DWORD_ENABLE \ 943 0x4d1604UL 944#define TMLD_REG_DBG_SHIFT \ 945 0x4d1608UL 946#define TMLD_REG_DBG_FORCE_VALID \ 947 0x4d160cUL 948#define TMLD_REG_DBG_FORCE_FRAME \ 949 0x4d1610UL 950#define MULD_REG_DBG_SELECT \ 951 0x4e1600UL 952#define MULD_REG_DBG_DWORD_ENABLE \ 953 0x4e1604UL 954#define MULD_REG_DBG_SHIFT \ 955 0x4e1608UL 956#define MULD_REG_DBG_FORCE_VALID \ 957 0x4e160cUL 958#define MULD_REG_DBG_FORCE_FRAME \ 959 0x4e1610UL 960#define NIG_REG_DBG_SELECT \ 961 0x502140UL 962#define NIG_REG_DBG_DWORD_ENABLE \ 963 0x502144UL 964#define NIG_REG_DBG_SHIFT \ 965 0x502148UL 966#define NIG_REG_DBG_FORCE_VALID \ 967 0x50214cUL 968#define NIG_REG_DBG_FORCE_FRAME \ 969 0x502150UL 970#define BMB_REG_DBG_SELECT \ 971 0x540a7cUL 972#define BMB_REG_DBG_DWORD_ENABLE \ 973 0x540a80UL 974#define BMB_REG_DBG_SHIFT \ 975 0x540a84UL 976#define BMB_REG_DBG_FORCE_VALID \ 977 0x540a88UL 978#define BMB_REG_DBG_FORCE_FRAME \ 979 0x540a8cUL 980#define PTU_REG_DBG_SELECT \ 981 0x560100UL 982#define PTU_REG_DBG_DWORD_ENABLE \ 983 0x560104UL 984#define PTU_REG_DBG_SHIFT \ 985 0x560108UL 986#define PTU_REG_DBG_FORCE_VALID \ 987 0x56010cUL 988#define PTU_REG_DBG_FORCE_FRAME \ 989 0x560110UL 990#define CDU_REG_DBG_SELECT \ 991 0x580704UL 992#define CDU_REG_DBG_DWORD_ENABLE \ 993 0x580708UL 994#define CDU_REG_DBG_SHIFT \ 995 0x58070cUL 996#define CDU_REG_DBG_FORCE_VALID \ 997 0x580710UL 998#define CDU_REG_DBG_FORCE_FRAME \ 999 0x580714UL 1000#define WOL_REG_DBG_SELECT_K2 \
1001 0x600140UL 1002#define WOL_REG_DBG_DWORD_ENABLE_K2 \ 1003 0x600144UL 1004#define WOL_REG_DBG_SHIFT_K2 \ 1005 0x600148UL 1006#define WOL_REG_DBG_FORCE_VALID_K2 \ 1007 0x60014cUL 1008#define WOL_REG_DBG_FORCE_FRAME_K2 \ 1009 0x600150UL 1010#define BMBN_REG_DBG_SELECT_K2 \ 1011 0x610140UL 1012#define BMBN_REG_DBG_DWORD_ENABLE_K2 \ 1013 0x610144UL 1014#define BMBN_REG_DBG_SHIFT_K2 \ 1015 0x610148UL 1016#define BMBN_REG_DBG_FORCE_VALID_K2 \ 1017 0x61014cUL 1018#define BMBN_REG_DBG_FORCE_FRAME_K2 \ 1019 0x610150UL 1020#define NWM_REG_DBG_SELECT_K2 \ 1021 0x8000ecUL 1022#define NWM_REG_DBG_DWORD_ENABLE_K2 \ 1023 0x8000f0UL 1024#define NWM_REG_DBG_SHIFT_K2 \ 1025 0x8000f4UL 1026#define NWM_REG_DBG_FORCE_VALID_K2 \ 1027 0x8000f8UL 1028#define NWM_REG_DBG_FORCE_FRAME_K2\ 1029 0x8000fcUL 1030#define PBF_REG_DBG_SELECT \ 1031 0xd80060UL 1032#define PBF_REG_DBG_DWORD_ENABLE \ 1033 0xd80064UL 1034#define PBF_REG_DBG_SHIFT \ 1035 0xd80068UL 1036#define PBF_REG_DBG_FORCE_VALID \ 1037 0xd8006cUL 1038#define PBF_REG_DBG_FORCE_FRAME \ 1039 0xd80070UL 1040#define PBF_PB1_REG_DBG_SELECT \ 1041 0xda0728UL 1042#define PBF_PB1_REG_DBG_DWORD_ENABLE \ 1043 0xda072cUL 1044#define PBF_PB1_REG_DBG_SHIFT \ 1045 0xda0730UL 1046#define PBF_PB1_REG_DBG_FORCE_VALID \ 1047 0xda0734UL 1048#define PBF_PB1_REG_DBG_FORCE_FRAME \ 1049 0xda0738UL 1050#define PBF_PB2_REG_DBG_SELECT \ 1051 0xda4728UL 1052#define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1053 0xda472cUL 1054#define PBF_PB2_REG_DBG_SHIFT \ 1055 0xda4730UL 1056#define PBF_PB2_REG_DBG_FORCE_VALID \ 1057 0xda4734UL 1058#define PBF_PB2_REG_DBG_FORCE_FRAME \ 1059 0xda4738UL 1060#define BTB_REG_DBG_SELECT \ 1061 0xdb08c8UL 1062#define BTB_REG_DBG_DWORD_ENABLE \ 1063 0xdb08ccUL 1064#define BTB_REG_DBG_SHIFT \ 1065 0xdb08d0UL 1066#define BTB_REG_DBG_FORCE_VALID \ 1067 0xdb08d4UL 1068#define BTB_REG_DBG_FORCE_FRAME \ 1069 0xdb08d8UL 1070#define XSDM_REG_DBG_SELECT \ 1071 0xf80e28UL 1072#define XSDM_REG_DBG_DWORD_ENABLE \ 1073 0xf80e2cUL 1074#define XSDM_REG_DBG_SHIFT \ 1075 0xf80e30UL 1076#define XSDM_REG_DBG_FORCE_VALID \ 1077 0xf80e34UL 1078#define XSDM_REG_DBG_FORCE_FRAME \ 1079 0xf80e38UL 1080#define YSDM_REG_DBG_SELECT \ 1081 0xf90e28UL 1082#define YSDM_REG_DBG_DWORD_ENABLE \ 1083 0xf90e2cUL 1084#define YSDM_REG_DBG_SHIFT \ 1085 0xf90e30UL 1086#define YSDM_REG_DBG_FORCE_VALID \ 1087 0xf90e34UL 1088#define YSDM_REG_DBG_FORCE_FRAME \ 1089 0xf90e38UL 1090#define PSDM_REG_DBG_SELECT \ 1091 0xfa0e28UL 1092#define PSDM_REG_DBG_DWORD_ENABLE \ 1093 0xfa0e2cUL 1094#define PSDM_REG_DBG_SHIFT \ 1095 0xfa0e30UL 1096#define PSDM_REG_DBG_FORCE_VALID \ 1097 0xfa0e34UL 1098#define PSDM_REG_DBG_FORCE_FRAME \ 1099 0xfa0e38UL 1100#define TSDM_REG_DBG_SELECT \ 1101 0xfb0e28UL 1102#define TSDM_REG_DBG_DWORD_ENABLE \ 1103 0xfb0e2cUL 1104#define TSDM_REG_DBG_SHIFT \ 1105 0xfb0e30UL 1106#define TSDM_REG_DBG_FORCE_VALID \ 1107 0xfb0e34UL 1108#define TSDM_REG_DBG_FORCE_FRAME \ 1109 0xfb0e38UL 1110#define MSDM_REG_DBG_SELECT \ 1111 0xfc0e28UL 1112#define MSDM_REG_DBG_DWORD_ENABLE \ 1113 0xfc0e2cUL 1114#define MSDM_REG_DBG_SHIFT \ 1115 0xfc0e30UL 1116#define MSDM_REG_DBG_FORCE_VALID \ 1117 0xfc0e34UL 1118#define MSDM_REG_DBG_FORCE_FRAME \ 1119 0xfc0e38UL 1120#define USDM_REG_DBG_SELECT \ 1121 0xfd0e28UL 1122#define USDM_REG_DBG_DWORD_ENABLE \ 1123 0xfd0e2cUL 1124#define USDM_REG_DBG_SHIFT \ 1125 0xfd0e30UL 1126#define USDM_REG_DBG_FORCE_VALID \ 1127 0xfd0e34UL 1128#define USDM_REG_DBG_FORCE_FRAME \ 1129 0xfd0e38UL 1130#define XCM_REG_DBG_SELECT \ 1131 0x1000040UL 1132#define XCM_REG_DBG_DWORD_ENABLE \ 1133 0x1000044UL 1134#define XCM_REG_DBG_SHIFT \ 1135 0x1000048UL 1136#define XCM_REG_DBG_FORCE_VALID \ 1137 0x100004cUL 1138#define XCM_REG_DBG_FORCE_FRAME \ 1139 0x1000050UL 1140#define YCM_REG_DBG_SELECT \ 1141 0x1080040UL 1142#define YCM_REG_DBG_DWORD_ENABLE \ 1143 0x1080044UL 1144#define YCM_REG_DBG_SHIFT \ 1145 0x1080048UL 1146#define YCM_REG_DBG_FORCE_VALID \ 1147 0x108004cUL 1148#define YCM_REG_DBG_FORCE_FRAME \ 1149 0x1080050UL 1150#define PCM_REG_DBG_SELECT \ 1151 0x1100040UL 1152#define PCM_REG_DBG_DWORD_ENABLE \ 1153 0x1100044UL 1154#define PCM_REG_DBG_SHIFT \ 1155 0x1100048UL 1156#define PCM_REG_DBG_FORCE_VALID \ 1157 0x110004cUL 1158#define PCM_REG_DBG_FORCE_FRAME \ 1159 0x1100050UL 1160#define TCM_REG_DBG_SELECT \ 1161 0x1180040UL 1162#define TCM_REG_DBG_DWORD_ENABLE \ 1163 0x1180044UL 1164#define TCM_REG_DBG_SHIFT \ 1165 0x1180048UL 1166#define TCM_REG_DBG_FORCE_VALID \ 1167 0x118004cUL 1168#define TCM_REG_DBG_FORCE_FRAME \ 1169 0x1180050UL 1170#define MCM_REG_DBG_SELECT \ 1171 0x1200040UL 1172#define MCM_REG_DBG_DWORD_ENABLE \ 1173 0x1200044UL 1174#define MCM_REG_DBG_SHIFT \ 1175 0x1200048UL 1176#define MCM_REG_DBG_FORCE_VALID \ 1177 0x120004cUL 1178#define MCM_REG_DBG_FORCE_FRAME \ 1179 0x1200050UL 1180#define UCM_REG_DBG_SELECT \ 1181 0x1280050UL 1182#define UCM_REG_DBG_DWORD_ENABLE \ 1183 0x1280054UL 1184#define UCM_REG_DBG_SHIFT \ 1185 0x1280058UL 1186#define UCM_REG_DBG_FORCE_VALID \ 1187 0x128005cUL 1188#define UCM_REG_DBG_FORCE_FRAME \ 1189 0x1280060UL 1190#define XSEM_REG_DBG_SELECT \ 1191 0x1401528UL 1192#define XSEM_REG_DBG_DWORD_ENABLE \ 1193 0x140152cUL 1194#define XSEM_REG_DBG_SHIFT \ 1195 0x1401530UL 1196#define XSEM_REG_DBG_FORCE_VALID \ 1197 0x1401534UL 1198#define XSEM_REG_DBG_FORCE_FRAME \ 1199 0x1401538UL 1200#define YSEM_REG_DBG_SELECT \ 1201 0x1501528UL 1202#define YSEM_REG_DBG_DWORD_ENABLE \ 1203 0x150152cUL 1204#define YSEM_REG_DBG_SHIFT \ 1205 0x1501530UL 1206#define YSEM_REG_DBG_FORCE_VALID \ 1207 0x1501534UL 1208#define YSEM_REG_DBG_FORCE_FRAME \ 1209 0x1501538UL 1210#define PSEM_REG_DBG_SELECT \ 1211 0x1601528UL 1212#define PSEM_REG_DBG_DWORD_ENABLE \ 1213 0x160152cUL 1214#define PSEM_REG_DBG_SHIFT \ 1215 0x1601530UL 1216#define PSEM_REG_DBG_FORCE_VALID \ 1217 0x1601534UL 1218#define PSEM_REG_DBG_FORCE_FRAME \ 1219 0x1601538UL 1220#define TSEM_REG_DBG_SELECT \ 1221 0x1701528UL 1222#define TSEM_REG_DBG_DWORD_ENABLE \ 1223 0x170152cUL 1224#define TSEM_REG_DBG_SHIFT \ 1225 0x1701530UL 1226#define TSEM_REG_DBG_FORCE_VALID \ 1227 0x1701534UL 1228#define TSEM_REG_DBG_FORCE_FRAME \ 1229 0x1701538UL 1230#define MSEM_REG_DBG_SELECT \ 1231 0x1801528UL 1232#define MSEM_REG_DBG_DWORD_ENABLE \ 1233 0x180152cUL 1234#define MSEM_REG_DBG_SHIFT \ 1235 0x1801530UL 1236#define MSEM_REG_DBG_FORCE_VALID \ 1237 0x1801534UL 1238#define MSEM_REG_DBG_FORCE_FRAME \ 1239 0x1801538UL 1240#define USEM_REG_DBG_SELECT \ 1241 0x1901528UL 1242#define USEM_REG_DBG_DWORD_ENABLE \ 1243 0x190152cUL 1244#define USEM_REG_DBG_SHIFT \ 1245 0x1901530UL 1246#define USEM_REG_DBG_FORCE_VALID \ 1247 0x1901534UL 1248#define USEM_REG_DBG_FORCE_FRAME \ 1249 0x1901538UL 1250#define NWS_REG_DBG_SELECT_K2 \ 1251 0x700128UL 1252#define NWS_REG_DBG_DWORD_ENABLE_K2 \ 1253 0x70012cUL 1254#define NWS_REG_DBG_SHIFT_K2 \ 1255 0x700130UL 1256#define NWS_REG_DBG_FORCE_VALID_K2 \ 1257 0x700134UL 1258#define NWS_REG_DBG_FORCE_FRAME_K2 \ 1259 0x700138UL 1260#define MS_REG_DBG_SELECT_K2 \ 1261 0x6a0228UL 1262#define MS_REG_DBG_DWORD_ENABLE_K2 \ 1263 0x6a022cUL 1264#define MS_REG_DBG_SHIFT_K2 \ 1265 0x6a0230UL 1266#define MS_REG_DBG_FORCE_VALID_K2 \ 1267 0x6a0234UL 1268#define MS_REG_DBG_FORCE_FRAME_K2 \ 1269 0x6a0238UL 1270#define PCIE_REG_DBG_COMMON_SELECT_K2 \ 1271 0x054398UL 1272#define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2 \ 1273 0x05439cUL 1274#define PCIE_REG_DBG_COMMON_SHIFT_K2 \ 1275 0x0543a0UL 1276#define PCIE_REG_DBG_COMMON_FORCE_VALID_K2 \ 1277 0x0543a4UL 1278#define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2 \ 1279 0x0543a8UL 1280#define MISC_REG_RESET_PL_UA \ 1281 0x008050UL 1282#define MISC_REG_RESET_PL_HV \ 1283 0x008060UL 1284#define XCM_REG_CTX_RBC_ACCS \ 1285 0x1001800UL 1286#define XCM_REG_AGG_CON_CTX \ 1287 0x1001804UL 1288#define XCM_REG_SM_CON_CTX \ 1289 0x1001808UL 1290#define YCM_REG_CTX_RBC_ACCS \ 1291 0x1081800UL 1292#define YCM_REG_AGG_CON_CTX \ 1293 0x1081804UL 1294#define YCM_REG_AGG_TASK_CTX \ 1295 0x1081808UL 1296#define YCM_REG_SM_CON_CTX \ 1297 0x108180cUL 1298#define YCM_REG_SM_TASK_CTX \ 1299 0x1081810UL 1300#define PCM_REG_CTX_RBC_ACCS \ 1301 0x1101440UL 1302#define PCM_REG_SM_CON_CTX \ 1303 0x1101444UL 1304#define TCM_REG_CTX_RBC_ACCS \ 1305 0x11814c0UL 1306#define TCM_REG_AGG_CON_CTX \ 1307 0x11814c4UL 1308#define TCM_REG_AGG_TASK_CTX \ 1309 0x11814c8UL 1310#define TCM_REG_SM_CON_CTX \ 1311 0x11814ccUL 1312#define TCM_REG_SM_TASK_CTX \ 1313 0x11814d0UL 1314#define MCM_REG_CTX_RBC_ACCS \ 1315 0x1201800UL 1316#define MCM_REG_AGG_CON_CTX \ 1317 0x1201804UL 1318#define MCM_REG_AGG_TASK_CTX \ 1319 0x1201808UL 1320#define MCM_REG_SM_CON_CTX \ 1321 0x120180cUL 1322#define MCM_REG_SM_TASK_CTX \ 1323 0x1201810UL 1324#define UCM_REG_CTX_RBC_ACCS \ 1325 0x1281700UL 1326#define UCM_REG_AGG_CON_CTX \ 1327 0x1281704UL 1328#define UCM_REG_AGG_TASK_CTX \ 1329 0x1281708UL 1330#define UCM_REG_SM_CON_CTX \ 1331 0x128170cUL 1332#define UCM_REG_SM_TASK_CTX \ 1333 0x1281710UL 1334#define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1335 0x1401140UL 1336#define XSEM_REG_SYNC_DBG_EMPTY \ 1337 0x1401160UL 1338#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1339 0x1401400UL 1340#define XSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1341 0x1401404UL 1342#define XSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1343 0x1401408UL 1344#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1345 0x1401420UL 1346#define XSEM_REG_FAST_MEMORY \ 1347 0x1440000UL 1348#define YSEM_REG_SYNC_DBG_EMPTY \ 1349 0x1501160UL 1350#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1351 0x1501400UL 1352#define YSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1353 0x1501404UL 1354#define YSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1355 0x1501408UL 1356#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1357 0x1501420UL 1358#define YSEM_REG_FAST_MEMORY \ 1359 0x1540000UL 1360#define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1361 0x1601140UL 1362#define PSEM_REG_SYNC_DBG_EMPTY \ 1363 0x1601160UL 1364#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1365 0x1601400UL 1366#define PSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1367 0x1601404UL 1368#define PSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1369 0x1601408UL 1370#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1371 0x1601420UL 1372#define PSEM_REG_FAST_MEMORY \ 1373 0x1640000UL 1374#define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1375 0x1701140UL 1376#define TSEM_REG_SYNC_DBG_EMPTY \ 1377 0x1701160UL 1378#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1379 0x1701400UL 1380#define TSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1381 0x1701404UL 1382#define TSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1383 0x1701408UL 1384#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1385 0x1701420UL 1386#define TSEM_REG_FAST_MEMORY \ 1387 0x1740000UL 1388#define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1389 0x1801140UL 1390#define MSEM_REG_SYNC_DBG_EMPTY \ 1391 0x1801160UL 1392#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1393 0x1801400UL 1394#define MSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1395 0x1801404UL 1396#define MSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1397 0x1801408UL 1398#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1399 0x1801420UL 1400#define MSEM_REG_FAST_MEMORY \ 1401 0x1840000UL 1402#define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1403 0x1901140UL 1404#define USEM_REG_SYNC_DBG_EMPTY \ 1405 0x1901160UL 1406#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1407 0x1901400UL 1408#define USEM_REG_SLOW_DBG_MODE_BB_K2 \ 1409 0x1901404UL 1410#define USEM_REG_DBG_FRAME_MODE_BB_K2 \ 1411 0x1901408UL 1412#define USEM_REG_DBG_MODE1_CFG_BB_K2 \ 1413 0x1901420UL 1414#define USEM_REG_FAST_MEMORY \ 1415 0x1940000UL 1416#define SEM_FAST_REG_INT_RAM \ 1417 0x020000UL 1418#define SEM_FAST_REG_INT_RAM_SIZE \ 1419 20480 1420#define GRC_REG_TRACE_FIFO_VALID_DATA \ 1421 0x050064UL 1422#define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1423 0x05040cUL 1424#define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1425 0x050500UL 1426#define IGU_REG_ERROR_HANDLING_MEMORY \ 1427 0x181520UL 1428#define MCP_REG_CPU_MODE \ 1429 0xe05000UL 1430#define MCP_REG_CPU_MODE_SOFT_HALT \ 1431 (0x1 << 10) 1432#define BRB_REG_BIG_RAM_ADDRESS \ 1433 0x340800UL 1434#define BRB_REG_BIG_RAM_DATA \ 1435 0x341500UL 1436#define SEM_FAST_REG_STALL_0_BB_K2 \ 1437 0x000488UL 1438#define SEM_FAST_REG_STALLED \ 1439 0x000494UL 1440#define BTB_REG_BIG_RAM_ADDRESS \ 1441 0xdb0800UL 1442#define BTB_REG_BIG_RAM_DATA \ 1443 0xdb0c00UL 1444#define BMB_REG_BIG_RAM_ADDRESS \ 1445 0x540800UL 1446#define BMB_REG_BIG_RAM_DATA \ 1447 0x540f00UL 1448#define SEM_FAST_REG_STORM_REG_FILE \ 1449 0x008000UL 1450#define RSS_REG_RSS_RAM_ADDR \ 1451 0x238c30UL 1452#define MISCS_REG_BLOCK_256B_EN \ 1453 0x009074UL 1454#define MCP_REG_SCRATCH_SIZE \ 1455 57344 1456#define MCP_REG_CPU_REG_FILE \ 1457 0xe05200UL 1458#define MCP_REG_CPU_REG_FILE_SIZE \ 1459 32 1460#define DBG_REG_DEBUG_TARGET \ 1461 0x01005cUL 1462#define DBG_REG_FULL_MODE \ 1463 0x010060UL 1464#define DBG_REG_CALENDAR_OUT_DATA \ 1465 0x010480UL 1466#define GRC_REG_TRACE_FIFO \ 1467 0x050068UL 1468#define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1469 0x181530UL 1470#define DBG_REG_DBG_BLOCK_ON \ 1471 0x010454UL 1472#define DBG_REG_FRAMING_MODE \ 1473 0x010058UL 1474#define SEM_FAST_REG_VFC_DATA_WR \ 1475 0x000b40UL 1476#define SEM_FAST_REG_VFC_ADDR \ 1477 0x000b44UL 1478#define SEM_FAST_REG_VFC_DATA_RD \ 1479 0x000b48UL 1480#define RSS_REG_RSS_RAM_DATA \ 1481 0x238c20UL 1482#define RSS_REG_RSS_RAM_DATA_SIZE \ 1483 4 1484#define MISC_REG_BLOCK_256B_EN \ 1485 0x008c14UL 1486#define NWS_REG_NWS_CMU_K2 \ 1487 0x720000UL 1488#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \ 1489 0x000680UL 1490#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \ 1491 0x000684UL 1492#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \ 1493 0x0006c0UL 1494#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \ 1495 0x0006c4UL 1496#define MS_REG_MS_CMU_K2 \ 1497 0x6a4000UL 1498#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \ 1499 0x000208UL 1500#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \ 1501 0x00020cUL 1502#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \ 1503 0x000210UL 1504#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \ 1505 0x000214UL 1506#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \ 1507 0x000208UL 1508#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \ 1509 0x00020cUL 1510#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \ 1511 0x000210UL 1512#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \ 1513 0x000214UL 1514#define PHY_PCIE_REG_PHY0_K2 \ 1515 0x620000UL 1516#define PHY_PCIE_REG_PHY1_K2 \ 1517 0x624000UL 1518#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1519#define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1520#define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1521#define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1522#define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1523#define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1524#define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1525#define NIG_REG_RX_PTP_EN 0x501900UL 1526#define NIG_REG_TX_PTP_EN 0x501904UL 1527#define NIG_REG_LLH_PTP_TO_HOST 0x501908UL 1528#define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL 1529#define NIG_REG_PTP_SW_TXTSEN 0x501910UL 1530#define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL 1531#define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL 1532#define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL 1533#define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL 1534#define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL 1535#define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL 1536#define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL 1537#define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL 1538#define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL 1539#define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL 1540#define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL 1541#define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL 1542#define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL 1543#define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL 1544#define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL 1545#define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL 1546#define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL 1547#define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL 1548#define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL 1549#define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL 1550#define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL 1551#define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL 1552#define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL 1553#define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL 1554#define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL 1555#define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL 1556#define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL 1557#define PSWRQ2_REG_WR_MBS0 0x240400UL 1558 1559#define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL 1560#define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL 1561#define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL 1562#define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL 1563#define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL 1564#define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL 1565#define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL 1566 1567#define NIG_REG_TX_EDPM_CTRL 0x501f0cUL 1568#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0) 1569#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0 1570#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1) 1571#define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1 1572 1573#define PRS_REG_SEARCH_GFT 0x1f11bcUL 1574#define PRS_REG_CM_HDR_GFT 0x1f11c8UL 1575#define PRS_REG_GFT_CAM 0x1f1100UL 1576#define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL 1577#define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 1578#define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 1579#define PRS_REG_LOAD_L2_FILTER 0x1f0198UL 1580 1581#endif 1582