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20#ifndef __DESCS_H__
21#define __DESCS_H__
22
23#include <linux/bitops.h>
24
25
26
27
28#define RDES0_PAYLOAD_CSUM_ERR BIT(0)
29#define RDES0_CRC_ERROR BIT(1)
30#define RDES0_DRIBBLING BIT(2)
31#define RDES0_MII_ERROR BIT(3)
32#define RDES0_RECEIVE_WATCHDOG BIT(4)
33#define RDES0_FRAME_TYPE BIT(5)
34#define RDES0_COLLISION BIT(6)
35#define RDES0_IPC_CSUM_ERROR BIT(7)
36#define RDES0_LAST_DESCRIPTOR BIT(8)
37#define RDES0_FIRST_DESCRIPTOR BIT(9)
38#define RDES0_VLAN_TAG BIT(10)
39#define RDES0_OVERFLOW_ERROR BIT(11)
40#define RDES0_LENGTH_ERROR BIT(12)
41#define RDES0_SA_FILTER_FAIL BIT(13)
42#define RDES0_DESCRIPTOR_ERROR BIT(14)
43#define RDES0_ERROR_SUMMARY BIT(15)
44#define RDES0_FRAME_LEN_MASK GENMASK(29, 16)
45#define RDES0_FRAME_LEN_SHIFT 16
46#define RDES0_DA_FILTER_FAIL BIT(30)
47#define RDES0_OWN BIT(31)
48
49#define RDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
50#define RDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
51#define RDES1_BUFFER2_SIZE_SHIFT 11
52#define RDES1_SECOND_ADDRESS_CHAINED BIT(24)
53#define RDES1_END_RING BIT(25)
54#define RDES1_DISABLE_IC BIT(31)
55
56
57
58
59#define ERDES0_RX_MAC_ADDR BIT(0)
60
61
62#define ERDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
63#define ERDES1_SECOND_ADDRESS_CHAINED BIT(14)
64#define ERDES1_END_RING BIT(15)
65#define ERDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
66#define ERDES1_BUFFER2_SIZE_SHIFT 16
67#define ERDES1_DISABLE_IC BIT(31)
68
69
70
71#define TDES0_DEFERRED BIT(0)
72#define TDES0_UNDERFLOW_ERROR BIT(1)
73#define TDES0_EXCESSIVE_DEFERRAL BIT(2)
74#define TDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
75#define TDES0_VLAN_FRAME BIT(7)
76#define TDES0_EXCESSIVE_COLLISIONS BIT(8)
77#define TDES0_LATE_COLLISION BIT(9)
78#define TDES0_NO_CARRIER BIT(10)
79#define TDES0_LOSS_CARRIER BIT(11)
80#define TDES0_PAYLOAD_ERROR BIT(12)
81#define TDES0_FRAME_FLUSHED BIT(13)
82#define TDES0_JABBER_TIMEOUT BIT(14)
83#define TDES0_ERROR_SUMMARY BIT(15)
84#define TDES0_IP_HEADER_ERROR BIT(16)
85#define TDES0_TIME_STAMP_STATUS BIT(17)
86#define TDES0_OWN ((u32)BIT(31))
87
88#define TDES1_BUFFER1_SIZE_MASK GENMASK(10, 0)
89#define TDES1_BUFFER2_SIZE_MASK GENMASK(21, 11)
90#define TDES1_BUFFER2_SIZE_SHIFT 11
91#define TDES1_TIME_STAMP_ENABLE BIT(22)
92#define TDES1_DISABLE_PADDING BIT(23)
93#define TDES1_SECOND_ADDRESS_CHAINED BIT(24)
94#define TDES1_END_RING BIT(25)
95#define TDES1_CRC_DISABLE BIT(26)
96#define TDES1_CHECKSUM_INSERTION_MASK GENMASK(28, 27)
97#define TDES1_CHECKSUM_INSERTION_SHIFT 27
98#define TDES1_FIRST_SEGMENT BIT(29)
99#define TDES1_LAST_SEGMENT BIT(30)
100#define TDES1_INTERRUPT BIT(31)
101
102
103
104#define ETDES0_DEFERRED BIT(0)
105#define ETDES0_UNDERFLOW_ERROR BIT(1)
106#define ETDES0_EXCESSIVE_DEFERRAL BIT(2)
107#define ETDES0_COLLISION_COUNT_MASK GENMASK(6, 3)
108#define ETDES0_VLAN_FRAME BIT(7)
109#define ETDES0_EXCESSIVE_COLLISIONS BIT(8)
110#define ETDES0_LATE_COLLISION BIT(9)
111#define ETDES0_NO_CARRIER BIT(10)
112#define ETDES0_LOSS_CARRIER BIT(11)
113#define ETDES0_PAYLOAD_ERROR BIT(12)
114#define ETDES0_FRAME_FLUSHED BIT(13)
115#define ETDES0_JABBER_TIMEOUT BIT(14)
116#define ETDES0_ERROR_SUMMARY BIT(15)
117#define ETDES0_IP_HEADER_ERROR BIT(16)
118#define ETDES0_TIME_STAMP_STATUS BIT(17)
119#define ETDES0_SECOND_ADDRESS_CHAINED BIT(20)
120#define ETDES0_END_RING BIT(21)
121#define ETDES0_CHECKSUM_INSERTION_MASK GENMASK(23, 22)
122#define ETDES0_CHECKSUM_INSERTION_SHIFT 22
123#define ETDES0_TIME_STAMP_ENABLE BIT(25)
124#define ETDES0_DISABLE_PADDING BIT(26)
125#define ETDES0_CRC_DISABLE BIT(27)
126#define ETDES0_FIRST_SEGMENT BIT(28)
127#define ETDES0_LAST_SEGMENT BIT(29)
128#define ETDES0_INTERRUPT BIT(30)
129#define ETDES0_OWN ((u32)BIT(31))
130
131#define ETDES1_BUFFER1_SIZE_MASK GENMASK(12, 0)
132#define ETDES1_BUFFER2_SIZE_MASK GENMASK(28, 16)
133#define ETDES1_BUFFER2_SIZE_SHIFT 16
134
135
136#define ERDES4_IP_PAYLOAD_TYPE_MASK GENMASK(2, 6)
137#define ERDES4_IP_HDR_ERR BIT(3)
138#define ERDES4_IP_PAYLOAD_ERR BIT(4)
139#define ERDES4_IP_CSUM_BYPASSED BIT(5)
140#define ERDES4_IPV4_PKT_RCVD BIT(6)
141#define ERDES4_IPV6_PKT_RCVD BIT(7)
142#define ERDES4_MSG_TYPE_MASK GENMASK(11, 8)
143#define ERDES4_PTP_FRAME_TYPE BIT(12)
144#define ERDES4_PTP_VER BIT(13)
145#define ERDES4_TIMESTAMP_DROPPED BIT(14)
146#define ERDES4_AV_PKT_RCVD BIT(16)
147#define ERDES4_AV_TAGGED_PKT_RCVD BIT(17)
148#define ERDES4_VLAN_TAG_PRI_VAL_MASK GENMASK(20, 18)
149#define ERDES4_L3_FILTER_MATCH BIT(24)
150#define ERDES4_L4_FILTER_MATCH BIT(25)
151#define ERDES4_L3_L4_FILT_NO_MATCH_MASK GENMASK(27, 26)
152
153
154#define RDES_EXT_NO_PTP 0x0
155#define RDES_EXT_SYNC 0x1
156#define RDES_EXT_FOLLOW_UP 0x2
157#define RDES_EXT_DELAY_REQ 0x3
158#define RDES_EXT_DELAY_RESP 0x4
159#define RDES_EXT_PDELAY_REQ 0x5
160#define RDES_EXT_PDELAY_RESP 0x6
161#define RDES_EXT_PDELAY_FOLLOW_UP 0x7
162#define RDES_PTP_ANNOUNCE 0x8
163#define RDES_PTP_MANAGEMENT 0x9
164#define RDES_PTP_SIGNALING 0xa
165#define RDES_PTP_PKT_RESERVED_TYPE 0xf
166
167
168struct dma_desc {
169 __le32 des0;
170 __le32 des1;
171 __le32 des2;
172 __le32 des3;
173};
174
175
176struct dma_extended_desc {
177 struct dma_desc basic;
178 __le32 des4;
179 __le32 des5;
180 __le32 des6;
181 __le32 des7;
182};
183
184
185#define TX_CIC_FULL 3
186
187#endif
188