1/* 2 * Xilinx FPGA Xilinx TSN timer module header. 3 * 4 * Copyright (c) 2017 Xilinx Pvt., Ltd 5 * 6 * Author: Syed S <syeds@xilinx.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#ifndef _XILINX_TSN_H_ 19#define _XILINX_TSN_H_ 20 21#include <linux/platform_device.h> 22 23#define XAE_RTC_OFFSET 0x12800 24/* RTC Nanoseconds Field Offset Register */ 25#define XTIMER1588_RTC_OFFSET_NS 0x00000 26/* RTC Seconds Field Offset Register - Low */ 27#define XTIMER1588_RTC_OFFSET_SEC_L 0x00008 28/* RTC Seconds Field Offset Register - High */ 29#define XTIMER1588_RTC_OFFSET_SEC_H 0x0000C 30/* RTC Increment */ 31#define XTIMER1588_RTC_INCREMENT 0x00010 32/* Current TOD Nanoseconds - RO */ 33#define XTIMER1588_CURRENT_RTC_NS 0x00014 34/* Current TOD Seconds -Low RO */ 35#define XTIMER1588_CURRENT_RTC_SEC_L 0x00018 36/* Current TOD Seconds -High RO */ 37#define XTIMER1588_CURRENT_RTC_SEC_H 0x0001C 38#define XTIMER1588_SYNTONIZED_NS 0x0002C 39#define XTIMER1588_SYNTONIZED_SEC_L 0x00030 40#define XTIMER1588_SYNTONIZED_SEC_H 0x00034 41/* Write to Bit 0 to clear the interrupt */ 42#define XTIMER1588_INTERRUPT 0x00020 43/* 8kHz Pulse Offset Register */ 44#define XTIMER1588_8KPULSE 0x00024 45/* Correction Field - Low */ 46#define XTIMER1588_CF_L 0x0002C 47/* Correction Field - Low */ 48#define XTIMER1588_CF_H 0x00030 49 50#define XTIMER1588_RTC_MASK ((1 << 26) - 1) 51#define XTIMER1588_INT_SHIFT 0 52#define NANOSECOND_BITS 20 53#define NANOSECOND_MASK ((1 << NANOSECOND_BITS) - 1) 54#define SECOND_MASK ((1 << (32 - NANOSECOND_BITS)) - 1) 55#define XTIMER1588_RTC_INCREMENT_SHIFT 20 56#define PULSESIN1PPS 128 57 58/* Read/Write access to the registers */ 59#ifndef out_be32 60#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP) 61#define in_be32(offset) __raw_readl(offset) 62#define out_be32(offset, val) __raw_writel(val, offset) 63#endif 64#endif 65 66/* The tsn ptp module will set this variable */ 67extern int axienet_phc_index; 68 69void *axienet_ptp_timer_probe(void __iomem *base, 70 struct platform_device *pdev); 71int axienet_ptp_timer_remove(void *priv); 72int axienet_get_phc_index(void *priv); 73#endif 74