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15#ifndef _HWM_
16#define _HWM_
17
18#include "mbuf.h"
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33#ifndef DRV_BUF_FLUSH
34#define DRV_BUF_FLUSH(desc,flag)
35#define DDI_DMA_SYNC_FORCPU
36#define DDI_DMA_SYNC_FORDEV
37#endif
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42#define RX_ENABLE_PASS_SMT 21
43#define RX_DISABLE_PASS_SMT 22
44#define RX_ENABLE_PASS_NSA 23
45#define RX_DISABLE_PASS_NSA 24
46#define RX_ENABLE_PASS_DB 25
47#define RX_DISABLE_PASS_DB 26
48#define RX_DISABLE_PASS_ALL 27
49#define RX_DISABLE_LLC_PROMISC 28
50#define RX_ENABLE_LLC_PROMISC 29
51
52
53#ifndef DMA_RD
54#define DMA_RD 1
55#endif
56#ifndef DMA_WR
57#define DMA_WR 2
58#endif
59#define SMT_BUF 0x80
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63
64#define EN_IRQ_EOF 0x02
65#define LOC_TX 0x04
66#define LAST_FRAG 0x08
67#define FIRST_FRAG 0x10
68#define LAN_TX 0x20
69#define RING_DOWN 0x40
70#define OUT_OF_TXD 0x80
71
72
73#ifndef NULL
74#define NULL 0
75#endif
76
77#define C_INDIC (1L<<25)
78#define A_INDIC (1L<<26)
79#define RD_FS_LOCAL 0x80
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83
84#define DEBUG_SMTF 1
85#define DEBUG_SMT 2
86#define DEBUG_ECM 3
87#define DEBUG_RMT 4
88#define DEBUG_CFM 5
89#define DEBUG_PCM 6
90#define DEBUG_SBA 7
91#define DEBUG_ESS 8
92
93#define DB_HWM_RX 10
94#define DB_HWM_TX 11
95#define DB_HWM_GEN 12
96
97struct s_mbuf_pool {
98#ifndef MB_OUTSIDE_SMC
99 SMbuf mb[MAX_MBUF] ;
100#endif
101 SMbuf *mb_start ;
102 SMbuf *mb_free ;
103} ;
104
105struct hwm_r {
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109 u_int len ;
110 char *mb_pos ;
111} ;
112
113struct hw_modul {
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117 struct s_mbuf_pool mbuf_pool ;
118 struct hwm_r r ;
119
120 union s_fp_descr volatile *descr_p ;
121
122 u_short pass_SMT ;
123 u_short pass_NSA ;
124 u_short pass_DB ;
125 u_short pass_llc_promisc ;
126
127 SMbuf *llc_rx_pipe ;
128 SMbuf *llc_rx_tail ;
129 int queued_rx_frames ;
130
131 SMbuf *txd_tx_pipe ;
132 SMbuf *txd_tx_tail ;
133 int queued_txd_mb ;
134
135 int rx_break ;
136 int leave_isr ;
137 int isr_flag ;
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141 struct s_smt_tx_queue *tx_p ;
142 u_long tx_descr ;
143 int tx_len ;
144 SMbuf *tx_mb ;
145 char *tx_data ;
146
147 int detec_count ;
148 u_long rx_len_error ;
149} ;
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155
156#ifdef DEBUG
157struct os_debug {
158 int hwm_rx ;
159 int hwm_tx ;
160 int hwm_gen ;
161} ;
162#endif
163
164#ifdef DEBUG
165#ifdef DEBUG_BRD
166#define DB_P smc->debug
167#else
168#define DB_P debug
169#endif
170
171#define DB_RX(lev, fmt, ...) \
172do { \
173 if (DB_P.d_os.hwm_rx >= (lev)) \
174 printf(fmt "\n", ##__VA_ARGS__); \
175} while (0)
176#define DB_TX(lev, fmt, ...) \
177do { \
178 if (DB_P.d_os.hwm_tx >= (lev)) \
179 printf(fmt "\n", ##__VA_ARGS__); \
180} while (0)
181#define DB_GEN(lev, fmt, ...) \
182do { \
183 if (DB_P.d_os.hwm_gen >= (lev)) \
184 printf(fmt "\n", ##__VA_ARGS__); \
185} while (0)
186#else
187#define DB_RX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
188#define DB_TX(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
189#define DB_GEN(lev, fmt, ...) no_printk(fmt "\n", ##__VA_ARGS__)
190#endif
191
192#ifndef SK_BREAK
193#define SK_BREAK()
194#endif
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213#define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
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229#define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
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246#define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
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264#define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
265 (smc)->hw.fp.tx_q[queue].tx_curr_put
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281#define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
282 RD_LENGTH)
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298#define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
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315#define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
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329#define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
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344#define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
345 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
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361#ifndef HWM_NO_FLOW_CTL
362#define HWM_RX_CHECK(smc,low_water) {\
363 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
364 mac_drv_fill_rxd(smc) ;\
365 }\
366}
367#else
368#define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
369#endif
370
371#ifndef HWM_EBASE
372#define HWM_EBASE 500
373#endif
374
375#define HWM_E0001 HWM_EBASE + 1
376#define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
377#define HWM_E0002 HWM_EBASE + 2
378#define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
379#define HWM_E0003 HWM_EBASE + 3
380#define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
381#define HWM_E0004 HWM_EBASE + 4
382#define HWM_E0004_MSG "HWM: Parity error rx queue 1"
383#define HWM_E0005 HWM_EBASE + 5
384#define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
385#define HWM_E0006 HWM_EBASE + 6
386#define HWM_E0006_MSG "HWM: Encoding error async tx queue"
387#define HWM_E0007 HWM_EBASE + 7
388#define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
389#define HWM_E0008 HWM_EBASE + 8
390#define HWM_E0008_MSG ""
391#define HWM_E0009 HWM_EBASE + 9
392#define HWM_E0009_MSG "HWM: Out of RxD condition detected"
393#define HWM_E0010 HWM_EBASE + 10
394#define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
395#define HWM_E0011 HWM_EBASE + 11
396#define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
397#define HWM_E0012 HWM_EBASE + 12
398#define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
399#define HWM_E0013 HWM_EBASE + 13
400#define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
401
402#endif
403