1/* 2 * Intel Core SoC Power Management Controller Header File 3 * 4 * Copyright (c) 2016, Intel Corporation. 5 * All Rights Reserved. 6 * 7 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> 8 * Vishwanath Somayaji <vishwanath.somayaji@intel.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 */ 20 21#ifndef PMC_CORE_H 22#define PMC_CORE_H 23 24/* Sunrise Point Power Management Controller PCI Device ID */ 25#define SPT_PMC_PCI_DEVICE_ID 0x9d21 26 27#define SPT_PMC_BASE_ADDR_OFFSET 0x48 28#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c 29#define SPT_PMC_PM_CFG_OFFSET 0x18 30#define SPT_PMC_PM_STS_OFFSET 0x1c 31#define SPT_PMC_MTPMC_OFFSET 0x20 32#define SPT_PMC_MFPMC_OFFSET 0x38 33#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 34#define SPT_PMC_MPHY_CORE_STS_0 0x1143 35#define SPT_PMC_MPHY_CORE_STS_1 0x1142 36#define SPT_PMC_MPHY_COM_STS_0 0x1155 37#define SPT_PMC_MMIO_REG_LEN 0x1000 38#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 39#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 40#define MTPMC_MASK 0xffff0000 41#define PPFEAR_MAX_NUM_ENTRIES 5 42#define SPT_PPFEAR_NUM_ENTRIES 5 43#define SPT_PMC_READ_DISABLE_BIT 0x16 44#define SPT_PMC_MSG_FULL_STS_BIT 0x18 45#define NUM_RETRIES 100 46#define NUM_IP_IGN_ALLOWED 17 47 48/* Sunrise Point: PGD PFET Enable Ack Status Registers */ 49enum ppfear_regs { 50 SPT_PMC_XRAM_PPFEAR0A = 0x590, 51 SPT_PMC_XRAM_PPFEAR0B, 52 SPT_PMC_XRAM_PPFEAR0C, 53 SPT_PMC_XRAM_PPFEAR0D, 54 SPT_PMC_XRAM_PPFEAR1A, 55}; 56 57#define SPT_PMC_BIT_PMC BIT(0) 58#define SPT_PMC_BIT_OPI BIT(1) 59#define SPT_PMC_BIT_SPI BIT(2) 60#define SPT_PMC_BIT_XHCI BIT(3) 61#define SPT_PMC_BIT_SPA BIT(4) 62#define SPT_PMC_BIT_SPB BIT(5) 63#define SPT_PMC_BIT_SPC BIT(6) 64#define SPT_PMC_BIT_GBE BIT(7) 65 66#define SPT_PMC_BIT_SATA BIT(0) 67#define SPT_PMC_BIT_HDA_PGD0 BIT(1) 68#define SPT_PMC_BIT_HDA_PGD1 BIT(2) 69#define SPT_PMC_BIT_HDA_PGD2 BIT(3) 70#define SPT_PMC_BIT_HDA_PGD3 BIT(4) 71#define SPT_PMC_BIT_RSVD_0B BIT(5) 72#define SPT_PMC_BIT_LPSS BIT(6) 73#define SPT_PMC_BIT_LPC BIT(7) 74 75#define SPT_PMC_BIT_SMB BIT(0) 76#define SPT_PMC_BIT_ISH BIT(1) 77#define SPT_PMC_BIT_P2SB BIT(2) 78#define SPT_PMC_BIT_DFX BIT(3) 79#define SPT_PMC_BIT_SCC BIT(4) 80#define SPT_PMC_BIT_RSVD_0C BIT(5) 81#define SPT_PMC_BIT_FUSE BIT(6) 82#define SPT_PMC_BIT_CAMREA BIT(7) 83 84#define SPT_PMC_BIT_RSVD_0D BIT(0) 85#define SPT_PMC_BIT_USB3_OTG BIT(1) 86#define SPT_PMC_BIT_EXI BIT(2) 87#define SPT_PMC_BIT_CSE BIT(3) 88#define SPT_PMC_BIT_CSME_KVM BIT(4) 89#define SPT_PMC_BIT_CSME_PMT BIT(5) 90#define SPT_PMC_BIT_CSME_CLINK BIT(6) 91#define SPT_PMC_BIT_CSME_PTIO BIT(7) 92 93#define SPT_PMC_BIT_CSME_USBR BIT(0) 94#define SPT_PMC_BIT_CSME_SUSRAM BIT(1) 95#define SPT_PMC_BIT_CSME_SMT BIT(2) 96#define SPT_PMC_BIT_RSVD_1A BIT(3) 97#define SPT_PMC_BIT_CSME_SMS2 BIT(4) 98#define SPT_PMC_BIT_CSME_SMS1 BIT(5) 99#define SPT_PMC_BIT_CSME_RTC BIT(6) 100#define SPT_PMC_BIT_CSME_PSF BIT(7) 101 102#define SPT_PMC_BIT_MPHY_LANE0 BIT(0) 103#define SPT_PMC_BIT_MPHY_LANE1 BIT(1) 104#define SPT_PMC_BIT_MPHY_LANE2 BIT(2) 105#define SPT_PMC_BIT_MPHY_LANE3 BIT(3) 106#define SPT_PMC_BIT_MPHY_LANE4 BIT(4) 107#define SPT_PMC_BIT_MPHY_LANE5 BIT(5) 108#define SPT_PMC_BIT_MPHY_LANE6 BIT(6) 109#define SPT_PMC_BIT_MPHY_LANE7 BIT(7) 110 111#define SPT_PMC_BIT_MPHY_LANE8 BIT(0) 112#define SPT_PMC_BIT_MPHY_LANE9 BIT(1) 113#define SPT_PMC_BIT_MPHY_LANE10 BIT(2) 114#define SPT_PMC_BIT_MPHY_LANE11 BIT(3) 115#define SPT_PMC_BIT_MPHY_LANE12 BIT(4) 116#define SPT_PMC_BIT_MPHY_LANE13 BIT(5) 117#define SPT_PMC_BIT_MPHY_LANE14 BIT(6) 118#define SPT_PMC_BIT_MPHY_LANE15 BIT(7) 119 120#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0) 121#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1) 122#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 123#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 124 125struct pmc_bit_map { 126 const char *name; 127 u32 bit_mask; 128}; 129 130/** 131 * struct pmc_reg_map - Structure used to define parameter unique to a 132 PCH family 133 * @pfear_sts: Maps name of IP block to PPFEAR* bit 134 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit 135 * @pll_sts: Maps name of PLL to corresponding bit status 136 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency 137 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit 138 * @base_address: Base address of PWRMBASE defined in BIOS writer guide 139 * @regmap_length: Length of memory to map from PWRMBASE address to access 140 * @ppfear0_offset: PWRMBASE offset to to read PPFEAR* 141 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from 142 * PPFEAR 143 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register 144 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE 145 * 146 * Each PCH has unique set of register offsets and bit indexes. This structure 147 * captures them to have a common implementation. 148 */ 149struct pmc_reg_map { 150 const struct pmc_bit_map *pfear_sts; 151 const struct pmc_bit_map *mphy_sts; 152 const struct pmc_bit_map *pll_sts; 153 const u32 slp_s0_offset; 154 const u32 ltr_ignore_offset; 155 const u32 base_address; 156 const int regmap_length; 157 const u32 ppfear0_offset; 158 const int ppfear_buckets; 159 const u32 pm_cfg_offset; 160 const int pm_read_disable_bit; 161}; 162 163/** 164 * struct pmc_dev - pmc device structure 165 * @base_addr: comtains pmc base address 166 * @regbase: pointer to io-remapped memory location 167 * @dbgfs_dir: path to debug fs interface 168 * @feature_available: flag to indicate whether 169 * the feature is available 170 * on a particular platform or not. 171 * 172 * pmc_dev contains info about power management controller device. 173 */ 174struct pmc_dev { 175 u32 base_addr; 176 void __iomem *regbase; 177 const struct pmc_reg_map *map; 178#if IS_ENABLED(CONFIG_DEBUG_FS) 179 struct dentry *dbgfs_dir; 180#endif /* CONFIG_DEBUG_FS */ 181 bool has_slp_s0_res; 182 int pmc_xram_read_bit; 183 struct mutex lock; /* generic mutex lock for PMC Core */ 184}; 185 186#endif /* PMC_CORE_H */ 187