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22#ifndef __JSM_DRIVER_H
23#define __JSM_DRIVER_H
24
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/tty.h>
28#include <linux/serial_core.h>
29#include <linux/device.h>
30
31
32
33
34
35enum {
36 DBG_INIT = 0x01,
37 DBG_BASIC = 0x02,
38 DBG_CORE = 0x04,
39 DBG_OPEN = 0x08,
40 DBG_CLOSE = 0x10,
41 DBG_READ = 0x20,
42 DBG_WRITE = 0x40,
43 DBG_IOCTL = 0x80,
44 DBG_PROC = 0x100,
45 DBG_PARAM = 0x200,
46 DBG_PSCAN = 0x400,
47 DBG_EVENT = 0x800,
48 DBG_DRAIN = 0x1000,
49 DBG_MSIGS = 0x2000,
50 DBG_MGMT = 0x4000,
51 DBG_INTR = 0x8000,
52 DBG_CARR = 0x10000,
53};
54
55#define jsm_dbg(nlevel, pdev, fmt, ...) \
56do { \
57 if (DBG_##nlevel & jsm_debug) \
58 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
59} while (0)
60
61#define MAXLINES 256
62#define MAXPORTS 8
63#define MAX_STOPS_SENT 5
64
65
66#define PCI_DEVICE_ID_CLASSIC_4 0x0028
67#define PCI_DEVICE_ID_CLASSIC_8 0x0029
68#define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0
69#define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1
70#define PCI_DEVICE_ID_NEO_4 0x00B0
71#define PCI_DEVICE_ID_NEO_1_422 0x00CC
72#define PCI_DEVICE_ID_NEO_1_422_485 0x00CD
73#define PCI_DEVICE_ID_NEO_2_422_485 0x00CE
74#define PCIE_DEVICE_ID_NEO_8 0x00F0
75#define PCIE_DEVICE_ID_NEO_4 0x00F1
76#define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2
77#define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3
78
79
80
81#define T_NEO 0000
82#define T_CLASSIC 0001
83#define T_PCIBUS 0400
84
85
86
87#define BD_RUNNING 0x0
88#define BD_REASON 0x7f
89#define BD_NOTFOUND 0x1
90#define BD_NOIOPORT 0x2
91#define BD_NOMEM 0x3
92#define BD_NOBIOS 0x4
93#define BD_NOFEP 0x5
94#define BD_FAILED 0x6
95#define BD_ALLOCATED 0x7
96#define BD_TRIBOOT 0x8
97#define BD_BADKME 0x80
98
99
100
101#define WRITEBUFLEN ((4096) + 4)
102
103#define JSM_VERSION "jsm: 1.2-1-INKERNEL"
104#define JSM_PARTNUM "40002438_A-INKERNEL"
105
106struct jsm_board;
107struct jsm_channel;
108
109
110
111
112struct board_ops {
113 irq_handler_t intr;
114 void (*uart_init)(struct jsm_channel *ch);
115 void (*uart_off)(struct jsm_channel *ch);
116 void (*param)(struct jsm_channel *ch);
117 void (*assert_modem_signals)(struct jsm_channel *ch);
118 void (*flush_uart_write)(struct jsm_channel *ch);
119 void (*flush_uart_read)(struct jsm_channel *ch);
120 void (*disable_receiver)(struct jsm_channel *ch);
121 void (*enable_receiver)(struct jsm_channel *ch);
122 void (*send_break)(struct jsm_channel *ch);
123 void (*clear_break)(struct jsm_channel *ch);
124 void (*send_start_character)(struct jsm_channel *ch);
125 void (*send_stop_character)(struct jsm_channel *ch);
126 void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
127 u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
128 void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
129};
130
131
132
133
134
135struct jsm_board
136{
137 int boardnum;
138
139 int type;
140 u8 rev;
141 struct pci_dev *pci_dev;
142 u32 maxports;
143
144 spinlock_t bd_intr_lock;
145
146
147
148 u32 nasync;
149
150 u32 irq;
151
152 u64 membase;
153 u64 membase_end;
154
155 u8 __iomem *re_map_membase;
156
157 u64 iobase;
158 u64 iobase_end;
159
160 u32 bd_uart_offset;
161
162 struct jsm_channel *channels[MAXPORTS];
163
164 u32 bd_dividend;
165
166 struct board_ops *bd_ops;
167
168 struct list_head jsm_board_entry;
169};
170
171
172
173
174#define CH_PRON 0x0001
175#define CH_STOP 0x0002
176#define CH_STOPI 0x0004
177#define CH_CD 0x0008
178#define CH_FCAR 0x0010
179#define CH_HANGUP 0x0020
180
181#define CH_RECEIVER_OFF 0x0040
182#define CH_OPENING 0x0080
183#define CH_CLOSING 0x0100
184#define CH_FIFO_ENABLED 0x0200
185#define CH_TX_FIFO_EMPTY 0x0400
186#define CH_TX_FIFO_LWM 0x0800
187#define CH_BREAK_SENDING 0x1000
188#define CH_LOOPBACK 0x2000
189#define CH_BAUD0 0x08000
190
191
192#define RQUEUEMASK 0x1FFF
193#define EQUEUEMASK 0x1FFF
194#define RQUEUESIZE (RQUEUEMASK + 1)
195#define EQUEUESIZE RQUEUESIZE
196
197
198
199
200
201struct jsm_channel {
202 struct uart_port uart_port;
203 struct jsm_board *ch_bd;
204
205 spinlock_t ch_lock;
206 wait_queue_head_t ch_flags_wait;
207
208 u32 ch_portnum;
209 u32 ch_open_count;
210 u32 ch_flags;
211
212 u64 ch_close_delay;
213
214 tcflag_t ch_c_iflag;
215 tcflag_t ch_c_cflag;
216 tcflag_t ch_c_oflag;
217 tcflag_t ch_c_lflag;
218 u8 ch_stopc;
219 u8 ch_startc;
220
221 u8 ch_mostat;
222 u8 ch_mistat;
223
224
225 struct neo_uart_struct __iomem *ch_neo_uart;
226 struct cls_uart_struct __iomem *ch_cls_uart;
227
228 u8 ch_cached_lsr;
229
230 u8 *ch_rqueue;
231 u16 ch_r_head;
232 u16 ch_r_tail;
233
234 u8 *ch_equeue;
235 u16 ch_e_head;
236 u16 ch_e_tail;
237
238 u64 ch_rxcount;
239 u64 ch_txcount;
240
241 u8 ch_r_tlevel;
242 u8 ch_t_tlevel;
243
244 u8 ch_r_watermark;
245
246
247 u32 ch_stops_sent;
248
249
250 u64 ch_err_parity;
251 u64 ch_err_frame;
252 u64 ch_err_break;
253 u64 ch_err_overrun;
254
255 u64 ch_xon_sends;
256 u64 ch_xoff_sends;
257};
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267
268struct cls_uart_struct {
269 u8 txrx;
270 u8 ier;
271 u8 isr_fcr;
272 u8 lcr;
273 u8 mcr;
274 u8 lsr;
275 u8 msr;
276 u8 spr;
277};
278
279
280#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
281
282#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
283
284#define UART_16654_FCR_TXTRIGGER_8 0x0
285#define UART_16654_FCR_TXTRIGGER_16 0x10
286#define UART_16654_FCR_TXTRIGGER_32 0x20
287#define UART_16654_FCR_TXTRIGGER_56 0x30
288
289#define UART_16654_FCR_RXTRIGGER_8 0x0
290#define UART_16654_FCR_RXTRIGGER_16 0x40
291#define UART_16654_FCR_RXTRIGGER_56 0x80
292#define UART_16654_FCR_RXTRIGGER_60 0xC0
293
294#define UART_IIR_CTSRTS 0x20
295#define UART_IIR_RDI_TIMEOUT 0x0C
296
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300
301#define UART_EXAR654_EFR_ECB 0x10
302#define UART_EXAR654_EFR_IXON 0x2
303#define UART_EXAR654_EFR_IXOFF 0x8
304#define UART_EXAR654_EFR_RTSDTR 0x40
305#define UART_EXAR654_EFR_CTSDSR 0x80
306
307#define UART_EXAR654_XOFF_DETECT 0x1
308#define UART_EXAR654_XON_DETECT 0x2
309
310#define UART_EXAR654_IER_XOFF 0x20
311#define UART_EXAR654_IER_RTSDTR 0x40
312#define UART_EXAR654_IER_CTSDSR 0x80
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322
323struct neo_uart_struct {
324 u8 txrx;
325 u8 ier;
326 u8 isr_fcr;
327 u8 lcr;
328 u8 mcr;
329 u8 lsr;
330 u8 msr;
331 u8 spr;
332 u8 fctr;
333 u8 efr;
334 u8 tfifo;
335 u8 rfifo;
336 u8 xoffchar1;
337 u8 xoffchar2;
338 u8 xonchar1;
339 u8 xonchar2;
340
341 u8 reserved1[0x2ff - 0x200];
342 u8 txrxburst[64];
343 u8 reserved2[0x37f - 0x340];
344 u8 rxburst_with_errors[64];
345};
346
347
348#define UART_17158_POLL_ADDR_OFFSET 0x80
349
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352
353
354
355
356#define UART_17158_FCTR_RTS_NODELAY 0x00
357#define UART_17158_FCTR_RTS_4DELAY 0x01
358#define UART_17158_FCTR_RTS_6DELAY 0x02
359#define UART_17158_FCTR_RTS_8DELAY 0x03
360#define UART_17158_FCTR_RTS_12DELAY 0x12
361#define UART_17158_FCTR_RTS_16DELAY 0x05
362#define UART_17158_FCTR_RTS_20DELAY 0x13
363#define UART_17158_FCTR_RTS_24DELAY 0x06
364#define UART_17158_FCTR_RTS_28DELAY 0x14
365#define UART_17158_FCTR_RTS_32DELAY 0x07
366#define UART_17158_FCTR_RTS_36DELAY 0x16
367#define UART_17158_FCTR_RTS_40DELAY 0x08
368#define UART_17158_FCTR_RTS_44DELAY 0x09
369#define UART_17158_FCTR_RTS_48DELAY 0x10
370#define UART_17158_FCTR_RTS_52DELAY 0x11
371
372#define UART_17158_FCTR_RTS_IRDA 0x10
373#define UART_17158_FCTR_RS485 0x20
374#define UART_17158_FCTR_TRGA 0x00
375#define UART_17158_FCTR_TRGB 0x40
376#define UART_17158_FCTR_TRGC 0x80
377#define UART_17158_FCTR_TRGD 0xC0
378
379
380#define UART_17158_FCTR_BIT6 0x40
381#define UART_17158_FCTR_BIT7 0x80
382
383
384#define UART_17158_RX_FIFOSIZE 64
385#define UART_17158_TX_FIFOSIZE 64
386
387
388#define UART_17158_IIR_RDI_TIMEOUT 0x0C
389#define UART_17158_IIR_XONXOFF 0x10
390#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20
391#define UART_17158_IIR_FIFO_ENABLED 0xC0
392
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396
397#define UART_17158_RX_LINE_STATUS 0x1
398#define UART_17158_RXRDY_TIMEOUT 0x2
399#define UART_17158_TXRDY 0x3
400#define UART_17158_MSR 0x4
401#define UART_17158_TX_AND_FIFO_CLR 0x40
402#define UART_17158_RX_FIFO_DATA_ERROR 0x80
403
404
405
406
407
408#define UART_17158_EFR_ECB 0x10
409#define UART_17158_EFR_IXON 0x2
410#define UART_17158_EFR_IXOFF 0x8
411#define UART_17158_EFR_RTSDTR 0x40
412#define UART_17158_EFR_CTSDSR 0x80
413
414#define UART_17158_XOFF_DETECT 0x1
415#define UART_17158_XON_DETECT 0x2
416
417#define UART_17158_IER_RSVD1 0x10
418#define UART_17158_IER_XOFF 0x20
419#define UART_17158_IER_RTSDTR 0x40
420#define UART_17158_IER_CTSDSR 0x80
421
422#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
423#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
424#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
425#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
426#define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
427
428
429
430
431extern struct uart_driver jsm_uart_driver;
432extern struct board_ops jsm_neo_ops;
433extern struct board_ops jsm_cls_ops;
434extern int jsm_debug;
435
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439
440
441int jsm_tty_init(struct jsm_board *);
442int jsm_uart_port_init(struct jsm_board *);
443int jsm_remove_uart_port(struct jsm_board *);
444void jsm_input(struct jsm_channel *ch);
445void jsm_check_queue_flow_control(struct jsm_channel *ch);
446
447#endif
448