LXR linux/include/linux/mtd/spi-nor.h

   1/*
   2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; either version 2 of the License, or
   7 * (at your option) any later version.
   8 */
   9
  10#ifndef __LINUX_MTD_SPI_NOR_H
  11#define __LINUX_MTD_SPI_NOR_H
  12
  13#include <linux/bitops.h>
  14#include <linux/mtd/cfi.h>
  15#include <linux/mtd/mtd.h>
  16
  17/*
  18 * Manufacturer IDs
  19 *
  20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  21 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  22 */
  23#define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
  24#define SNOR_MFR_GIGADEVICE     0xc8
  25#define SNOR_MFR_INTEL          CFI_MFR_INTEL
  26#define SNOR_MFR_MICRON         CFI_MFR_ST /* ST Micro <--> Micron */
  27#define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
  28#define SNOR_MFR_SPANSION       CFI_MFR_AMD
  29#define SNOR_MFR_SST            CFI_MFR_SST
  30#define SNOR_MFR_WINBOND        0xef /* Also used by some Spansion */
  31#define SNOR_MFR_ISSI           CFI_MFR_ISSI
  32
  33/*
  34 * Note on opcode nomenclature: some opcodes have a format like
  35 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  36 * of I/O lines used for the opcode, address, and data (respectively). The
  37 * FUNCTION has an optional suffix of '4', to represent an opcode which
  38 * requires a 4-byte (32-bit) address.
  39 */
  40
  41/* Flash opcodes. */
  42#define SPINOR_OP_WREN          0x06    /* Write enable */
  43#define SPINOR_OP_RDSR          0x05    /* Read status register */
  44#define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
  45#define SPINOR_OP_RDSR2         0x3f    /* Read status register 2 */
  46#define SPINOR_OP_WRSR2         0x3e    /* Write status register 2 */
  47#define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
  48#define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
  49#define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
  50#define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
  51#define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
  52#define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
  53#define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
  54#define SPINOR_OP_PP_1_1_4      0x32    /* Quad page program */
  55#define SPINOR_OP_PP_1_4_4      0x38    /* Quad page program */
  56#define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
  57#define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
  58#define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
  59#define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
  60#define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
  61#define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
  62#define SPINOR_OP_RDSFDP        0x5a    /* Read SFDP */
  63#define SPINOR_OP_RDCR          0x35    /* Read configuration register */
  64#define SPINOR_OP_RDFSR         0x70    /* Read flag status register */
  65#define SPINOR_OP_WREAR         0xc5    /* Write Extended Address Register */
  66#define SPINOR_OP_RDEAR         0xc8    /* Read Extended Address Register */
  67
  68/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  69#define SPINOR_OP_READ_4B       0x13    /* Read data bytes (low frequency) */
  70#define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
  71#define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
  72#define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
  73#define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
  74#define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
  75#define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
  76#define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
  77#define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
  78#define SPINOR_OP_BE_4K_4B      0x21    /* Erase 4KiB block */
  79#define SPINOR_OP_BE_32K_4B     0x5c    /* Erase 32KiB block */
  80#define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
  81
  82/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  83#define SPINOR_OP_READ_1_1_1_DTR        0x0d
  84#define SPINOR_OP_READ_1_2_2_DTR        0xbd
  85#define SPINOR_OP_READ_1_4_4_DTR        0xed
  86
  87#define SPINOR_OP_READ_1_1_1_DTR_4B     0x0e
  88#define SPINOR_OP_READ_1_2_2_DTR_4B     0xbe
  89#define SPINOR_OP_READ_1_4_4_DTR_4B     0xee
  90
  91/* Used for SST flashes only. */
  92#define SPINOR_OP_BP            0x02    /* Byte program */
  93#define SPINOR_OP_WRDI          0x04    /* Write disable */
  94#define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
  95
  96#define GLOBAL_BLKPROT_UNLK     0x98    /* Clear global write protection bits */
  97
  98/* Used for S3AN flashes only */
  99#define SPINOR_OP_XSE           0x50    /* Sector erase */
 100#define SPINOR_OP_XPP           0x82    /* Page program */
 101#define SPINOR_OP_XRDSR         0xd7    /* Read status register */
 102
 103#define XSR_PAGESIZE            BIT(0)  /* Page size in Po2 or Linear */
 104#define XSR_RDY                 BIT(7)  /* Ready */
 105
 106/* Used for Macronix and Winbond flashes. */
 107#define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
 108#define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
 109
 110/* Used for Spansion flashes only. */
 111#define SPINOR_OP_BRWR          0x17    /* Bank register write */
 112#define SPINOR_OP_BRRD          0x16    /* Bank register read */
 113#define SPINOR_OP_CLSR          0x30    /* Clear status register 1 */
 114
 115/* Used for Micron flashes only. */
 116#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 117#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 118
 119/* Status Register bits. */
 120#define SR_WIP                  BIT(0)  /* Write in progress */
 121#define SR_WEL                  BIT(1)  /* Write enable latch */
 122/* meaning of other SR_* bits may differ between vendors */
 123#define SR_BP0                  BIT(2)  /* Block protect 0 */
 124#define SR_BP1                  BIT(3)  /* Block protect 1 */
 125#define SR_BP2                  BIT(4)  /* Block protect 2 */
 126#define SR_BP_BIT_OFFSET        2       /* Offset to Block protect 0 */
 127#define SR_BP_BIT_MASK          (SR_BP2 | SR_BP1 | SR_BP0)
 128
 129#define SR_TB                   BIT(5)  /* Top/Bottom protect */
 130#define SR_SRWD                 BIT(7)  /* SR write protect */
 131#define SR_BP3                  0x40
 132/* Bit to determine whether protection starts from top or bottom */
 133#define SR_BP_TB                0x20
 134#define BP_BITS_FROM_SR(sr)     (((sr) & SR_BP_BIT_MASK) >> SR_BP_BIT_OFFSET)
 135#define M25P_MAX_LOCKABLE_SECTORS       64
 136
 137/* Spansion/Cypress specific status bits */
 138#define SR_E_ERR                BIT(5)
 139#define SR_P_ERR                BIT(6)
 140
 141#define SR_QUAD_EN_MX           BIT(6)  /* Macronix Quad I/O */
 142
 143/* Enhanced Volatile Configuration Register bits */
 144#define EVCR_QUAD_EN_MICRON     BIT(7)  /* Micron Quad I/O */
 145
 146/* Flag Status Register bits */
 147#define FSR_READY               BIT(7)
 148
 149/* Configuration Register bits. */
 150#define CR_QUAD_EN_SPAN         BIT(1)  /* Spansion Quad I/O */
 151
 152/* Extended/Bank Address Register bits */
 153#define EAR_SEGMENT_MASK        0x7 /* 128 Mb segment mask */
 154
 155enum read_mode {
 156        SPI_NOR_NORMAL = 0,
 157        SPI_NOR_FAST,
 158        SPI_NOR_DUAL,
 159        SPI_NOR_QUAD,
 160};
 161
 162/* Status Register 2 bits. */
 163#define SR2_QUAD_EN_BIT7        BIT(7)
 164
 165/* Supported SPI protocols */
 166#define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
 167#define SNOR_PROTO_INST_SHIFT   16
 168#define SNOR_PROTO_INST(_nbits) \
 169        ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
 170         SNOR_PROTO_INST_MASK)
 171
 172#define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
 173#define SNOR_PROTO_ADDR_SHIFT   8
 174#define SNOR_PROTO_ADDR(_nbits) \
 175        ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
 176         SNOR_PROTO_ADDR_MASK)
 177
 178#define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
 179#define SNOR_PROTO_DATA_SHIFT   0
 180#define SNOR_PROTO_DATA(_nbits) \
 181        ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
 182         SNOR_PROTO_DATA_MASK)
 183
 184#define SNOR_PROTO_IS_DTR       BIT(24) /* Double Transfer Rate */
 185
 186#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
 187        (SNOR_PROTO_INST(_inst_nbits) |                         \
 188         SNOR_PROTO_ADDR(_addr_nbits) |                         \
 189         SNOR_PROTO_DATA(_data_nbits))
 190#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
 191        (SNOR_PROTO_IS_DTR |                                    \
 192         SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
 193
 194enum spi_nor_protocol {
 195        SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
 196        SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
 197        SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
 198        SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
 199        SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
 200        SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
 201        SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
 202        SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
 203        SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
 204        SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
 205
 206        SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
 207        SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
 208        SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
 209        SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
 210};
 211
 212static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
 213{
 214        return !!(proto & SNOR_PROTO_IS_DTR);
 215}
 216
 217static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
 218{
 219        return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
 220                SNOR_PROTO_INST_SHIFT;
 221}
 222
 223static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
 224{
 225        return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
 226                SNOR_PROTO_ADDR_SHIFT;
 227}
 228
 229static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
 230{
 231        return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
 232                SNOR_PROTO_DATA_SHIFT;
 233}
 234
 235static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
 236{
 237        return spi_nor_get_protocol_data_nbits(proto);
 238}
 239
 240#define SPI_NOR_MAX_CMD_SIZE    8
 241enum spi_nor_ops {
 242        SPI_NOR_OPS_READ = 0,
 243        SPI_NOR_OPS_WRITE,
 244        SPI_NOR_OPS_ERASE,
 245        SPI_NOR_OPS_LOCK,
 246        SPI_NOR_OPS_UNLOCK,
 247};
 248
 249enum spi_nor_option_flags {
 250        SNOR_F_USE_FSR          = BIT(0),
 251        SNOR_F_HAS_SR_TB        = BIT(1),
 252        SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
 253        SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
 254        SNOR_F_READY_XSR_RDY    = BIT(4),
 255        SNOR_F_USE_CLSR         = BIT(5),
 256};
 257
 258/**
 259 * struct spi_nor - Structure for defining a the SPI NOR layer
 260 * @mtd:                point to a mtd_info structure
 261 * @lock:               the lock for the read/write/erase/lock/unlock operations
 262 * @dev:                point to a spi device, or a spi nor controller device.
 263 * @page_size:          the page size of the SPI NOR
 264 * @addr_width:         number of address bytes
 265 * @erase_opcode:       the opcode for erasing a sector
 266 * @read_opcode:        the read opcode
 267 * @read_dummy:         the dummy needed by the read operation
 268 * @program_opcode:     the program opcode
 269 * @sst_write_second:   used by the SST write operation
 270 * @flags:              flag options for the current SPI-NOR (SNOR_F_*)
 271 * @read_proto:         the SPI protocol for read operations
 272 * @write_proto:        the SPI protocol for write operations
 273 * @reg_proto           the SPI protocol for read_reg/write_reg/erase operations
 274 * @cmd_buf:            used by the write_reg
 275 * @prepare:            [OPTIONAL] do some preparations for the
 276 *                      read/write/erase/lock/unlock operations
 277 * @unprepare:          [OPTIONAL] do some post work after the
 278 *                      read/write/erase/lock/unlock operations
 279 * @read_reg:           [DRIVER-SPECIFIC] read out the register
 280 * @write_reg:          [DRIVER-SPECIFIC] write data to the register
 281 * @read:               [DRIVER-SPECIFIC] read data from the SPI NOR
 282 * @write:              [DRIVER-SPECIFIC] write data to the SPI NOR
 283 * @erase:              [DRIVER-SPECIFIC] erase a sector of the SPI NOR
 284 *                      at the offset @offs; if not provided by the driver,
 285 *                      spi-nor will send the erase opcode via write_reg()
 286 * @flash_lock:         [FLASH-SPECIFIC] lock a region of the SPI NOR
 287 * @flash_unlock:       [FLASH-SPECIFIC] unlock a region of the SPI NOR
 288 * @flash_is_locked:    [FLASH-SPECIFIC] check if a region of the SPI NOR is
 289 *                      completely locked
 290 * @priv:               the private data
 291 */
 292struct spi_nor {
 293        struct mtd_info         mtd;
 294        struct mutex            lock;
 295        struct device           *dev;
 296        struct spi_device       *spi;
 297        u32                     page_size;
 298        u8                      addr_width;
 299        u8                      erase_opcode;
 300        u8                      read_opcode;
 301        u8                      read_dummy;
 302        u8                      program_opcode;
 303        enum read_mode          flash_read;
 304        u32                     jedec_id;
 305        u16                     curbank;
 306        u16                     n_sectors;
 307        u32                     sector_size;
 308        enum spi_nor_protocol   read_proto;
 309        enum spi_nor_protocol   write_proto;
 310        enum spi_nor_protocol   reg_proto;
 311        bool                    sst_write_second;
 312        bool                    shift;
 313        bool                    isparallel;
 314        bool                    isstacked;
 315        u32                     flags;
 316        u8                      cmd_buf[SPI_NOR_MAX_CMD_SIZE];
 317        bool                    is_lock;
 318
 319        int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 320        void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 321        int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 322        int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 323
 324        ssize_t (*read)(struct spi_nor *nor, loff_t from,
 325                        size_t len, u_char *read_buf);
 326        ssize_t (*write)(struct spi_nor *nor, loff_t to,
 327                        size_t len, const u_char *write_buf);
 328        int (*erase)(struct spi_nor *nor, loff_t offs);
 329
 330        int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 331        int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 332        int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 333
 334        void *priv;
 335};
 336
 337static inline void spi_nor_set_flash_node(struct spi_nor *nor,
 338                                          struct device_node *np)
 339{
 340        mtd_set_of_node(&nor->mtd, np);
 341}
 342
 343static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
 344{
 345        return mtd_get_of_node(&nor->mtd);
 346}
 347
 348/**
 349 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 350 * supported by the SPI controller (bus master).
 351 * @mask:               the bitmask listing all the supported hw capabilies
 352 */
 353struct spi_nor_hwcaps {
 354        u32     mask;
 355};
 356
 357/*
 358 *(Fast) Read capabilities.
 359 * MUST be ordered by priority: the higher bit position, the higher priority.
 360 * As a matter of performances, it is relevant to use Octo SPI protocols first,
 361 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 362 * (Slow) Read.
 363 */
 364#define SNOR_HWCAPS_READ_MASK           GENMASK(14, 0)
 365#define SNOR_HWCAPS_READ                BIT(0)
 366#define SNOR_HWCAPS_READ_FAST           BIT(1)
 367#define SNOR_HWCAPS_READ_1_1_1_DTR      BIT(2)
 368
 369#define SNOR_HWCAPS_READ_DUAL           GENMASK(6, 3)
 370#define SNOR_HWCAPS_READ_1_1_2          BIT(3)
 371#define SNOR_HWCAPS_READ_1_2_2          BIT(4)
 372#define SNOR_HWCAPS_READ_2_2_2          BIT(5)
 373#define SNOR_HWCAPS_READ_1_2_2_DTR      BIT(6)
 374
 375#define SNOR_HWCAPS_READ_QUAD           GENMASK(10, 7)
 376#define SNOR_HWCAPS_READ_1_1_4          BIT(7)
 377#define SNOR_HWCAPS_READ_1_4_4          BIT(8)
 378#define SNOR_HWCAPS_READ_4_4_4          BIT(9)
 379#define SNOR_HWCAPS_READ_1_4_4_DTR      BIT(10)
 380
 381#define SNOR_HWCPAS_READ_OCTO           GENMASK(14, 11)
 382#define SNOR_HWCAPS_READ_1_1_8          BIT(11)
 383#define SNOR_HWCAPS_READ_1_8_8          BIT(12)
 384#define SNOR_HWCAPS_READ_8_8_8          BIT(13)
 385#define SNOR_HWCAPS_READ_1_8_8_DTR      BIT(14)
 386
 387/*
 388 * Page Program capabilities.
 389 * MUST be ordered by priority: the higher bit position, the higher priority.
 390 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
 391 * legacy SPI 1-1-1 protocol.
 392 * Note that Dual Page Programs are not supported because there is no existing
 393 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 394 * implements such commands.
 395 */
 396#define SNOR_HWCAPS_PP_MASK     GENMASK(22, 16)
 397#define SNOR_HWCAPS_PP          BIT(16)
 398
 399#define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
 400#define SNOR_HWCAPS_PP_1_1_4    BIT(17)
 401#define SNOR_HWCAPS_PP_1_4_4    BIT(18)
 402#define SNOR_HWCAPS_PP_4_4_4    BIT(19)
 403
 404#define SNOR_HWCAPS_PP_OCTO     GENMASK(22, 20)
 405#define SNOR_HWCAPS_PP_1_1_8    BIT(20)
 406#define SNOR_HWCAPS_PP_1_8_8    BIT(21)
 407#define SNOR_HWCAPS_PP_8_8_8    BIT(22)
 408
 409/**
 410 * spi_nor_scan() - scan the SPI NOR
 411 * @nor:        the spi_nor structure
 412 * @name:       the chip type name
 413 * @hwcaps:     the hardware capabilities supported by the controller driver
 414 *
 415 * The drivers can use this fuction to scan the SPI NOR.
 416 * In the scanning, it will try to get all the necessary information to
 417 * fill the mtd_info{} and the spi_nor{}.
 418 *
 419 * The chip type name can be provided through the @name parameter.
 420 *
 421 * Return: 0 for success, others for failure.
 422 */
 423int spi_nor_scan(struct spi_nor *nor, const char *name,
 424                 const struct spi_nor_hwcaps *hwcaps);
 425
 426/**
 427 * spi_nor_shutdown() - prepare for reboot
 428 * @nor:        the spi_nor structure
 429 *
 430 * The drivers can use this fuction to get the address back to
 431 * 0 as will be required for a ROM boot.
 432 */
 433void spi_nor_shutdown(struct spi_nor *nor);
 434
 435#endif
 436