LXR linux/arch/blackfin/mach-bf527/include/mach/anomaly.h

   1/*
   2 * DO NOT EDIT THIS FILE
   3 * This file is under version control at
   4 *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
   5 * and can be replaced with that version at any time
   6 * DO NOT EDIT THIS FILE
   7 *
   8 * Copyright 2004-2011 Analog Devices Inc.
   9 * Licensed under the Clear BSD license.
  10 */
  11
  12/* This file should be up to date with:
  13 *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
  14 *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
  15 */
  16
  17#ifndef _MACH_ANOMALY_H_
  18#define _MACH_ANOMALY_H_
  19
  20/* We do not support old silicon - sorry */
  21#if __SILICON_REVISION__ < 0
  22# error will not work on BF526/BF527 silicon version
  23#endif
  24
  25#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
  26# define ANOMALY_BF526 1
  27#else
  28# define ANOMALY_BF526 0
  29#endif
  30#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
  31# define ANOMALY_BF527 1
  32#else
  33# define ANOMALY_BF527 0
  34#endif
  35
  36#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
  37#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
  38#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
  39
  40/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  41#define ANOMALY_05000074 (1)
  42/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  43#define ANOMALY_05000119 (1)
  44/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  45#define ANOMALY_05000122 (1)
  46/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  47#define ANOMALY_05000245 (1)
  48/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
  49#define ANOMALY_05000254 (1)
  50/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  51#define ANOMALY_05000265 (1)
  52/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  53#define ANOMALY_05000310 (1)
  54/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
  55#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
  56/* Incorrect Access of OTP_STATUS During otp_write() Function */
  57#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
  58/* Host DMA Boot Modes Are Not Functional */
  59#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
  60/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
  61#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
  62/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
  63#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
  64/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
  65#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
  66/* USB Calibration Value Is Not Initialized */
  67#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
  68/* USB Calibration Value to use */
  69#define ANOMALY_05000346_value 0xE510
  70/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
  71#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
  72/* Security Features Are Not Functional */
  73#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
  74/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
  75#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
  76/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
  77#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
  78/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
  79#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
  80/* Incorrect Revision Number in DSPID Register */
  81#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
  82/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  83#define ANOMALY_05000366 (1)
  84/* Incorrect Default CSEL Value in PLL_DIV */
  85#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
  86/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
  87#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
  88/* Authentication Fails To Initiate */
  89#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
  90/* Data Read From L3 Memory by USB DMA May be Corrupted */
  91#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
  92/* 8-Bit NAND Flash Boot Mode Not Functional */
  93#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
  94/* Boot from OTP Memory Not Functional */
  95#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
  96/* bfrom_SysControl() Firmware Routine Not Functional */
  97#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
  98/* Programmable Preboot Settings Not Functional */
  99#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
 100/* CRC32 Checksum Support Not Functional */
 101#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
 102/* Reset Vector Must Not Be in SDRAM Memory Space */
 103#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
 104/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
 105#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
 106/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
 107#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
 108/* Log Buffer Not Functional */
 109#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
 110/* Hook Routine Not Functional */
 111#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
 112/* Header Indirect Bit Not Functional */
 113#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
 114/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
 115#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
 116/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
 117#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
 118/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
 119#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
 120/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
 121#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
 122/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
 123#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
 124/* Lockbox SESR Disallows Certain User Interrupts */
 125#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
 126/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
 127#define ANOMALY_05000405 (1)
 128/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
 129#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
 130/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
 131#define ANOMALY_05000408 (1)
 132/* Lockbox firmware leaves MDMA0 channel enabled */
 133#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
 134/* Incorrect Default Internal Voltage Regulator Setting */
 135#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 136/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
 137#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
 138/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
 139#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 140/* DEB2_URGENT Bit Not Functional */
 141#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
 142/* Speculative Fetches Can Cause Undesired External FIFO Operations */
 143#define ANOMALY_05000416 (1)
 144/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
 145#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
 146/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
 147#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
 148/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
 149#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
 150/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
 151#define ANOMALY_05000421 (1)
 152/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
 153#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
 154/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
 155#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
 156/* Internal Voltage Regulator Not Trimmed */
 157#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
 158/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
 159#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
 160/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 161#define ANOMALY_05000426 (1)
 162/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
 163#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
 164/* Software System Reset Corrupts PLL_LOCKCNT Register */
 165#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
 166/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
 167#define ANOMALY_05000431 (1)
 168/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
 169#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
 170/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
 171#define ANOMALY_05000434 (1)
 172/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
 173#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
 174/* Preboot Cannot be Used to Alter the PLL_DIV Register */
 175#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
 176/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
 177#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
 178/* OTP Write Accesses Not Supported */
 179#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
 180/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 181#define ANOMALY_05000443 (1)
 182/* The WURESET Bit in the SYSCR Register is not Functional */
 183#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
 184/* USB DMA Short Packet Data Corruption */
 185#define ANOMALY_05000450 (1)
 186/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
 187#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
 188/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
 189#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 190/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 191#define ANOMALY_05000456 (1)
 192/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 193#define ANOMALY_05000457 (1)
 194/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
 195#define ANOMALY_05000460 (1)
 196/* False Hardware Error when RETI Points to Invalid Memory */
 197#define ANOMALY_05000461 (1)
 198/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
 199#define ANOMALY_05000462 (1)
 200/* USB Rx DMA Hang */
 201#define ANOMALY_05000465 (1)
 202/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
 203#define ANOMALY_05000466 (1)
 204/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
 205#define ANOMALY_05000467 (1)
 206/* PLL Latches Incorrect Settings During Reset */
 207#define ANOMALY_05000469 (1)
 208/* Incorrect Default MSEL Value in PLL_CTL */
 209#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
 210/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
 211#define ANOMALY_05000473 (1)
 212/* Possible Lockup Condition when Modifying PLL from External Memory */
 213#define ANOMALY_05000475 (1)
 214/* TESTSET Instruction Cannot Be Interrupted */
 215#define ANOMALY_05000477 (1)
 216/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 217#define ANOMALY_05000481 (1)
 218/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
 219#define ANOMALY_05000483 (1)
 220/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
 221#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
 222/* The CODEC Zero-Cross Detect Feature is not Functional */
 223#define ANOMALY_05000487 (1)
 224/* SPI Master Boot Can Fail Under Certain Conditions */
 225#define ANOMALY_05000490 (1)
 226/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
 227#define ANOMALY_05000491 (1)
 228/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
 229#define ANOMALY_05000494 (1)
 230/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
 231#define ANOMALY_05000498 (1)
 232/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
 233#define ANOMALY_05000501 (1)
 234
 235/* Anomalies that don't exist on this proc */
 236#define ANOMALY_05000099 (0)
 237#define ANOMALY_05000120 (0)
 238#define ANOMALY_05000125 (0)
 239#define ANOMALY_05000149 (0)
 240#define ANOMALY_05000158 (0)
 241#define ANOMALY_05000171 (0)
 242#define ANOMALY_05000179 (0)
 243#define ANOMALY_05000182 (0)
 244#define ANOMALY_05000183 (0)
 245#define ANOMALY_05000189 (0)
 246#define ANOMALY_05000198 (0)
 247#define ANOMALY_05000202 (0)
 248#define ANOMALY_05000215 (0)
 249#define ANOMALY_05000219 (0)
 250#define ANOMALY_05000220 (0)
 251#define ANOMALY_05000227 (0)
 252#define ANOMALY_05000230 (0)
 253#define ANOMALY_05000231 (0)
 254#define ANOMALY_05000233 (0)
 255#define ANOMALY_05000234 (0)
 256#define ANOMALY_05000242 (0)
 257#define ANOMALY_05000244 (0)
 258#define ANOMALY_05000248 (0)
 259#define ANOMALY_05000250 (0)
 260#define ANOMALY_05000257 (0)
 261#define ANOMALY_05000261 (0)
 262#define ANOMALY_05000263 (0)
 263#define ANOMALY_05000266 (0)
 264#define ANOMALY_05000273 (0)
 265#define ANOMALY_05000274 (0)
 266#define ANOMALY_05000278 (0)
 267#define ANOMALY_05000281 (0)
 268#define ANOMALY_05000283 (0)
 269#define ANOMALY_05000285 (0)
 270#define ANOMALY_05000287 (0)
 271#define ANOMALY_05000301 (0)
 272#define ANOMALY_05000305 (0)
 273#define ANOMALY_05000307 (0)
 274#define ANOMALY_05000311 (0)
 275#define ANOMALY_05000312 (0)
 276#define ANOMALY_05000315 (0)
 277#define ANOMALY_05000323 (0)
 278#define ANOMALY_05000362 (1)
 279#define ANOMALY_05000363 (0)
 280#define ANOMALY_05000383 (0)
 281#define ANOMALY_05000400 (0)
 282#define ANOMALY_05000402 (0)
 283#define ANOMALY_05000412 (0)
 284#define ANOMALY_05000447 (0)
 285#define ANOMALY_05000448 (0)
 286#define ANOMALY_05000474 (0)
 287#define ANOMALY_05000480 (0)
 288#define ANOMALY_16000030 (0)
 289
 290#endif
 291