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11#include <linux/cpuhotplug.h>
12#include <linux/init.h>
13#include <linux/percpu.h>
14#include <linux/slab.h>
15
16#include <asm/asm-offsets.h>
17#include <asm/cacheflush.h>
18#include <asm/cacheops.h>
19#include <asm/idle.h>
20#include <asm/mips-cps.h>
21#include <asm/mipsmtregs.h>
22#include <asm/pm.h>
23#include <asm/pm-cps.h>
24#include <asm/smp-cps.h>
25#include <asm/uasm.h>
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41typedef unsigned (*cps_nc_entry_fn)(unsigned online, u32 *nc_ready_count);
42
43
44
45
46
47static DEFINE_PER_CPU_READ_MOSTLY(cps_nc_entry_fn[CPS_PM_STATE_COUNT],
48 nc_asm_enter);
49
50
51static DECLARE_BITMAP(state_support, CPS_PM_STATE_COUNT);
52
53
54
55
56
57static DEFINE_PER_CPU_ALIGNED(u32*, ready_count);
58
59
60static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled);
61
62
63
64
65
66static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier);
67
68
69DEFINE_PER_CPU_ALIGNED(struct mips_static_suspend_state, cps_cpu_state);
70
71
72static struct uasm_label labels[32];
73static struct uasm_reloc relocs[32];
74
75enum mips_reg {
76 zero, at, v0, v1, a0, a1, a2, a3,
77 t0, t1, t2, t3, t4, t5, t6, t7,
78 s0, s1, s2, s3, s4, s5, s6, s7,
79 t8, t9, k0, k1, gp, sp, fp, ra,
80};
81
82bool cps_pm_support_state(enum cps_pm_state state)
83{
84 return test_bit(state, state_support);
85}
86
87static void coupled_barrier(atomic_t *a, unsigned online)
88{
89
90
91
92
93
94
95 if (!coupled_coherence)
96 return;
97
98 smp_mb__before_atomic();
99 atomic_inc(a);
100
101 while (atomic_read(a) < online)
102 cpu_relax();
103
104 if (atomic_inc_return(a) == online * 2) {
105 atomic_set(a, 0);
106 return;
107 }
108
109 while (atomic_read(a) > online)
110 cpu_relax();
111}
112
113int cps_pm_enter_state(enum cps_pm_state state)
114{
115 unsigned cpu = smp_processor_id();
116 unsigned core = cpu_core(¤t_cpu_data);
117 unsigned online, left;
118 cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
119 u32 *core_ready_count, *nc_core_ready_count;
120 void *nc_addr;
121 cps_nc_entry_fn entry;
122 struct core_boot_config *core_cfg;
123 struct vpe_boot_config *vpe_cfg;
124
125
126 entry = per_cpu(nc_asm_enter, core)[state];
127 if (!entry)
128 return -EINVAL;
129
130
131#if defined(CONFIG_MIPS_MT) || defined(CONFIG_CPU_MIPSR6)
132 if (cpu_online(cpu)) {
133 cpumask_and(coupled_mask, cpu_online_mask,
134 &cpu_sibling_map[cpu]);
135 online = cpumask_weight(coupled_mask);
136 cpumask_clear_cpu(cpu, coupled_mask);
137 } else
138#endif
139 {
140 cpumask_clear(coupled_mask);
141 online = 1;
142 }
143
144
145 if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
146
147 if (!mips_cps_smp_in_use())
148 return -EINVAL;
149
150 core_cfg = &mips_cps_core_bootcfg[core];
151 vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)];
152 vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
153 vpe_cfg->gp = (unsigned long)current_thread_info();
154 vpe_cfg->sp = 0;
155 }
156
157
158 cpumask_clear_cpu(cpu, &cpu_coherent_mask);
159 smp_mb__after_atomic();
160
161
162 core_ready_count = per_cpu(ready_count, core);
163 nc_addr = kmap_noncoherent(virt_to_page(core_ready_count),
164 (unsigned long)core_ready_count);
165 nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK);
166 nc_core_ready_count = nc_addr;
167
168
169 ACCESS_ONCE(*nc_core_ready_count) = 0;
170 coupled_barrier(&per_cpu(pm_barrier, core), online);
171
172
173 left = entry(online, nc_core_ready_count);
174
175
176 kunmap_noncoherent();
177
178
179 cpumask_set_cpu(cpu, &cpu_coherent_mask);
180
181
182
183
184
185
186
187
188
189 if (coupled_coherence && (state == CPS_PM_NC_WAIT) && (left == online))
190 arch_send_call_function_ipi_mask(coupled_mask);
191
192 return 0;
193}
194
195static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl,
196 struct uasm_reloc **pr,
197 const struct cache_desc *cache,
198 unsigned op, int lbl)
199{
200 unsigned cache_size = cache->ways << cache->waybit;
201 unsigned i;
202 const unsigned unroll_lines = 32;
203
204
205 if (cache->flags & MIPS_CACHE_NOT_PRESENT)
206 return;
207
208
209 UASM_i_LA(pp, t0, (long)CKSEG0);
210
211
212 if (cache_size < 0x8000)
213 uasm_i_addiu(pp, t1, t0, cache_size);
214 else
215 UASM_i_LA(pp, t1, (long)(CKSEG0 + cache_size));
216
217
218 uasm_build_label(pl, *pp, lbl);
219
220
221 for (i = 0; i < unroll_lines; i++) {
222 if (cpu_has_mips_r6) {
223 uasm_i_cache(pp, op, 0, t0);
224 uasm_i_addiu(pp, t0, t0, cache->linesz);
225 } else {
226 uasm_i_cache(pp, op, i * cache->linesz, t0);
227 }
228 }
229
230 if (!cpu_has_mips_r6)
231
232 uasm_i_addiu(pp, t0, t0, unroll_lines * cache->linesz);
233
234
235 uasm_il_bne(pp, pr, t0, t1, lbl);
236 uasm_i_nop(pp);
237}
238
239static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
240 struct uasm_reloc **pr,
241 const struct cpuinfo_mips *cpu_info,
242 int lbl)
243{
244 unsigned i, fsb_size = 8;
245 unsigned num_loads = (fsb_size * 3) / 2;
246 unsigned line_stride = 2;
247 unsigned line_size = cpu_info->dcache.linesz;
248 unsigned perf_counter, perf_event;
249 unsigned revision = cpu_info->processor_id & PRID_REV_MASK;
250
251
252
253
254
255 switch (__get_cpu_type(cpu_info->cputype)) {
256 case CPU_INTERAPTIV:
257 perf_counter = 1;
258 perf_event = 51;
259 break;
260
261 case CPU_PROAPTIV:
262
263 if (revision >= PRID_REV_ENCODE_332(1, 1, 0))
264 return 0;
265
266
267 return -1;
268
269 default:
270
271 return 0;
272 }
273
274
275
276
277
278
279
280
281 uasm_i_mfc0(pp, t2, 25, (perf_counter * 2) + 0);
282 uasm_i_mfc0(pp, t3, 25, (perf_counter * 2) + 1);
283
284
285 uasm_i_addiu(pp, t0, zero, (perf_event << 5) | 0xf);
286 uasm_i_mtc0(pp, t0, 25, (perf_counter * 2) + 0);
287 uasm_i_ehb(pp);
288 uasm_i_mtc0(pp, zero, 25, (perf_counter * 2) + 1);
289 uasm_i_ehb(pp);
290
291
292 UASM_i_LA(pp, t0, (long)CKSEG0);
293
294
295 uasm_build_label(pl, *pp, lbl);
296
297
298 for (i = 0; i < num_loads; i++)
299 uasm_i_lw(pp, zero, i * line_size * line_stride, t0);
300
301
302
303
304
305 for (i = 0; i < num_loads; i++) {
306 uasm_i_cache(pp, Hit_Invalidate_D,
307 i * line_size * line_stride, t0);
308 uasm_i_cache(pp, Hit_Writeback_Inv_SD,
309 i * line_size * line_stride, t0);
310 }
311
312
313 uasm_i_sync(pp, STYPE_SYNC);
314 uasm_i_ehb(pp);
315
316
317 uasm_i_mfc0(pp, t1, 25, (perf_counter * 2) + 1);
318
319
320 uasm_il_beqz(pp, pr, t1, lbl);
321 uasm_i_nop(pp);
322
323
324 uasm_i_mtc0(pp, t2, 25, (perf_counter * 2) + 0);
325 uasm_i_ehb(pp);
326 uasm_i_mtc0(pp, t3, 25, (perf_counter * 2) + 1);
327 uasm_i_ehb(pp);
328
329 return 0;
330}
331
332static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl,
333 struct uasm_reloc **pr,
334 unsigned r_addr, int lbl)
335{
336 uasm_i_lui(pp, t0, uasm_rel_hi(0x80000000));
337 uasm_build_label(pl, *pp, lbl);
338 uasm_i_ll(pp, t1, 0, r_addr);
339 uasm_i_or(pp, t1, t1, t0);
340 uasm_i_sc(pp, t1, 0, r_addr);
341 uasm_il_beqz(pp, pr, t1, lbl);
342 uasm_i_nop(pp);
343}
344
345static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
346{
347 struct uasm_label *l = labels;
348 struct uasm_reloc *r = relocs;
349 u32 *buf, *p;
350 const unsigned r_online = a0;
351 const unsigned r_nc_count = a1;
352 const unsigned r_pcohctl = t7;
353 const unsigned max_instrs = 256;
354 unsigned cpc_cmd;
355 int err;
356 enum {
357 lbl_incready = 1,
358 lbl_poll_cont,
359 lbl_secondary_hang,
360 lbl_disable_coherence,
361 lbl_flush_fsb,
362 lbl_invicache,
363 lbl_flushdcache,
364 lbl_hang,
365 lbl_set_cont,
366 lbl_secondary_cont,
367 lbl_decready,
368 };
369
370
371 p = buf = kcalloc(max_instrs, sizeof(u32), GFP_KERNEL);
372 if (!buf)
373 return NULL;
374
375
376 memset(labels, 0, sizeof(labels));
377 memset(relocs, 0, sizeof(relocs));
378
379 if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
380
381 if (!mips_cps_smp_in_use())
382 goto out_err;
383
384
385
386
387
388
389 UASM_i_LA(&p, t0, (long)mips_cps_pm_save);
390 uasm_i_jalr(&p, v0, t0);
391 uasm_i_nop(&p);
392 }
393
394
395
396
397
398
399 UASM_i_LA(&p, r_pcohctl, (long)addr_gcr_cl_coherence());
400
401 if (coupled_coherence) {
402
403 uasm_i_sync(&p, STYPE_SYNC_MB);
404 uasm_build_label(&l, p, lbl_incready);
405 uasm_i_ll(&p, t1, 0, r_nc_count);
406 uasm_i_addiu(&p, t2, t1, 1);
407 uasm_i_sc(&p, t2, 0, r_nc_count);
408 uasm_il_beqz(&p, &r, t2, lbl_incready);
409 uasm_i_addiu(&p, t1, t1, 1);
410
411
412 uasm_i_sync(&p, STYPE_SYNC_MB);
413
414
415
416
417
418 uasm_il_beq(&p, &r, t1, r_online, lbl_disable_coherence);
419 uasm_i_nop(&p);
420
421 if (state < CPS_PM_POWER_GATED) {
422
423
424
425
426
427
428 uasm_i_addiu(&p, t1, zero, -1);
429 uasm_build_label(&l, p, lbl_poll_cont);
430 uasm_i_lw(&p, t0, 0, r_nc_count);
431 uasm_il_bltz(&p, &r, t0, lbl_secondary_cont);
432 uasm_i_ehb(&p);
433 if (cpu_has_mipsmt)
434 uasm_i_yield(&p, zero, t1);
435 uasm_il_b(&p, &r, lbl_poll_cont);
436 uasm_i_nop(&p);
437 } else {
438
439
440
441
442 if (cpu_has_mipsmt) {
443
444 uasm_i_addiu(&p, t0, zero, TCHALT_H);
445 uasm_i_mtc0(&p, t0, 2, 4);
446 } else if (cpu_has_vp) {
447
448 unsigned int vpe_id;
449
450 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
451 uasm_i_addiu(&p, t0, zero, 1 << vpe_id);
452 UASM_i_LA(&p, t1, (long)addr_cpc_cl_vp_stop());
453 uasm_i_sw(&p, t0, 0, t1);
454 } else {
455 BUG();
456 }
457 uasm_build_label(&l, p, lbl_secondary_hang);
458 uasm_il_b(&p, &r, lbl_secondary_hang);
459 uasm_i_nop(&p);
460 }
461 }
462
463
464
465
466
467
468 uasm_build_label(&l, p, lbl_disable_coherence);
469
470
471 cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].icache,
472 Index_Invalidate_I, lbl_invicache);
473
474
475 cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
476 Index_Writeback_Inv_D, lbl_flushdcache);
477
478
479 uasm_i_sync(&p, STYPE_SYNC);
480 uasm_i_ehb(&p);
481
482 if (mips_cm_revision() < CM_REV_CM3) {
483
484
485
486
487
488 uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
489 uasm_i_sw(&p, t0, 0, r_pcohctl);
490 uasm_i_lw(&p, t0, 0, r_pcohctl);
491
492
493 uasm_i_sync(&p, STYPE_SYNC);
494 uasm_i_ehb(&p);
495 }
496
497
498 uasm_i_sw(&p, zero, 0, r_pcohctl);
499 uasm_i_lw(&p, t0, 0, r_pcohctl);
500
501 if (state >= CPS_PM_CLOCK_GATED) {
502 err = cps_gen_flush_fsb(&p, &l, &r, &cpu_data[cpu],
503 lbl_flush_fsb);
504 if (err)
505 goto out_err;
506
507
508 switch (state) {
509 case CPS_PM_CLOCK_GATED:
510 cpc_cmd = CPC_Cx_CMD_CLOCKOFF;
511 break;
512 case CPS_PM_POWER_GATED:
513 cpc_cmd = CPC_Cx_CMD_PWRDOWN;
514 break;
515 default:
516 BUG();
517 goto out_err;
518 }
519
520
521 UASM_i_LA(&p, t0, (long)addr_cpc_cl_cmd());
522 uasm_i_addiu(&p, t1, zero, cpc_cmd);
523 uasm_i_sw(&p, t1, 0, t0);
524
525 if (state == CPS_PM_POWER_GATED) {
526
527 uasm_build_label(&l, p, lbl_hang);
528 uasm_il_b(&p, &r, lbl_hang);
529 uasm_i_nop(&p);
530
531
532
533
534
535
536 goto gen_done;
537 }
538
539
540 uasm_i_sync(&p, STYPE_SYNC);
541 uasm_i_ehb(&p);
542 }
543
544 if (state == CPS_PM_NC_WAIT) {
545
546
547
548
549
550 if (coupled_coherence)
551 cps_gen_set_top_bit(&p, &l, &r, r_nc_count,
552 lbl_set_cont);
553
554
555
556
557
558
559 uasm_build_label(&l, p, lbl_secondary_cont);
560
561
562 uasm_i_wait(&p, 0);
563 }
564
565
566
567
568
569
570 uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3
571 ? CM_GCR_Cx_COHERENCE_COHDOMAINEN
572 : CM3_GCR_Cx_COHERENCE_COHEN);
573
574 uasm_i_sw(&p, t0, 0, r_pcohctl);
575 uasm_i_lw(&p, t0, 0, r_pcohctl);
576
577
578 uasm_i_sync(&p, STYPE_SYNC);
579 uasm_i_ehb(&p);
580
581 if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
582
583 uasm_build_label(&l, p, lbl_decready);
584 uasm_i_sync(&p, STYPE_SYNC_MB);
585 uasm_i_ll(&p, t1, 0, r_nc_count);
586 uasm_i_addiu(&p, t2, t1, -1);
587 uasm_i_sc(&p, t2, 0, r_nc_count);
588 uasm_il_beqz(&p, &r, t2, lbl_decready);
589 uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
590
591
592 uasm_i_sync(&p, STYPE_SYNC_MB);
593 }
594
595 if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
596
597
598
599
600
601 cps_gen_set_top_bit(&p, &l, &r, r_nc_count, lbl_set_cont);
602
603
604
605
606
607
608
609
610
611 uasm_build_label(&l, p, lbl_secondary_cont);
612
613
614 uasm_i_sync(&p, STYPE_SYNC_MB);
615 }
616
617
618 uasm_i_jr(&p, ra);
619 uasm_i_nop(&p);
620
621gen_done:
622
623 BUG_ON((p - buf) > max_instrs);
624 BUG_ON((l - labels) > ARRAY_SIZE(labels));
625 BUG_ON((r - relocs) > ARRAY_SIZE(relocs));
626
627
628 uasm_resolve_relocs(relocs, labels);
629
630
631 local_flush_icache_range((unsigned long)buf, (unsigned long)p);
632
633 return buf;
634out_err:
635 kfree(buf);
636 return NULL;
637}
638
639static int cps_pm_online_cpu(unsigned int cpu)
640{
641 enum cps_pm_state state;
642 unsigned core = cpu_core(&cpu_data[cpu]);
643 void *entry_fn, *core_rc;
644
645 for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
646 if (per_cpu(nc_asm_enter, core)[state])
647 continue;
648 if (!test_bit(state, state_support))
649 continue;
650
651 entry_fn = cps_gen_entry_code(cpu, state);
652 if (!entry_fn) {
653 pr_err("Failed to generate core %u state %u entry\n",
654 core, state);
655 clear_bit(state, state_support);
656 }
657
658 per_cpu(nc_asm_enter, core)[state] = entry_fn;
659 }
660
661 if (!per_cpu(ready_count, core)) {
662 core_rc = kmalloc(sizeof(u32), GFP_KERNEL);
663 if (!core_rc) {
664 pr_err("Failed allocate core %u ready_count\n", core);
665 return -ENOMEM;
666 }
667 per_cpu(ready_count, core) = core_rc;
668 }
669
670 return 0;
671}
672
673static int __init cps_pm_init(void)
674{
675
676 if (!mips_cm_present()) {
677 pr_warn("pm-cps: no CM, non-coherent states unavailable\n");
678 return 0;
679 }
680
681
682
683
684
685
686 if (cpu_wait == r4k_wait_irqoff)
687 set_bit(CPS_PM_NC_WAIT, state_support);
688 else
689 pr_warn("pm-cps: non-coherent wait unavailable\n");
690
691
692 if (mips_cpc_present()) {
693
694 if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL)
695 set_bit(CPS_PM_CLOCK_GATED, state_support);
696 else
697 pr_warn("pm-cps: CPC does not support clock gating\n");
698
699
700 if (mips_cps_smp_in_use())
701 set_bit(CPS_PM_POWER_GATED, state_support);
702 else
703 pr_warn("pm-cps: CPS SMP not in use, power gating unavailable\n");
704 } else {
705 pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
706 }
707
708 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
709 cps_pm_online_cpu, NULL);
710}
711arch_initcall(cps_pm_init);
712