LXR linux/arch/sh/kernel/cpu/sh4a/clock-sh7757.c

   1/*
   2 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
   3 *
   4 * SH7757 support for the clock framework
   5 *
   6 *  Copyright (C) 2009-2010  Renesas Solutions Corp.
   7 *
   8 * This file is subject to the terms and conditions of the GNU General Public
   9 * License.  See the file "COPYING" in the main directory of this archive
  10 * for more details.
  11 */
  12#include <linux/init.h>
  13#include <linux/kernel.h>
  14#include <linux/io.h>
  15#include <linux/clkdev.h>
  16#include <asm/clock.h>
  17#include <asm/freq.h>
  18
  19/*
  20 * Default rate for the root input clock, reset this with clk_set_rate()
  21 * from the platform code.
  22 */
  23static struct clk extal_clk = {
  24        .rate           = 48000000,
  25};
  26
  27static unsigned long pll_recalc(struct clk *clk)
  28{
  29        int multiplier;
  30
  31        multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
  32
  33        return clk->parent->rate * multiplier;
  34}
  35
  36static struct sh_clk_ops pll_clk_ops = {
  37        .recalc         = pll_recalc,
  38};
  39
  40static struct clk pll_clk = {
  41        .ops            = &pll_clk_ops,
  42        .parent         = &extal_clk,
  43        .flags          = CLK_ENABLE_ON_INIT,
  44};
  45
  46static struct clk *clks[] = {
  47        &extal_clk,
  48        &pll_clk,
  49};
  50
  51static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
  52                               1, 1, 1, 16, 1, 24, 1, 1 };
  53
  54static struct clk_div_mult_table div4_div_mult_table = {
  55        .divisors = div2,
  56        .nr_divisors = ARRAY_SIZE(div2),
  57};
  58
  59static struct clk_div4_table div4_table = {
  60        .div_mult_table = &div4_div_mult_table,
  61};
  62
  63enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
  64
  65#define DIV4(_bit, _mask, _flags) \
  66  SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
  67
  68struct clk div4_clks[DIV4_NR] = {
  69        /*
  70         * P clock is always enable, because some P clock modules is used
  71         * by Host PC.
  72         */
  73        [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
  74        [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
  75        [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
  76};
  77
  78#define MSTPCR0         0xffc80030
  79#define MSTPCR1         0xffc80034
  80#define MSTPCR2         0xffc10028
  81
  82enum { MSTP004, MSTP000, MSTP127, MSTP114, MSTP113, MSTP112,
  83       MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
  84       MSTP_NR };
  85
  86static struct clk mstp_clks[MSTP_NR] = {
  87        /* MSTPCR0 */
  88        [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
  89        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
  90
  91        /* MSTPCR1 */
  92        [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
  93        [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
  94        [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
  95        [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
  96        [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
  97        [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
  98        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
  99        [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
 100
 101        /* MSTPCR2 */
 102        [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
 103};
 104
 105static struct clk_lookup lookups[] = {
 106        /* main clocks */
 107        CLKDEV_CON_ID("extal", &extal_clk),
 108        CLKDEV_CON_ID("pll_clk", &pll_clk),
 109
 110        /* DIV4 clocks */
 111        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 112        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 113        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 114
 115        /* MSTP32 clocks */
 116        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
 117        CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
 118        CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
 119        CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
 120        CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
 121        CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
 122        CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
 123        CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
 124        CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
 125
 126        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
 127        CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
 128        CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP112]),
 129        CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP111]),
 130        CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
 131
 132        CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP103]),
 133        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
 134        CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
 135        CLKDEV_DEV_ID("rspi.2", &mstp_clks[MSTP127]),
 136};
 137
 138int __init arch_clk_init(void)
 139{
 140        int i, ret = 0;
 141
 142        for (i = 0; i < ARRAY_SIZE(clks); i++)
 143                ret |= clk_register(clks[i]);
 144
 145        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 146
 147        if (!ret)
 148                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 149                                           &div4_table);
 150        if (!ret)
 151                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 152
 153        return ret;
 154}
 155
 156